3253 Normative Rules: Includes 205 Implementation-Defined Behaviors (119 No Category, 82 WARL, 4 WLRL)
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| a_aq_rl_bits | each atomic instruction has two bits, aq and rl, used to specify additional memory ordering constraints as viewed by other RISC-V harts. |
norm:a_aq_rl_bits |
| a_domain_specific_ordering | The bits order accesses to one of the two address domains, memory or I/O, depending on which address domain the atomic instruction is accessing. No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used to order across both domains. |
norm:a_domain_specific_ordering |
| a_no_aq_rl | If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation. |
norm:a_no_aq_rl |
| a_acquire_semantics | If only the aq bit is set, the atomic memory operation is treated as an acquire access, i.e., no following memory operations on this RISC-V hart can be observed to take place before the acquire memory operation. |
norm:a_acquire_semantics |
| a_release_semantics | If only the rl bit is set, the atomic memory operation is treated as a release access, i.e., the release memory operation cannot be observed to take place before any earlier memory operations on this RISC-V hart. |
norm:a_release_semantics |
| a_seq_cst_semantics | If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain. |
norm:a_seq_cst_semantics |
| lr_w_op | LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that subsumes the bytes in the addressed word. |
norm:lr_w_op |
| sc_w_success | SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. |
norm:sc_w_success |
| sc_w_failure | If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd. |
norm:sc_w_failure |
| sc_retire_permission | No SC.W instruction shall retire unless it passes memory permission checks, | norm:sc_retire_permission |
| sc_failed_side_effects | but it is UNSPECIFIED whether any side effects of implicit address translation and protection memory accesses (such as setting a page-table entry D bit) occur on a failed SC.W. |
norm:sc_failed_side_effects |
| sc_failed_as_store | For the purposes of memory protection, a failed SC.W may be treated like a store. |
norm:sc_failed_as_store |
| sc_reservation_invalidate | Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart. |
norm:sc_reservation_invalidate |
| lr_sc_rv64 | LR.D and SC.D act analogously on doublewords and are only available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd. |
norm:lr_sc_rv64 |
| sc_failure_code | The failure code with value 1 encodes an unspecified failure. Other failure codes are reserved at this time. Portable software should only assume the failure code will be non-zero. |
norm:sc_failure_code |
| LR_SC_ALIGNMENT | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| For LR and SC, the Zalrsc extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words). If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated. |
norm:lr_sc_alignment | |
| LR_RESERVATION_SET_SIZE | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword. |
norm:lr_reservation_set_size | |
| sc_pairs_latest_lr | An SC can only pair with the most recent LR in program order. |
norm:sc_pairs_latest_lr |
| sc_success_conditions | An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order. |
norm:sc_success_conditions |
| sc_device_write_failure | An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC. |
norm:sc_device_write_failure |
| sc_addr_not_in_reservation_fail | The SC must fail if the address is not within the reservation set of the most recent LR in program order. |
norm:sc_addr_not_in_reservation_fail |
| sc_other_hart_store_fail | The SC must fail if a store to the reservation set from another hart can be observed to occur between the LR and SC. |
norm:sc_other_hart_store_fail |
| sc_other_device_write_fail | The SC must fail if a write from some other device to the bytes accessed by the LR can be observed to occur between the LR and SC. |
norm:sc_other_device_write_fail |
| sc_intervening_sc_fail | An SC must fail if there is another SC (to any address) between the LR and the SC in program order. |
norm:sc_intervening_sc_fail |
| lr_sc_atomicity_axiom | The precise statement of the atomicity requirements for successful LR/SC sequences is defined by the Atomicity Axiom in rvwmo. |
norm:lr_sc_atomicity_axiom |
| sc_not_observable_before_lr | An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation. |
norm:sc_not_observable_before_lr |
| lr_sc_aq_rl_software_rule | Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance. |
norm:lr_sc_aq_rl_software_rule |
| constrained_lrsc_loop_size | The loop comprises only an LR/SC sequence and code to retry the sequence in the case of failure, and must comprise at most 16 instructions placed sequentially in memory. |
norm:constrained_lrsc_loop_size |
| constrained_lrsc_instruction_set | An LR/SC sequence begins with an LR instruction and ends with an SC instruction. The dynamic code executed between the LR and SC instructions can only contain instructions from the base ''I'' instruction set, excluding loads, stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM instructions. |
norm:constrained_lrsc_instruction_set |
| constrained_lrsc_compressed_allowed | Compressed forms of the aforementioned ''I'' instructions in the C (hence Zca) and Zcb extensions are also permitted. |
norm:constrained_lrsc_compressed_allowed |
| constrained_lrsc_retry_code | The code to retry a failing LR/SC sequence can contain backwards jumps and/or branches to repeat the LR/SC sequence, but otherwise has the same constraint as the code between the LR and SC. |
norm:constrained_lrsc_retry_code |
| lrsc_eventuality_region | The LR and SC addresses must lie within a memory region with the LR/SC eventuality property. The execution environment is responsible for communicating which regions have this property. |
norm:lrsc_eventuality_region |
| lrsc_same_address_and_size | The SC must be to the same effective address and of the same data size as the latest LR executed by the same hart. |
norm:lrsc_same_address_and_size |
| unconstrained_lrsc_no_progress | LR/SC sequences that do not lie within constrained LR/SC loops are unconstrained. Unconstrained LR/SC sequences might succeed on some attempts on some implementations, but might never succeed on other implementations. |
norm:unconstrained_lrsc_no_progress |
| amo_operand_size | AMOs can either operate on doublewords (RV64 only) or words in memory. For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2. |
norm:amo_operand_size |
| amo_alignment | For AMOs, the Zaamo extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words). |
norm:amo_alignment |
| MISALIGNED_ATOMICITY_GRANULE_SIZE | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The misaligned atomicity granule PMA, defined in Volume II of this manual, optionally relaxes this alignment requirement. If present, the misaligned atomicity granule PMA specifies the size of a misaligned atomicity granule, a power-of-two number of bytes. The misaligned atomicity granule PMA applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions, and compressed encodings thereof. For an instruction in that set, if all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO--i.e., it will execute atomically. |
norm:misaligned_atomicity_granule_size | |
| amo_release_consistency | To help implement multiprocessor synchronization, the AMOs optionally provide release consistency semantics. If the aq bit is set, then no later memory operations in this RISC-V hart can be observed to take place before the AMO. Conversely, if the rl bit is set, then other RISC-V harts will not observe the AMO before memory accesses preceding the AMO in this RISC-V hart. Setting both the aq and the rl bit on an AMO makes the sequence sequentially consistent, meaning that it cannot be reordered with earlier or later memory operations from the same hart. |
norm:amo_release_consistency |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| fcvt-bf16-s_op | Narrowing convert FP32 value to a BF16 value. Round according to the RM field. | norm:fcvt-bf16-s_op |
| fcvt-s-bf16_op | Converts a BF16 value to an FP32 value. The conversion is exact. | norm:fcvt-s-bf16_op |
| vfncvtbf16-f-f-w_op | Narrowing convert from FP32 to BF16. Round according to the frm register. | norm:vfncvtbf16-f-f-w_op |
| vfncvtbf16-f-f-w_sew_rsv | SEW is any value other than 16 | norm:vfncvtbf16-f-f-w_sew_rsv |
| vfwcvtbf16-f-f-v_op | Widening convert from BF16 to FP32. The conversion is exact. | norm:vfwcvtbf16-f-f-v_op |
| vfwcvtbf16-f-f-v_sew_rsv | SEW is any value other than 16 | norm:vfwcvtbf16-f-f-v_sew_rsv |
| vfwmaccbf16_vv_op | This instruction performs a widening fused multiply-accumulate operation, where each pair of BF16 values are multiplied and their unrounded product is added to the corresponding FP32 accumulate value. The sum is rounded according to the frm register. | norm:vfwmaccbf16_op |
| In the vector-vector version, the BF16 elements are read from vs1 and vs2 and FP32 accumulate value is read from vd. The FP32 result is written to the destination register vd. | norm:vfwmaccbf16_vv | |
| All of the BF16 instructions in the extensions defined in this specification (i.e., Zfbfmin, Zvfbfmin, and Zvfbfwma) fully support subnormal numbers. That is, instructions are able to accept subnormal values as inputs and they can produce subnormal results. | norm:bf16_subnorm | |
| vfwmaccbf16_vf_op | This instruction performs a widening fused multiply-accumulate operation, where each pair of BF16 values are multiplied and their unrounded product is added to the corresponding FP32 accumulate value. The sum is rounded according to the frm register. | norm:vfwmaccbf16_op |
| The vector-scalar version is similar, but instead of reading elements from vs1, a scalar BF16 value is read from the FPU register rs1. | norm:vfwmaccbf16_vf | |
| All of the BF16 instructions in the extensions defined in this specification (i.e., Zfbfmin, Zvfbfmin, and Zvfbfwma) fully support subnormal numbers. That is, instructions are able to accept subnormal values as inputs and they can produce subnormal results. | norm:bf16_subnorm | |
| vfwmaccbf16_vv_sew_rsv | SEW is any value other than 16 | norm:vfwmaccbf16_sew_rsv |
| vfwmaccbf16_vf_sew_rsv | SEW is any value other than 16 | norm:vfwmaccbf16_sew_rsv |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| bitmanip_rv32_rv64 | The bitmanip extensions are defined for RV32 and RV64. | norm:bitmanip_rv32_rv64 |
| bitmanip_w_suffix_semantics | The bitmanip extension follows the convention in RV64 that w-suffixed instructions (without a dot before the w) ignore the upper 32 bits of their inputs, operate on the least-significant 32 bits as signed values, and produce a 32-bit signed result that is sign-extended to XLEN. | norm:bitmanip_w_suffix_semantics |
| bitmanip_uw_suffix_semantics | Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32-bit value that is extracted from the least-significant 32 bits of the specified register. Other than that, these perform full-XLEN operations. | norm:bitmanip_uw_suffix_semantics |
| bitmanip_bhw_suffix_semantics | Bitmanip instructions with the suffixes .b, .h, and .w only look at the least-significant 8 bits, 16 bits, and 32 bits of the input (respectively) and produce an XLEN-wide result that is sign-extended or zero-extended, based on the specific instruction. | norm:bitmanip_bhw_suffix_semantics |
| b_extension_composition | The B standard extension comprises instructions provided by the Zba, Zbb, and Zbs extensions. |
norm:b_extension_composition |
| zba_slli_uw_function | While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw -- added in this extension -- can be used when the index is to be interpreted as an unsigned word. | norm:zba_slli_uw_function |
| zbb_sign_zero_extension_function | These instructions perform the sign extension or zero extension of the least-significant 8 bits or 16 bits of the source register. | norm:zbb_sign_zero_extension_function |
| zbb_rotate_semantics | where the shift-logical instructions shift in zeros, the rotate instructions shift in the bits that were shifted out of the other side of the value. |
norm:zbb_rotate_semantics |
| zbb_orc_b_semantics | orc.b sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set. | norm:zbb_orc_b_semantics |
| zbc_clmul_clmulh_results | clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2{times}XLEN carry-less product. | norm:zbc_clmul_clmulh_results |
| zbc_clmulr_results | clmulr produces bits 2{times}XLEN−2:XLEN-1 of the 2{times}XLEN carry-less product. | norm:zbc_clmulr_results |
| zbs_single_bit_functionality | The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. |
norm:zbs_single_bit_functionality |
| zbkx_lookup_table_model | These instructions implement a "lookup table" for 4 and 8 bit elements inside the general purpose registers. |
norm:zbkx_lookup_table_model |
| zbkx_indexing_behavior | Elements in rs1 are replaced by the indexed element in rs2, or zero if the index into rs2 is out of bounds. |
norm:zbkx_indexing_behavior |
| Zb_shamt_rsv_rv32 | For RV32, the encodings corresponding to shamt[5]=1 are reserved. | norm:bclri_shamt_rsv_rv32 |
| For RV32, the encodings corresponding to shamt[5]=1 are reserved. | norm:bexti_shamt_rsv_rv32 | |
| For RV32, the encodings corresponding to shamt[5]=1 are reserved. | norm:binvi_shamt_rsv_rv32 | |
| For RV32, the encodings corresponding to shamt[5]=1 are reserved. | norm:bseti_shamt_rsv_rv32 | |
| add_uw_enc | Encoding | norm:add_uw_enc |
| add_uw_op | Operation | norm:add_uw_op |
| andn_enc | Encoding | norm:andn_enc |
| andn_op | Operation | norm:andn_op |
| bclr_enc | Encoding | norm:bclr_enc |
| bclr_op | Operation | norm:bclr_op |
| bclri_enc | Encoding (RV32) | norm:bclri_rv32_enc |
| Encoding (RV64) | norm:bclri_rv64_enc | |
| bclri_op | Operation | norm:bclri_op |
| bext_enc | Encoding | norm:bext_enc |
| bext_op | Operation | norm:bext_op |
| bexti_enc | Encoding (RV32) | norm:bexti_rv32_enc |
| Encoding (RV64) | norm:bexti_rv64_enc | |
| bexti_op | Operation | norm:bexti_op |
| binv_enc | Encoding | norm:binv_enc |
| binv_op | Operation | norm:binv_op |
| binvi_enc | Encoding (RV32) | norm:binvi_rv32_enc |
| Encoding (RV64) | norm:binvi_rv64_enc | |
| binvi_op | Operation | norm:binvi_op |
| bset_enc | Encoding | norm:bset_enc |
| bset_op | Operation | norm:bset_op |
| bseti_enc | Encoding (RV32) | norm:bseti_rv32_enc |
| Encoding (RV64) | norm:bseti_rv64_enc | |
| bseti_op | Operation | norm:bseti_op |
| clmul_enc | Encoding | norm:clmul_enc |
| clmul_op | Operation | norm:clmul_op |
| clmulh_enc | Encoding | norm:clmulh_enc |
| clmulh_op | Operation | norm:clmulh_op |
| clmulr_enc | Encoding | norm:clmulr_enc |
| clmulr_op | Operation | norm:clmulr_op |
| clz_enc | Encoding | norm:clz_enc |
| clz_op | Operation | norm:clz_op |
| clzw_enc | Encoding | norm:clzw_enc |
| clzw_op | Operation | norm:clzw_op |
| cpop_enc | Encoding | norm:cpop_enc |
| cpop_op | Operation | norm:cpop_op |
| cpopw_enc | Encoding | norm:cpopw_enc |
| cpopw_op | Operation | norm:cpopw_op |
| ctz_enc | Encoding | norm:ctz_enc |
| ctz_op | Operation | norm:ctz_op |
| ctzw_enc | Encoding | norm:ctzw_enc |
| ctzw_op | Operation | norm:ctzw_op |
| max_enc | Encoding | norm:max_enc |
| max_op | Operation | norm:max_op |
| maxu_enc | Encoding | norm:maxu_enc |
| maxu_op | Operation | norm:maxu_op |
| min_enc | Encoding | norm:min_enc |
| min_op | Operation | norm:min_op |
| minu_enc | Encoding | norm:minu_enc |
| minu_op | Operation | norm:minu_op |
| orc_b_enc | Encoding | norm:orc_b_enc |
| orc_b_op | Operation | norm:orc_b_op |
| orn_enc | Encoding | norm:orn_enc |
| orn_op | Operation | norm:orn_op |
| pack_enc | Encoding | norm:pack_enc |
| pack_op | Operation | norm:pack_op |
| packh_enc | Encoding | norm:packh_enc |
| packh_op | Operation | norm:packh_op |
| packw_enc | Encoding | norm:packw_enc |
| packw_op | Operation | norm:packw_op |
| rev8_enc | Encoding (RV32) | norm:rev8_rv32_enc |
| Encoding (RV64) | norm:rev8_rv64_enc | |
| rev8_op | Operation | norm:rev8_op |
| brev8_enc | Encoding | norm:brev8_enc |
| brev8_op | Operation | norm:brev8_op |
| rol_enc | Encoding | norm:rol_enc |
| rol_op | Operation | norm:rol_op |
| rolw_enc | Encoding | norm:rolw_enc |
| rolw_op | Operation | norm:rolw_op |
| ror_enc | Encoding | norm:ror_enc |
| ror_op | Operation | norm:ror_op |
| rori_enc | Encoding (RV32) | norm:rori_rv32_enc |
| Encoding (RV64) | norm:rori_rv64_enc | |
| rori_op | Operation | norm:rori_op |
| roriw_enc | Encoding | norm:roriw_enc |
| roriw_op | Operation | norm:roriw_op |
| rorw_enc | Encoding | norm:rorw_enc |
| rorw_op | Operation | norm:rorw_op |
| sext_b_enc | Encoding | norm:sext_b_enc |
| sext_b_op | Operation | norm:sext_b_op |
| sext_h_enc | Encoding | norm:sext_h_enc |
| sext_h_op | Operation | norm:sext_h_op |
| sh1add_enc | Encoding | norm:sh1add_enc |
| sh1add_op | Operation | norm:sh1add_op |
| sh1add_uw_enc | Encoding | norm:sh1add_uw_enc |
| sh1add_uw_op | Operation | norm:sh1add_uw_op |
| sh2add_enc | Encoding | norm:sh2add_enc |
| sh2add_op | Operation | norm:sh2add_op |
| sh2add_uw_enc | Encoding | norm:sh2add_uw_enc |
| sh2add_uw_op | Operation | norm:sh2add_uw_op |
| sh3add_enc | Encoding | norm:sh3add_enc |
| sh3add_op | Operation | norm:sh3add_op |
| sh3add_uw_enc | Encoding | norm:sh3add_uw_enc |
| sh3add_uw_op | Operation | norm:sh3add_uw_op |
| slli_uw_enc | Encoding | norm:slli_uw_enc |
| slli_uw_op | Operation | norm:slli_uw_op |
| unzip_enc | Encoding | norm:unzip_enc |
| unzip_op | Operation | norm:unzip_op |
| xnor_enc | Encoding | norm:xnor_enc |
| xnor_op | Operation | norm:xnor_op |
| xperm8_enc | Encoding | norm:xperm8_enc |
| xperm8_op | Operation | norm:xperm8_op |
| xperm4_enc | Encoding | norm:xperm4_enc |
| xperm4_op | Operation | norm:xperm4_op |
| zext_h_enc | Encoding (RV32) | norm:zext_h_rv32_enc |
| Encoding (RV64) | norm:zext_h_rv64_enc | |
| zext_h_op | Operation | norm:zext_h_op |
| zip_enc | Encoding | norm:zip_enc |
| zip_op | Operation | norm:zip_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zabha_rd_sign_extension | Byte and halfword AMOs always sign-extend the value placed in rd, and ignore the image:../../build/images-out/stem-2aa35a881e52a6683f571d117edc7f47.svg[width=136,height=12] bits of the original value in rs2. |
norm:Zabha_rd_sign_extension |
| Zabha_amocas-BH_ignore_bits | The AMOCAS.[B|H] instructions similarly ignore the image:../../build/images-out/stem-2aa35a881e52a6683f571d117edc7f47.svg[width=136,height=12] bits of the original value in rd. |
norm:Zabha_amocas-BH_ignore_bits |
| Zabha_rs1_align_addr | Similar to the AMOs specified in the A extension, the Zabha extension mandates that the address contained in the rs1 register must be naturally aligned to the size of the operand. |
norm:Zabha_rs1_align_addr |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zca_offsets_mul2 | compressed instruction offsets are multiples of 2 | Rule's "summary" property |
| As with base RVI instructions, the offsets of all RVC control transfer instructions are in multiples of 2 bytes. |
norm:Zca_offsets_mul2 | |
| Zca_align16 | The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary, i.e., IALIGN=16. |
norm:Zca_align16 |
| Zca_no_misaligned | With the addition of the C extension, no instructions can raise instruction-address-misaligned exceptions. |
norm:Zca_no_misaligned |
| Zca_regs8 | CIW, CL, CS, CA, and CB are limited to just 8 of them. registers lists these popular registers, which correspond to registers x8 to x15. |
norm:Zca_regs8 |
| Zc_fp_regs | Compressed register-based floating-point loads and stores also use the CL and CS formats respectively, with the eight registers mapping to f8 to f15. |
norm:Zc_fp_regs |
| c-lwsp_op | C.LWSP loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to lw rd, offset(x2). |
norm:c-lwsp_op |
| c-lwsp_rsv | C.LWSP is valid only when rd≠x0; the code points with rd=x0 are reserved. |
norm:c-lwsp_rsv |
| c-ldsp_op | C.LDSP is an RV64C-only instruction that loads a 64-bit value from memory into register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld rd, offset(x2). |
norm:c-ldsp_op |
| c-ldsp_rsv | C.LDSP is valid only when rd≠x0; the code points with rd=x0 are reserved. |
norm:c-ldsp_rsv |
| c-flwsp_op | C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to flw rd, offset(x2). |
norm:c-flwsp_op |
| c-fldsp_op | C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fld rd, offset(x2). |
norm:c-fldsp_op |
| c-swsp_op | C.SWSP stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to sw rs2, offset(x2). |
norm:c-swsp_op |
| c-sdsp_op | C.SDSP is an RV64C-only instruction that stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd rs2, offset(x2). |
norm:c-sdsp_op |
| c-fswsp_op | C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to fsw rs2, offset(x2). |
norm:c-fswsp_op |
| c-fsdwsp_op | C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fsd rs2, offset(x2). |
norm:c-fsdwsp_op |
| c-lw_op | C.LW loads a 32-bit value from memory into register rd′. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to lw rd′, offset(rs1′). |
norm:c-lw_op |
| c-ld_op | C.LD is an RV64C-only instruction that loads a 64-bit value from memory into register rd′. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to ld rd′, offset(rs1′). |
norm:c-ld_op |
| c-flw_op | C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd′. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to flw rd′, offset(rs1′). |
norm:c-flw_op |
| c-fld_op | C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd′. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to fld rd′, offset(rs1′). |
norm:c-fld_op |
| c-sw_op | C.SW stores a 32-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to sw rs2′, offset(rs1′). |
norm:c-sw_op |
| c-sd_op | C.SD is an RV64C-only instruction that stores a 64-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to sd rs2′, offset(rs1′). |
norm:c-sd_op |
| c-fsw_op | C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to fsw rs2′, offset(rs1′). |
norm:c-fsw_op |
| c-fsd_op | C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to fsd rs2′, offset(rs1′). |
norm:c-fsd_op |
| c-j_op | C.J performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. C.J can therefore target a {pm}2 KiB range. C.J expands to jal x0, offset. |
norm:c-j_op |
| c-jal_op | C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JAL expands to jal x1, offset. |
norm:c-jal_op |
| c-jr_op | C.JR (jump register) performs an unconditional control transfer to the address in register rs1. C.JR expands to jalr x0, 0(rs1). |
norm:c-jr_op |
| c-jr_rsv | C.JR is valid only when rs1≠x0; the code point with rs1=x0 is reserved. |
norm:c-jr_rsv |
| c-jalr_op | C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JALR expands to jalr x1, 0(rs1). |
norm:c-jalr_op |
| c-ebreak | C.JALR is valid only when rs1≠x0; the code point with rs1=x0 corresponds to the C.EBREAK instruction. |
norm:c-jalr_ebreak |
| c-beqz_op | C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a {pm}256 B range. C.BEQZ takes the branch if the value in register rs1′ is zero. It expands to beq rs1′, x0, offset. |
norm:c-beqz_op |
| c-bnez_op | C.BNEZ is defined analogously, but it takes the branch if rs1′ contains a nonzero value. It expands to bne rs1′, x0, offset. |
norm:c-bnez_op |
| c-li_op | C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into addi rd, x0, imm. |
norm:c-li_op |
| c-li_hint | The C.LI code points with rd=x0 are HINTs. | norm:c-li_hint |
| c-lui_op | C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into lui rd, imm. |
norm:c-lui_op |
| c-lui_rsv | C.LUI is valid only when rd≠x2, and when the immediate is not equal to zero. The code points with imm=0 are reserved. The code points with rd=x2 and imm≠0 correspond to the C.ADDI16SP instruction. |
norm:c-lui_rsv |
| c-lui_hint | The code points with rd=x0 and imm≠0 are HINTs. | norm:c-lui_hint |
| c-addi_op | C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into addi rd, rd, imm. |
norm:c-addi_op |
| c-addi_hint | The code points with rd≠0 and imm=0 are HINTs. | norm:c-addi_hint |
| c-addi_nop | The code points with rd=x0 encode the C.NOP instruction, of which the code points with imm≠0 are HINTs. |
norm:c-addi_nop |
| c-addiw_op | C.ADDIW is an RV64C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into addiw rd, rd, imm. The immediate can be zero for C.ADDIW, where this corresponds to sext.w rd. |
norm:c-addiw_op |
| c-addiw_rsv | C.ADDIW is valid only when rd≠x0; the code points with rd=x0 are reserved. |
norm:c-addiw_rsv |
| c-addi16sp_op | C.ADDI16SP (add immediate to stack pointer) shares the opcode with C.LUI, but has a destination field of x2. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. It expands into addi x2, x2, nzimm[9:4]. |
norm:c-addi16sp_op |
| c-addi16sp_rsv | C.ADDI16SP is valid only when nzimm≠0; the code point with nzimm=0 is reserved. |
norm:c-addi16sp_rsv |
| c-addi4spn_op | C.ADDI4SPN (add immediate to stack pointer, non-destructive) is a CIW-format instruction that adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd′. This instruction is used to generate pointers to stack-allocated variables, and expands to addi rd′, x2, nzuimm[9:2]. |
norm:c-addi4spn_op |
| c-addi4spn_rsv | C.ADDI4SPN is valid only when nzuimm≠0; the code points with nzuimm=0 are reserved. |
norm:c-addi4spn_rsv |
| c-slli_op | C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd. The shift amount is encoded in the shamt field. C.SLLI expands into slli rd, rd, shamt[5:0]. |
norm:c-slli_op |
| c-slli_hint | The C.SLLI code points with shamt=0 or with rd=x0 are HINTs. | norm:c-slli_hint |
| c-slli_shamt5 | For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions. |
norm:c-slli_shamt5 |
| c-srli_op | C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd′ then writes the result to rd′. The shift amount is encoded in the shamt field. C.SRLI expands into srli rd′, rd′, shamt. |
norm:c-srli_op |
| c-srli_hint | The C.SRLI code points with shamt=0 are HINTs. | norm:c-srli_hint |
| c-srli_shamt5 | For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions. |
norm:c-srli_shamt5 |
| c-srai_op | C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to srai rd′, rd′, shamt. |
norm:c-srai_op |
| c-srai_hint | C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to srai rd′, rd′, shamt. |
norm:c-srai_op |
| The C.SRLI code points with shamt=0 are HINTs. | norm:c-srli_hint | |
| c-andi_op | C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register rd′ and the sign-extended 6-bit immediate, then writes the result to rd′. C.ANDI expands to andi rd′, rd′, imm. |
norm:c-andi_op |
| c-mv_op | C.MV copies the value in register rs2 into register rd. C.MV expands into add rd, x0, rs2. |
norm:c-mv_op |
| c-mv_jr | C.MV is valid only when rs2≠x0; the code points with rs2=x0 correspond to the C.JR instruction. |
norm:c-mv_jr |
| c-mv_hint | The code points with rs2≠x0 and rd=x0 are HINTs. | norm:c-mv_hint |
| c-add_op | C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into add rd, rd, rs2. |
norm:c-add_op |
| c-add_val | C.ADD is only valid when rs2≠x0; the code points with rs2=x0 correspond to the C.JALR and C.EBREAK instructions. |
norm:c-add_val |
| c-add_hint | The code points with rs2≠x0 and rd=x0 are HINTs. | norm:c-add_hint |
| c-and_op | C.AND computes the bitwise AND of the values in registers rd′ and rs2′, then writes the result to register rd′. C.AND expands into and rd′, rd′, rs2′. |
norm:c-and_op |
| c-or_op | C.OR computes the bitwise OR of the values in registers rd′ and rs2′, then writes the result to register rd′. C.OR expands into or rd′, rd′, rs2′. |
norm:c-or_op |
| c-xor_op | C.XOR computes the bitwise XOR of the values in registers rd′ and rs2′, then writes the result to register rd′. C.XOR expands into xor rd′, rd′, rs2′. |
norm:c-xor_op |
| c-sub_op | C.SUB subtracts the value in register rs2′ from the value in register rd′, then writes the result to register rd′. C.SUB expands into sub rd′, rd′, rs2′. |
norm:c-sub_op |
| c-addw_op | C.ADDW is an RV64C-only instruction that adds the values in registers rd′ and rs2′, then sign-extends the lower 32 bits of the sum before writing the result to register rd′. C.ADDW expands into addw rd′, rd′, rs2′. |
norm:c-addw_op |
| c-subw_op | C.SUBW is an RV64C-only instruction that subtracts the value in register rs2′ from the value in register rd′, then sign-extends the lower 32 bits of the difference before writing the result to register rd′. C.SUBW expands into subw rd′, rd′, rs2′. |
norm:c-subw_op |
| Zca_illegal | A 16-bit instruction with all bits zero is permanently reserved as an illegal instruction. |
norm:Zca_illegal |
| c-nop_op | C.NOP is a CI-format instruction that does not change any user-visible state, except for advancing the pc and incrementing any applicable performance counters. C.NOP expands to nop. |
norm:c-nop_op |
| c-nop_hint | The C.NOP code points with imm≠0 encode HINTs. |
norm:c-nop_hint |
| c-ebreak_op | Debuggers can use the C.EBREAK instruction, which expands to ebreak, to cause control to be transferred back to the debugging environment. C.EBREAK shares the opcode with the C.ADD instruction, but with rd and rs2 both zero, thus can also use the CR format. |
norm:c-ebreak_op |
| Zca_hints | A portion of the RVC encoding space is reserved for microarchitectural HINTs. Like the HINTs in the RV32I base ISA (see rv32i-hints), these instructions do not modify any architectural state, except for advancing the pc and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them. |
norm:Zca_hints |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| CACHE_BLOCK_SIZE | extension | Rule's "kind" property |
| [Zicbom, Zicbop, Zicboz] | Rule's "instances" property | |
| Implementation-defined behavior | Rule's property | |
| The capacity and organization of a cache and the size of a cache block are both implementation-specific, and the execution environment provides software a means to discover information about the caches and cache blocks in a system. In the initial set of CMO extensions, the size of a cache block shall be uniform throughout the system. |
norm:cache_block_size | |
| PPO_overlap | PPO overlapping address rule for CMO instructions | Rule's "summary" property |
| if a precedes b in program order, then a will precede b in the global memory order if: |
norm:PPO_overlap_1 | |
| a is an invalidate, clean, or flush, b is a load, and a and b access overlapping memory addresses |
norm:PPO_overlap_2 | |
| cmo_invalidate_load_values | Load value rules for invalidate operations | Rule's "summary" property |
| If no clean or flush operations on x precede i in the global memory order, either the initial value of x or the value of any store to x that precedes i |
norm:invalidate_load_val1 | |
| If no store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the initial value of x or the value of any store to x that precedes i |
norm:invalidate_load_val2 | |
| If a store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the value of the latest store to x that precedes the latest clean or flush operation on x or the value of any store to x that both precedes i and succeeds the latest clean or flush operation on x that precedes i |
norm:invalidate_load_val3 | |
| The value of any store to x by a non-coherent agent regardless of the above conditions |
norm:invalidate_load_val4 | |
| cbo_physical_address_constraints | Physical address constraints for CBO instructions in cache blocks | Rule's "summary" property |
| The PMP access control bits shall be the same for all physical addresses in the cache block, and if write permission is granted by the PMP access control bits, read permission shall also be granted |
norm:PMP_same | |
| The PMAs shall be the same for all physical addresses in the cache block, and if write permission is granted by the supported access type PMAs, read permission shall also be granted |
norm:PMA_same | |
| If the above constraints are not met, the behavior of a CBO instruction is UNSPECIFIED. |
norm:cbo_rsv | |
| cbm_access | Cache-block management instruction access permission | Rule's "summary" property |
| A cache-block management instruction is permitted to access the specified cache block whenever a load instruction or store instruction is permitted to access the corresponding physical addresses. |
norm:cbm_access | |
| cbm_unperm_fault | Cache-block management instruction fault on unpermitted access | Rule's "summary" property |
| If access to the cache block is not permitted, a cache-block management instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit any access or raises a store access-fault exception otherwise. |
norm:cbm_unperm_fault | |
| cbm_unperm_translate | Cache-block management instruction address translation behavior | Rule's "summary" property |
| During address translation, the instruction also checks the accessed bit and may either raise an exception or set the bit as required. |
norm:cbm_unperm_translate | |
| cbz_access | Cache-block zero instruction access permission | Rule's "summary" property |
| A cache-block zero instruction is permitted to access the specified cache block whenever a store instruction is permitted to access the corresponding physical addresses and when the PMAs indicate that cache-block zero instructions are a supported access type. |
norm:cbz_access | |
| cbz_unperm_fault | Cache-block zero instruction fault on unpermitted access | Rule's "summary" property |
| If access to the cache block is not permitted, a cache-block zero instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit write access or raises a store access-fault exception otherwise. |
norm:cbz_unperm_fault | |
| cbz_unperm_translate | Cache-block zero instruction address translation behavior | Rule's "summary" property |
| During address translation, the instruction also checks the accessed and dirty bits and may either raise an exception or set the bits as required. |
norm:cbz_unperm_translate | |
| cbp_access | Cache-block prefetch instruction access permission | Rule's "summary" property |
| A cache-block prefetch instruction is permitted to access the specified cache block whenever a load instruction, store instruction, or instruction fetch is permitted to access the corresponding physical addresses. |
norm:cbp_access | |
| cbp_unperm_noexcep | Cache-block prefetch instruction no exception on unpermitted access | Rule's "summary" property |
| If access to the cache block is not permitted, a cache-block prefetch instruction does not raise any exceptions and shall not access any caches or memory. |
norm:cbp_unperm_noexcep | |
| cbp_unperm_translate | Cache-block prefetch instruction address translation behavior | Rule's "summary" property |
| During address translation, the instruction does not check the accessed and dirty bits and neither raises an exception nor sets the bits. |
norm:cbp_unperm_translate | |
| fault_excep_csr | CMO instruction fault exception CSR behavior | Rule's "summary" property |
| When a page-fault, guest-page-fault, or access-fault exception is taken, the relevant *tval CSR is written with the faulting effective address (i.e. the value of rs1). |
norm:fault_excep_csr | |
| no_addr_misaligned_excep | CMO instructions do not generate address-misaligned exceptions | Rule's "summary" property |
| CMO instructions do not generate address-misaligned exceptions. | norm:no_addr_misaligned_excep | |
| h_trans_cache | CMO instruction hypervisor transformation | Rule's "summary" property |
| For the purposes of writing the mtinst or htinst register on a trap, the following standard transformation is defined for cache-block management instructions and cache-block zero instructions: | norm:h_trans_cache | |
| cbo-inval | CBO.INVAL instruction execution control | Rule's "summary" property |
| A CBO.INVAL instruction executes or raises either an illegal-instruction exception or a virtual-instruction exception based on the state of the xenvcfg.CBIE fields: | norm:cbo-inval | |
| cbo-clean_cbo-flush | CBO.CLEAN and CBO.FLUSH instruction execution control | Rule's "summary" property |
| A CBO.CLEAN or CBO.FLUSH instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the xenvcfg.CBCFE bits: | norm:cbo-clean_cbo-flush | |
| cbo-zero_basedon_xenvcfg-CBZE | CBO.ZERO execution control based on xenvcfg.CBZE | Rule's "summary" property |
| Finally, a CBO.ZERO instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the xenvcfg.CBZE bits: | norm:cbo-zero_basedon_xenvcfg-CBZE | |
| cbxe_unaffected | CBIE/CBCFE/CBZE fields do not affect other registers | Rule's "summary" property |
| The CBIE/CBCFE/CBZE fields in each xenvcfg register do not affect the read and write behavior of the same fields in the other xenvcfg registers. | norm:cbxe_unaffected | |
| cbo-zero_specified_block | CBO.ZERO operates on specified cache block | Rule's "summary" property |
| These instructions operate on the cache block, or the memory locations corresponding to the cache block, whose effective address is specified in rs1. |
norm:cbo-zero_specified_block | |
| prefetch_operating_block | Prefetch instructions operate on specified cache block | Rule's "summary" property |
| These instructions operate on the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] shall equal 0b00000. |
norm:prefetch_operating_block | |
| cbo-clean_op | CBO.CLEAN instruction operation | Rule's "summary" property |
| A cbo.clean instruction performs a clean operation on the cache block whose effective address is the base address specified in rs1. |
norm:cbo-clean_op | |
| cbo-clean_offset | CBO.CLEAN offset operand behavior | Rule's "summary" property |
| The offset operand may be omitted; otherwise, any expression that computes the offset shall evaluate to zero. |
norm:cbo-clean_offset | |
| cbo-flush_op | CBO.FLUSH instruction operation | Rule's "summary" property |
| A cbo.flush instruction performs a flush operation on the cache block whose that contains the address specified in rs1. |
norm:cbo-flush_op | |
| cbo-flush_unaligned | CBO.FLUSH does not require cache block alignment | Rule's "summary" property |
| It is not required that rs1 is aligned to the size of a cache block. |
norm:cbo-flush_unaligned | |
| cbo-inval_op | CBO.INVAL instruction operation | Rule's "summary" property |
| A cbo.inval instruction performs an invalidate operation on the cache block that contains the address specified in rs1. |
norm:cbo-inval_op | |
| cbo-inval_unaligned | CBO.INVAL does not require cache block alignment | Rule's "summary" property |
| It is not required that rs1 is aligned to the size of a cache block. |
norm:cbo-inval_unaligned | |
| cbo-zero_op | CBO.ZERO instruction operation | Rule's "summary" property |
| A cbo.zero instruction performs stores of zeros to the full set of bytes corresponding to the cache block that contains the address specified in rs1. |
norm:cbo-zero_op | |
| cbo-zero_unaligned | CBO.ZERO does not require cache block alignment | Rule's "summary" property |
| It is not required that rs1 is aligned to the size of a cache block. | norm:cbo-zero_unaligned | |
| cbo-zero_offset | CBO.ZERO offset operand behavior | Rule's "summary" property |
| The assembly offset operand may be omitted. If it isn’t then any expression that computes the offset shall evaluate to zero. | norm:cbo-zero_offset | |
| prefetch-i_op | PREFETCH.I instruction operation | Rule's "summary" property |
| A prefetch.i instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by an instruction fetch in the near future. | norm:prefetch-i_op | |
| prefetch-r_op | PREFETCH.R instruction operation | Rule's "summary" property |
| A prefetch.r instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data read (i.e. load) in the near future. | norm:prefetch-r_op | |
| prefetch-w_op | PREFETCH.W instruction operation | Rule's "summary" property |
| A prefetch.w instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data write (i.e. store) in the near future. | norm:prefetch-w_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zicfilp_forward_traps | A trap may need to be delivered to the same or to a higher privilege mode upon completion of JALR/C.JALR/C.JR, but before the instruction at the target of indirect call/jump was decoded |
norm:Zicfilp_forward_traps |
| Asynchronous interrupts. | norm:Zicfilp_forward_trap_async_interrupt | |
| Synchronous exceptions with priority higher than that of a software-check exception with xtval set to "landing pad fault (code=2)" (See norm:exc_priority of Privileged Specification). |
norm:Zicfilp_forward_trap_async_exception | |
| Zicfilp_exception_priority | The software-check exception caused by Zicfilp has higher priority than an illegal-instruction exception but lower priority than instruction access-fault. | norm:Zicfilp_exception_priority |
| lpad_sw_exception | The software-check exception due to the instruction not being an LPAD instruction when ELP is LP_EXPECTED or a software-check exception caused by the LPAD instruction itself leads to a trap being delivered to the same or to a higher privilege mode. | norm:lpad_sw_exception |
| Zicfilp_forward_traps_s_hs_mode | To store the previous ELP state on trap delivery to S/HS-mode, an SPELP bit is provided in the mstatus CSR. |
norm:cfi_mstatus_spelp_op |
| The SPELP bit in mstatus can be accessed through the sstatus CSR. |
norm:cfi_sstatus_spelp_op | |
| vsstatus_spelp_op2 | To store the previous ELP state on traps to VS-mode, a SPELP bit is defined in the vsstatus (VS-modes version of sstatus). |
norm:vsstatus_spelp_op2 |
| Zicfilp_forward_traps_debug_mode | To store the previous ELP state on transition to Debug Mode, a pelp bit is defined in the dcsr register. |
norm:dcsr_pelp_op |
| Upon entry into Debug Mode, the pelp bit in dcsr is updated with the ELP at the privilege level the hart was previously in, and the ELP is set to NO_LP_EXPECTED. When a hart resumes from Debug Mode, if the new privilege mode is y, then ELP is set to the value of pelp if yLPE (see ) is 1; otherwise, it is set to NO_LP_EXPECTED. | norm:Zicfilp_pelp_debug_mode | |
| Zicfilp_pelp_trap | When a trap is taken into privilege mode x, the xPELP is set to ELP and ELP is set to NO_LP_EXPECTED. | norm:Zicfilp_pelp_trap |
| Zicfilp_pelp_trap_return | An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if the new privilege mode is y, then ELP is set to the value of xPELP if yLPE (see ) is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED. | norm:Zicfilp_pelp_trap_return |
| Zicfilp_ssp_below_m_mode | If the privilege mode is less than M and menvcfg.SSE is 0, an illegal-instruction exception is raised. |
norm:zicfiss_m_menvcfg_sse |
| Attempts to access the ssp CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the x`envcfg.SSE` fields. The conditions are specified as follows: | norm:zicfiss_ssp_csr | |
| Zicfiss_ssp_u_mode | Otherwise, if in U-mode and senvcfg.SSE is 0, an illegal-instruction exception is raised. |
norm:zicfiss_u_senvcfg_sse |
| Attempts to access the ssp CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the x`envcfg.SSE` fields. The conditions are specified as follows: | norm:zicfiss_ssp_csr | |
| Zicfiss_ssp_vs_mode | Otherwise, if in VS-mode and henvcfg.SSE is 0, a virtual-instruction exception is raised. |
norm:zicfiss_vs_henvcfg_sse |
| Attempts to access the ssp CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the x`envcfg.SSE` fields. The conditions are specified as follows: | norm:zicfiss_ssp_csr | |
| Zicfiss_ssp_vu_mode | Otherwise, if in VU-mode and either henvcfg.SSE or senvcfg.SSE is 0, a virtual-instruction exception is raised. |
norm:zicfiss_vu_henvcfg_senvcfg_sse |
| Attempts to access the ssp CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the x`envcfg.SSE` fields. The conditions are specified as follows: | norm:zicfiss_ssp_csr | |
| Zicfiss_ssp_hs_modes | Otherwise, the access is allowed. | norm:zicfiss_sse_access |
| Attempts to access the ssp CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the x`envcfg.SSE` fields. The conditions are specified as follows: | norm:zicfiss_ssp_csr | |
| Zicfiss_smode_xsse | When S-mode is not implemented, then xSSE is 0 at both M and U privilege modes. | norm:zicfiss_smode_xsse |
| ss_page_enc | The encoding R=0, W=1, and X=0, is defined to represent an SS page. |
norm:ss_page_enc |
| ssmp_menvcfg_sse | When menvcfg.SSE=0, this encoding remains reserved. |
norm:ssmp_menvcfg_sse |
| ssmp_henvcfg_sse | Similarly, when V=1 and henvcfg.SSE=0, this encoding remains reserved at VS and VU levels. |
norm:ssmp_henvcfg_sse |
| satp_mode_bare | If satp.MODE (or vsatp.MODE when V=1) is set to Bare and the effective privilege mode is less than M, shadow stack instructions raise a store/AMO access-fault exception. |
norm:satp_mode_bare |
| ssmp_ssamoswap | When the effective privilege mode is M, memory access by an SSAMOSWAP.W/D instruction results in a store/AMO access-fault exception. |
norm:ssmp_ssamoswap |
| ss_page_exceptions | Memory mapped as an SS page cannot be written to by instructions other than SSAMOSWAP.W/D, SSPUSH, and C.SSPUSH. Attempts will raise a store/AMO access-fault exception. |
norm:ssmp_ss_page_access_fault |
| Access to a SS page using cache-block operation (CBO.*) instructions is not permitted. Such accesses will raise a store/AMO access-fault exception. |
norm:ssmp_ss_cache_block_access_fault | |
| Implicit accesses, including instruction fetches to an SS page, are not permitted. Such accesses will raise an access-fault exception appropriate to the access type. |
norm:ssmp_ss_implicit_access_fault | |
| However, the shadow stack is readable by all instructions that only load from memory. |
norm:ssmp_ss_load | |
| If a shadow stack (SS) instruction raises an access-fault, page-fault, or guest-page-fault exception that is supposed to indicate the original instruction type (load or store/AMO), then the reported exception cause is respectively a store/AMO access fault (code 7), a store/AMO page fault (code 15), or a store/AMO guest-page fault (code 23). |
norm:ss_fault_exception_code | |
| Should a shadow stack instruction access a page that is not designated as a shadow stack page and is not marked as read-only (pte.xwr=001), a store/AMO access-fault exception will be invoked. |
norm:ssmp_ss_page_illegeal_access | |
| Conversely, if the page being accessed by a shadow stack instruction is a read-only page, a store/AMO page-fault exception will be triggered. |
norm:ssmp_ss_read_only_page | |
| ssp_xlen_aligned | If the virtual address in ssp is not XLEN aligned, then the SSPUSH/ C.SSPUSH/SSPOPCHK/C.SSPOPCHK instructions cause a store/AMO access-fault exception. | norm:ssp_xlen_aligned |
| ssmp_ss_idempotent_memory | If the memory referenced by SSPUSH/C.SSPUSH/SSPOPCHK/C.SSPOPCHK/SSAMOSWAP.W/D instructions is not idempotent, then the instructions cause a store/AMO access-fault exception. |
norm:ssmp_ss_idempotent_memory |
| active_g_stage_pte | When G-stage page tables are active, the shadow stack instructions that access memory require the G-stage page table to have read-write permission for the accessed memory; else a store/AMO guest-page-fault exception is raised. |
norm:active_g_stage_pte |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| smcdeleg_ssccfg_tandem | For a RISC-V hardware platform, Smcdeleg and Ssccfg must always be implemented in tandem. | norm:smcdeleg_ssccfg_tandem |
| smcdeleg_cde_en | When the Smcdeleg/Ssccfg extensions are enabled (menvcfg.CDE=1), it further allows M-mode to delegate select counters to S-mode. | norm:smcdeleg_cde_en |
| ssccfg_illegal_sireg_cde0 | attempts to access any sireg* when menvcfg.CDE = 0; | norm:ssccfg_illegal_sireg_cde0 |
| ssccfg_illegal_sireg3_6 | attempts to access sireg3 or sireg6; | norm:ssccfg_illegal_sireg3_6 |
| ssccfg_illegal_sireg4_5_xlen64 | attempts to access sireg4 or sireg5 when XLEN = 64; | norm:ssccfg_illegal_sireg4_5_xlen64 |
| ssccfg_illegal_sireg_not_delegated | attempts to access sireg* when siselect = 0x41, or when the counter selected by siselect is not delegated to S-mode (the corresponding bit in mcounteren = 0). |
norm:ssccfg_illegal_sireg_not_delegated |
| ssccfg_missing_extension_illegal | If any extension upon which the underlying state depends is not implemented, an attempt from M or S mode to access the given state through sireg* raises an illegal-instruction exception. | norm:ssccfg_missing_extension_illegal |
| ssccfg_hyp_vs_or_vu_access_vsireg_illegal | If the hypervisor (H) extension is also implemented, then as specified by extensions Smcsrind/Sscsrind, a virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access vsiselect or vsireg*, or attempts from VU-mode to access siselect or sireg*. Furthermore, while vsiselect holds a value in the range 0x40-0x5F: | norm:ssccfg_hyp_vs_or_vu_access_vsireg_illegal |
| ssccfg_hyp_m_s_vsireg_illegal | An attempt to access any vsireg* from M or S mode raises an illegal-instruction exception. | norm:ssccfg_hyp_m_s_vsireg_illegal |
| ssccfg_hyp_vs_access_sireg_conditional | An attempt from VS-mode to access any sireg* (really vsireg*) raises an illegal-instruction exception if menvcfg.CDE = 0, or a virtual-instruction exception if menvcfg.CDE = 1. | norm:ssccfg_hyp_vs_access_sireg_conditional |
| ssccfg_scountinhibit_exists | Smcdeleg/Ssccfg defines a new scountinhibit register, a masked alias of mcountinhibit. | norm:ssccfg_scountinhibit_exists |
| ssccfg_scountinhibit_delegated_rw | For counters delegated to S-mode, the associated mcountinhibit bits can be accessed via scountinhibit | norm:ssccfg_scountinhibit_delegated_rw |
| ssccfg_scountinhibit_nondelegated_ro | For counters not delegated to S-mode, the associated bits in scountinhibit are read-only zero. | norm:ssccfg_scountinhibit_nondelegated_ro |
| ssccfg_illegal_scountinhibit_cde0 | When menvcfg.CDE=0, attempts to access scountinhibit raise an illegal-instruction exception. | norm:ssccfg_illegal_scountinhibit_cde0 |
| ssccfg_illegal_scountinhibit_vs_vu | When Supervisor Counter Delegation is enabled, attempts to access scountinhibit from VS-mode or VU-mode raise a virtual-instruction exception. |
norm:ssccfg_illegal_scountinhibit_vs_vu |
| ssccfg_virtual_scountovf_vs_vu | For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H extension, when menvcfg.CDE=1, attempts to read scountovf from VS-mode or VU-mode raise a virtual-instruction exception. | norm:ssccfg_virtual_scountovf_vs_vu |
| ssccfg_lcofi_mvip_mvien | For implementations that support Smcdeleg, Sscofpmf, and Smaia, the local-counter-overflow interrupt (LCOFI) bit (bit 13) in each of CSRs mvip and mvien is implemented and writable. | norm:ssccfg_lcofi_mvip_mvien |
| ssccfg_lcofi_hvip_hvien | For implementations that support Smcdeleg/Ssccfg, Sscofpmf, Smaia/Ssaia, and the H extension, the LCOFI bit (bit 13) in each of hvip and hvien is implemented and writable. | norm:ssccfg_lcofi_hvip_hvien |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| zihpm_op_sz_mode_acc_count | RISC-V ISAs provide a set of up to thirty-two 64-bit performance counters and timers |
norm:zihpm_op_sz_mode_acc_count |
| zihpm_op_sz_mode_acc_xlen32 | when XLEN=32, the upper 32 bits are accessed via CSR registers 0xC80–0xC9F |
norm:zihpm_op_sz_mode_acc_xlen32 |
| zihpm_op_sz_mode_acc_partition | These counters are divided between the "Zicntr" and "Zihpm" extensions. |
norm:zihpm_op_sz_mode_acc_partition |
| zihpm_op_sz_mode_acc_priv | accessible via unprivileged XLEN-bit read-only CSR registers 0xC00–0xC1F |
norm:zihpm_op_sz_mode_acc_priv |
| zicntr_rdcycle_op | The RDCYCLE pseudoinstruction reads the low XLEN bits of the cycle CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an arbitrary start time in the past. |
norm:zicntr_rdcycle_op |
| zicntr_rdcycleh_op | RDCYCLEH is only present when XLEN=32 and reads bits 63-32 of the same cycle counter. |
norm:zicntr_rdcycleh_op |
| zicntr_rdtime_op | The RDTIME pseudoinstruction reads the low XLEN bits of the "time" CSR, which counts wall-clock real time that has passed from an arbitrary start time in the past. |
norm:zicntr_rdtime_op |
| zicntr_rdtimeh_op | RDTIMEH is only present when XLEN=32 and reads bits 63-32 of the same real-time counter. |
norm:zicntr_rdtimeh_op |
| zicntr_time_hart_sync | The real-time clocks of all harts must be synchronized to within one tick of the real-time clock. |
norm:zicntr_time_hart_sync |
| zicntr_rdinstret_op | The RDINSTRET pseudoinstruction reads the low XLEN bits of the instret CSR, which counts the number of instructions retired by this hart from some arbitrary start point in the past. |
norm:zicntr_rdinstret_op |
| zicntr_rdinstreth_op | RDINSTRETH is only present when XLEN=32 and reads bits 63-32 of the same instruction counter. |
norm:zicntr_rdinstreth_op |
| hpm_counter_op_sz_mode_dependency | The Zihpm extension depends on the Zicsr extension. |
norm:hpm_counter_op_sz_mode_dependency |
| hpm_counter_op_sz_mode_xlen32 | When XLEN=32, the upper 32 bits of these performance counters are accessible via additional CSRs hpmcounter3h- hpmcounter31h. |
norm:hpm_counter_op_sz_mode_xlen32 |
| hpmcounter_op_sz_mode | The Zihpm extension comprises up to 29 additional unprivileged 64-bit hardware performance counters, hpmcounter3-hpmcounter31. |
norm:hpmcounter_op_sz_mode |
| HPM_PLATFORM_SPECIFIC_IMPL | extension | Rule's "kind" property |
| Zihpm | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The implemented number and width of these additional counters, and the set of events they count, are platform-specific. |
norm:hpm_platform_specific_impl | |
| HPM_UNIMPLEMENTED_COUNTER_ACCESS | extension | Rule's "kind" property |
| Zihpm | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Accessing an unimplemented counter may cause an illegal-instruction exception or may return a constant value. |
norm:hpm_unimplemented_counter_access | |
| hpm_misconfigured_event_behavior | If the configuration used to select the events counted by a counter is misconfigured, the counter may return a constant value. |
norm:hpm_misconfigured_event_behavior |
| Rule Name | Rule Description | Origin of Description | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| D_fpr_regs | The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide |
norm:flen | ||||||||||||||||||||||||||
| The D extension widens the 32 floating-point registers, f0-f31, to 64 bits (FLEN=64 in fprs |
norm:D_flen_64 | |||||||||||||||||||||||||||
| fld_op | The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd |
norm:fld_op | ||||||||||||||||||||||||||
| fsd_op | FSD stores a double-precision value from the floating-point registers to memory |
norm:fsd_op | ||||||||||||||||||||||||||
| fsd_atomic_align | FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64. | norm:fld_fsd_atomic_align | ||||||||||||||||||||||||||
| fld_atomic_align | FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64. | norm:fld_fsd_atomic_align | ||||||||||||||||||||||||||
| fsd_bits_maintained | FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fld_fsd_bits_maintained | ||||||||||||||||||||||||||
| fld_bits_maintained | FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fld_fsd_bits_maintained | ||||||||||||||||||||||||||
| fadd-d_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmul-d_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsub-d_op | FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 |
norm:fsub-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fdiv-d_op | FDIV.S performs the single-precision floating-point division of rs1 by rs2 | norm:fdiv-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsqrt-d_op | FSQRT.S computes the square root of rs1 | norm:fsqrt-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmadd-d_op | FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. | norm:fmadd-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmsub-d_op | FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. | norm:fmsub-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmsub-d_op | FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. | norm:fnmsub-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmadd-d_op | FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. | norm:fnmadd-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. | norm:D_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-w-d_op | FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd |
norm:fcvt-w-d_fcvt-l-d_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-l-d_op | FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd |
norm:fcvt-w-d_fcvt-l-d_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. | norm:fcvt_long_double_rv64_only | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-d-w_op | FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd |
norm:fcvt-d-w_fcvt-d-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-d-l_op | FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd |
norm:fcvt-d-w_fcvt-d-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. | norm:fcvt_long_double_rv64_only | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-wu-d_op | FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-d_fcvt-lu-d_fcvt-d-wu_fcvt-d-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-lu-d_op | FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-d_fcvt-lu-d_fcvt-d-wu_fcvt-d-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. | norm:fcvt_long_double_rv64_only | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-d-wu_op | FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-d_fcvt-lu-d_fcvt-d-wu_fcvt-d-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-d-lu_op | FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-d_fcvt-lu-d_fcvt-d-wu_fcvt-d-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. | norm:fcvt_long_double_rv64_only | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-s-d_op | The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers. The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination |
norm:fcvt-s-d_fcvt-d-s_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-d-s_op | The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers. The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination |
norm:fcvt-s-d_fcvt-d-s_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fsgnj-d_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-d_fsgnjn-d_fsgnjx-d_op | |||||||||||||||||||||||||||
| fsgnjn-d_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-d_fsgnjn-d_fsgnjx-d_op | |||||||||||||||||||||||||||
| fsgnjx-d_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-d_fsgnjn-d_fsgnjx-d_op | |||||||||||||||||||||||||||
| fmv-x-d_op | FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd |
norm:fmv-x-d_op | ||||||||||||||||||||||||||
| fmv-d-x_op | FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd |
norm:fmv-d-x_op | ||||||||||||||||||||||||||
| fmv-x-d_op_bits_preserved | FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fmv_bits_preserved | ||||||||||||||||||||||||||
| fmv-d-x_op_bits_preserved | FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fmv_bits_preserved | ||||||||||||||||||||||||||
| feq-d_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands. | norm:D_compare_instrs | |||||||||||||||||||||||||||
| flt-d_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands. | norm:D_compare_instrs | |||||||||||||||||||||||||||
| fle-d_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands. | norm:D_compare_instrs | |||||||||||||||||||||||||||
| feq-d_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN |
norm:feq-s_quiet | |||||||||||||||||||||||||||
| The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands. | norm:D_compare_instrs | |||||||||||||||||||||||||||
| flt-d_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands. | norm:D_compare_instrs | |||||||||||||||||||||||||||
| fle-d_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands. | norm:D_compare_instrs | |||||||||||||||||||||||||||
| fclass-d_op | The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags. | norm:fclass-s_op | ||||||||||||||||||||||||||
| The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands. | norm:fclass-d_op | |||||||||||||||||||||||||||
| fp_nan-boxing | When multiple floating-point precisions are supported, then valid values of narrower n-bit types, n<FLEN, are represented in the lower n bits of an FLEN-bit NaN value, in a process termed NaN-boxing. The upper bits of a valid NaN-boxed value must be all 1s. Valid NaN-boxed n-bit values therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value, n < m ≤ FLEN. Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-n bits to yield a legal NaN-boxedvalue. | norm:fp_nan-boxing | ||||||||||||||||||||||||||
| FP_transfer_instrs_narrow_transfer_in | A narrower n-bit transfer, n<FLEN, into the f registers will create a valid NaN-boxed value | norm:FP_transfer_instrs_narrow_transfer_in | ||||||||||||||||||||||||||
| FP_transfer_instrs_narrow_transfer_out | A narrower n-bit transfer out of the floating-point registers will transfer the lower n bits of the register ignoring the upper FLEN-n bits |
norm:FP_transfer_instrs_narrow_transfer_out | ||||||||||||||||||||||||||
| fcvt-w-d_fcvt-wu-d_sign_ext | For RV64, FCVT.W[U].D sign-extends the 32-bit result |
norm:fcvt-w-d_fcvt-wu-d_sign_ext |
| Rule Name | Rule Description | Origin of Description | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| FLEN | extension | Rule's "kind" property | ||||||||||||||||||||||||||
| F | Rule's "instance" property | |||||||||||||||||||||||||||
| The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide |
norm:flen | |||||||||||||||||||||||||||
| f_ieee_compliance | single-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard [.citation] |
norm:f_ieee_compliance | ||||||||||||||||||||||||||
| f_depends_zicsr | extension_dependency | Rule's "kind" property | ||||||||||||||||||||||||||
| The F extension depends on the "Zicsr" extension for control and status register access. | norm:f_depends_zicsr | |||||||||||||||||||||||||||
| fscr_sz | The floating-point control and status register, fcsr, is a RISC-V control and status register (CSR). It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in . | norm:fcsr_op_sz_acc | ||||||||||||||||||||||||||
| fcsr_acc | The floating-point control and status register, fcsr, is a RISC-V control and status register (CSR). It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in . | norm:fcsr_op_sz_acc | ||||||||||||||||||||||||||
| fcsr_op | The floating-point control and status register, fcsr, is a RISC-V control and status register (CSR). It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in . | norm:fcsr_op_sz_acc | ||||||||||||||||||||||||||
| Bits 31—8 of the fcsr are reserved for other standard extensions. If these extensions are not present, implementations shall ignore writes to these bits and supply a zero value when read. Standard software should preserve the contents of these bits. | norm:fcsr_rsv | |||||||||||||||||||||||||||
| fcsr_frm_sz | The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm (fcsr bits 7—5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags (fcsr bits 4—0). | norm:fflags_frm_op_sz_acc | ||||||||||||||||||||||||||
| fcsr_frm_acc | The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm (fcsr bits 7—5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags (fcsr bits 4—0). | norm:fflags_frm_op_sz_acc | ||||||||||||||||||||||||||
| fcsr_frm_op | The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm (fcsr bits 7—5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags (fcsr bits 4—0). | norm:fflags_frm_op_sz_acc | ||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcsr_fflags_op | The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm (fcsr bits 7—5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags (fcsr bits 4—0). | norm:fflags_frm_op_sz_acc | ||||||||||||||||||||||||||
| The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software, as shown in bitdef |
norm:fcsr_fflags_op | |||||||||||||||||||||||||||
| roundingmode_rsv | The behavior of floating-point instructions that depend on rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the rm field but are nevertheless mathematically unaffected by the rounding mode; software should set their rm field to RNE (000) but implementations must treat the rm field as usual (in particular, with regard to decoding legal vs. reserved encodings). |
norm:roundingmode_rsv | ||||||||||||||||||||||||||
| fp_misaligned | As described in , the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap. | norm:fp_misaligned | ||||||||||||||||||||||||||
| F_rm_field | All floating-point operations that perform rounding can select the rounding mode using the rm field with the encoding shown in . | norm:F_rm_field | ||||||||||||||||||||||||||
| fsw_op | Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory. | norm:fsw_flw_op | ||||||||||||||||||||||||||
| flw_op | Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory. | norm:fsw_flw_op | ||||||||||||||||||||||||||
| fsw_atomic_align | FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned. | norm:fsw_flw_atomic_align | ||||||||||||||||||||||||||
| flw_atomic_align | FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned. | norm:fsw_flw_atomic_align | ||||||||||||||||||||||||||
| fsw_bits_maintained | FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fsw_flw_bits_maintained | ||||||||||||||||||||||||||
| flw_bits_maintained | FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fsw_flw_bits_maintained | ||||||||||||||||||||||||||
| fmax-s_op | Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd | norm:fmin-s_fmax-s_op | ||||||||||||||||||||||||||
| fmin-s_op | Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd | norm:fmin-s_fmax-s_op | ||||||||||||||||||||||||||
| fmin-s_zero_compare | For the purposes of these instructions only, the value −0.0 is considered to be less than the value +0.0 | norm:fmin-s_fmax-s_zero_compare | ||||||||||||||||||||||||||
| fmax-s_zero_compare | For the purposes of these instructions only, the value −0.0 is considered to be less than the value +0.0 | norm:fmin-s_fmax-s_zero_compare | ||||||||||||||||||||||||||
| fmin-s_both_nan_input | If both inputs are NaNs, the result is the canonical NaN | norm:fmin-s_fmax-s_both_nan_input | ||||||||||||||||||||||||||
| Except when otherwise stated, if the result of a floating-point operation is NaN, it is the canonical NaN. The canonical NaN has a positive sign and all significand bits clear except the MSB, a.k.a. the quiet bit. For single-precision floating-point, this corresponds to the pattern 0x7fc00000. | norm:F_canonical_NaN | |||||||||||||||||||||||||||
| fmax-s_both_nan_input | If both inputs are NaNs, the result is the canonical NaN | norm:fmin-s_fmax-s_both_nan_input | ||||||||||||||||||||||||||
| Except when otherwise stated, if the result of a floating-point operation is NaN, it is the canonical NaN. The canonical NaN has a positive sign and all significand bits clear except the MSB, a.k.a. the quiet bit. For single-precision floating-point, this corresponds to the pattern 0x7fc00000. | norm:F_canonical_NaN | |||||||||||||||||||||||||||
| fmin-s_one_nan_input | If only one operand is a NaN, the result is the non-NaN operand | norm:fmin-s_fmax-s_one_nan_input | ||||||||||||||||||||||||||
| fmax-s_one_nan_input | If only one operand is a NaN, the result is the non-NaN operand | norm:fmin-s_fmax-s_one_nan_input | ||||||||||||||||||||||||||
| fmax-s_signaling_nan_nv | Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN | norm:fmin-s_fmax-s_signaling_nan_nv | ||||||||||||||||||||||||||
| fmin-s_signaling_nan_nv | Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN | norm:fmin-s_fmax-s_signaling_nan_nv | ||||||||||||||||||||||||||
| fadd-s_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| In each case, the result is written to rd. | norm:fp_rd | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmul-s_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| In each case, the result is written to rd. | norm:fp_rd | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsub-s_op | FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 |
norm:fsub-s_op | ||||||||||||||||||||||||||
| In each case, the result is written to rd. | norm:fp_rd | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fdiv-s_op | FDIV.S performs the single-precision floating-point division of rs1 by rs2 | norm:fdiv-s_op | ||||||||||||||||||||||||||
| In each case, the result is written to rd. | norm:fp_rd | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsqrt-s_op | FSQRT.S computes the square root of rs1 | norm:fsqrt-s_op | ||||||||||||||||||||||||||
| In each case, the result is written to rd. | norm:fp_rd | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmadd-s_op | FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. | norm:fmadd-s_op | ||||||||||||||||||||||||||
| Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. | norm:fma_rs3 | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmsub-s_op | FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. | norm:fmsub-s_op | ||||||||||||||||||||||||||
| Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. | norm:fma_rs3 | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmsub-s_op | FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. | norm:fnmsub-s_op | ||||||||||||||||||||||||||
| Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. | norm:fma_rs3 | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmadd-s_op | FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. | norm:fnmadd-s_op | ||||||||||||||||||||||||||
| Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. | norm:fma_rs3 | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-w-s_op | FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd |
norm:fcvt-l-s_fcvt-w-s_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-l-s_op | FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd |
norm:fcvt-l-s_fcvt-w-s_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions | norm:fcvt_long_float_rv64_only | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-s-w_op | FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd |
norm:fcvt-s-w_fcvt-s-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-s-l_op | FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd |
norm:fcvt-s-w_fcvt-s-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions | norm:fcvt_long_float_rv64_only | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-wu-s_op | FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width |
norm:fcvt-wu-s_fcvt-lu-s_fcvt-s-wu_fcvt-s-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-lu-s_op | FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width |
norm:fcvt-wu-s_fcvt-lu-s_fcvt-s-wu_fcvt-s-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions | norm:fcvt_long_float_rv64_only | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-s-wu_op | FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width |
norm:fcvt-wu-s_fcvt-lu-s_fcvt-s-wu_fcvt-s-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-s-lu_op | FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width |
norm:fcvt-wu-s_fcvt-lu-s_fcvt-s-wu_fcvt-s-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions | norm:fcvt_long_float_rv64_only | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsgnj-s_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| fsgnjn-s_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| fsgnjx-s_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. | norm:F_fmt_single | |||||||||||||||||||||||||||
| fmv-x-w_op | FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign bit | norm:fmv-x-w_op | ||||||||||||||||||||||||||
| fmv-w-x_op | FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. | norm:fmv-w-x_op | ||||||||||||||||||||||||||
| feq-s_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| flt-s_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| fle-s_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| feq-s_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN |
norm:feq-s_quiet | |||||||||||||||||||||||||||
| flt-s_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| fle-s_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| fclass-s_op | The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags. | norm:fclass-s_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| H_mtval_nrz | CSR mtval must not be read-only zero | norm:H_mtval_nrz |
| H_vm_supported | standard page-based address translation must be supported, either Sv32 for RV32, or a minimum of Sv39 for RV64 |
norm:H_vm_supported |
| misa_h_op | The hypervisor extension is enabled by setting bit 7 in the misa CSR | norm:misa_h_op |
| H_csrs_hs_not_vs | Additional CSRs are provided to HS-mode, but not to VS-mode, to manage two-stage address translation and to control the behavior of a VS-mode guest: hstatus, hedeleg, hideleg, hvip, hip, hie, hgeip, hgeie, henvcfg, henvcfgh, hcounteren, htimedelta, htimedeltah, htval, htinst, and hgatp. |
norm:H_csrs_hs_not_vs |
| H_vscsrs_sub | When V=1, the VS CSRs substitute for the corresponding supervisor CSRs, taking over all functions of the usual supervisor CSRs except as specified otherwise. Instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR. |
norm:H_vscsrs_sub |
| H_vscsrs_acc_vs | When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception. |
norm:H_vscsrs_acc_vs |
| H_vscsrs_acc_u | Attempts from U-mode cause an illegal-instruction exception as usual. |
norm:H_vscsrs_acc_u |
| H_vscsrs_acc_m_hs | The VS CSRs can be accessed as themselves only from M-mode or HS-mode. |
norm:H_vscsrs_acc_m_hs |
| H_vscsrs_v1 | While V=1, the normal HS-level supervisor CSRs that are replaced by VS CSRs retain their values but do not affect the behavior of the machine unless specifically documented to do so. |
norm:H_vscsrs_v1 |
| H_vscsrs_v0 | when V=0, the VS CSRs do not ordinarily affect the behavior of the machine other than being readable and writable by CSR instructions. |
norm:H_vscsrs_v0 |
| H_scsrs_nomatch | Some standard supervisor CSRs (senvcfg, scounteren, and scontext, possibly others) have no matching VS CSR. These supervisor CSRs continue to have their usual function and accessibility even when V=1, except with VS-mode and VU-mode substituting for HS-mode and U-mode. Hypervisor software is expected to manually swap the contents of these registers as needed. | norm:H_scsrs_nomatch |
| HSXLEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| we use the term HSXLEN to refer to the effective XLEN when executing in HS-mode |
norm:hsxlen | |
| VSXLEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| VSXLEN to refer to the effective XLEN when executing in VS-mode. |
norm:vsxlen | |
| hstatus_sz | The hstatus register is an HSXLEN-bit read/write register formatted as shown in when HSXLEN=32 and when HSXLEN=64. The hstatus register provides facilities analogous to the mstatus register for tracking and controlling the exception behavior of a VS-mode guest. | norm:hstatus_sz_acc_op |
| hstatus_acc | The hstatus register is an HSXLEN-bit read/write register formatted as shown in when HSXLEN=32 and when HSXLEN=64. The hstatus register provides facilities analogous to the mstatus register for tracking and controlling the exception behavior of a VS-mode guest. | norm:hstatus_sz_acc_op |
| hstatus_op | The hstatus register is an HSXLEN-bit read/write register formatted as shown in when HSXLEN=32 and when HSXLEN=64. The hstatus register provides facilities analogous to the mstatus register for tracking and controlling the exception behavior of a VS-mode guest. | norm:hstatus_sz_acc_op |
| hstatus_vsxl_op | The VSXL field controls the effective XLEN for VS-mode (known as VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN). |
norm:hstatus_vsxl_op |
| hstatus_vsxl_32 | When HSXLEN=32, the VSXL field does not exist, and VSXLEN=32. |
norm:hstatus_vsxl_32 |
| hstatus_vsxl_64 | When HSXLEN=64, VSXL is a WARL field that is encoded the same as the MXL field of misa, shown in norm:misa_mxl_enc. |
norm:hstatus_vsxl_64 |
| HSTATUS_VSXL_64_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| When HSXLEN=64, VSXL is a WARL field that is encoded the same as the MXL field of misa, shown in norm:misa_mxl_enc. |
norm:hstatus_vsxl_64 | |
| VSXL_RO | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN. |
norm:vsxl_ro | |
| hstatus_vsxl_change | If HSXLEN is changed from 32 to a wider width, and if field VSXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new HSXLEN. | norm:hstatus_vsxl_change |
| hstatus_vtsr_op | When VTSR=1, an attempt in VS-mode to execute SRET raises a virtual-instruction exception. |
norm:hstatus_vtsr_op |
| hstatus_vtw_op | When VTW=1 (and assuming mstatus.TW=0), an attempt in VS-mode to execute WFI raises a virtual-instruction exception if the WFI does not complete within an implementation-specific, bounded time limit. |
norm:hstatus_vtw_op |
| VTW_VIRTINSTR | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| An implementation may have WFI always raise a virtual-instruction exception in VS-mode when VTW=1 (and mstatus.TW=0), even if there are pending globally-disabled interrupts when the instruction is executed. |
norm:vtw_virtinstr | |
| hstatus_vtvm_op | When VTVM=1, an attempt in VS-mode to execute SFENCE.VMA or SINVAL.VMA or to access CSR satp raises a virtual-instruction exception. |
norm:hstatus_vtvm_op |
| hstatus_vgein_op | The VGEIN (Virtual Guest External Interrupt Number) field selects a guest external interrupt source for VS-level external interrupts. VGEIN is a WLRL field that must be able to hold values between zero and the maximum guest external interrupt number (known as GEILEN), inclusive. When VGEIN=0, no guest external interrupt source is selected for VS-level external interrupts. GEILEN may be zero, in which case VGEIN may be read-only zero. Guest external interrupts are explained in , and the use of VGEIN is covered further in . | norm:hstatus_vgein_op |
| HSTATUS_VGEIN_WLRL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WLRL | Implementation-defined behavior category | |
| The VGEIN (Virtual Guest External Interrupt Number) field selects a guest external interrupt source for VS-level external interrupts. VGEIN is a WLRL field that must be able to hold values between zero and the maximum guest external interrupt number (known as GEILEN), inclusive. When VGEIN=0, no guest external interrupt source is selected for VS-level external interrupts. GEILEN may be zero, in which case VGEIN may be read-only zero. Guest external interrupts are explained in , and the use of VGEIN is covered further in . | norm:hstatus_vgein_op | |
| hstatus_hu_op | Field HU (Hypervisor in U-mode) controls whether the virtual-machine load/store instructions, HLV, HLVX, and HSV, can be used also in U-mode. When HU=1, these instructions can be executed in U-mode the same as in HS-mode. When HU=0, all hypervisor instructions cause an illegal-instruction exception in U-mode. | norm:hstatus_hu_op |
| hstatus_spv_op | The SPV bit (Supervisor Previous Virtualization mode) is written by the implementation whenever a trap is taken into HS-mode. Just as the SPP bit in sstatus is set to the (nominal) privilege mode at the time of the trap, the SPV bit in hstatus is set to the value of the virtualization mode V at the time of the trap. |
norm:hstatus_spv_op |
| hstatus_spv_sret | When an SRET instruction is executed when V=0, V is set to SPV. |
norm:hstatus_spv_sret |
| hstatus_spvp_op | When V=1 and a trap is taken into HS-mode, bit SPVP (Supervisor Previous Virtual Privilege) is set to the nominal privilege mode at the time of the trap, the same as sstatus.SPP. But if V=0 before a trap, SPVP is left unchanged on trap entry. SPVP controls the effective privilege of explicit memory accesses made by the virtual-machine load/store instructions, HLV, HLVX, and HSV. | norm:hstatus_spvp_op |
| hstatus_gva_op | Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into HS-mode. For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to stval, GVA is set to 1. For any other trap into HS-mode, GVA is set to 0. | norm:hstatus_gva_op |
| hstatus_vsbe_op | The VSBE bit is a WARL field that controls the endianness of explicit memory accesses made from VS-mode. If VSBE=0, explicit load and store memory accesses made from VS-mode are little-endian, and if VSBE=1, they are big-endian. VSBE also controls the endianness of all implicit accesses to VS-level memory management data structures, such as page tables. An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode. | norm:hstatus_vsbe_op |
| HSTATUS_VSBE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| The VSBE bit is a WARL field that controls the endianness of explicit memory accesses made from VS-mode. If VSBE=0, explicit load and store memory accesses made from VS-mode are little-endian, and if VSBE=1, they are big-endian. VSBE also controls the endianness of all implicit accesses to VS-level memory management data structures, such as page tables. An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode. | norm:hstatus_vsbe_op | |
| hedeleg_sz | Register hedeleg is a 64-bit read/write register, formatted as shown in norm:hedeleg_img. |
norm:hedeleg_sz_acc |
| hedeleg_acc | Register hedeleg is a 64-bit read/write register, formatted as shown in norm:hedeleg_img. |
norm:hedeleg_sz_acc |
| Each bit of hedeleg shall be either writable or read-only zero. Many bits of hedeleg are required specifically to be writable or zero, as enumerated in hedeleg-bits. Bit 0, corresponding to instruction address-misaligned exceptions, must be writable if IALIGN=32. |
norm:hedeleg_acc | |
| HEDELEG_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hedeleg_img | |
| hideleg_sz | Register hideleg is an HSXLEN-bit read/write register, formatted as shown in norm:hideleg_img. |
norm:hideleg_sz_acc |
| HIDELEG_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hideleg_img | |
| hedeleg_op | A synchronous trap that has been delegated to HS-mode (using medeleg) is further delegated to VS-mode if V=1 before the trap and the corresponding hedeleg bit is set. |
norm:hedeleg_op |
| hedelegh_sz | When XLEN=32, hedelegh is a 32-bit read/write register that aliases bits 63:32 of hedeleg. Register hedelegh does not exist when XLEN=64. | norm:hedelegh_sz_acc_op |
| hedelegh_acc | When XLEN=32, hedelegh is a 32-bit read/write register that aliases bits 63:32 of hedeleg. Register hedelegh does not exist when XLEN=64. | norm:hedelegh_sz_acc_op |
| hedelegh_op | When XLEN=32, hedelegh is a 32-bit read/write register that aliases bits 63:32 of hedeleg. Register hedelegh does not exist when XLEN=64. | norm:hedelegh_sz_acc_op |
| hideleg_op | An interrupt that has been delegated to HS-mode (using mideleg) is further delegated to VS-mode if the corresponding hideleg bit is set. |
norm:hideleg_op |
| hideleg_acc | Register hideleg is an HSXLEN-bit read/write register, formatted as shown in norm:hideleg_img. |
norm:hideleg_sz_acc |
| Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros. |
norm:hideleg_acc | |
| hideleg_trans | When a virtual supervisor external interrupt (code 10) is delegated to VS-mode, it is automatically translated by the machine into a supervisor external interrupt (code 9) for VS-mode, including the value written to vscause on an interrupt trap. Likewise, a virtual supervisor timer interrupt (6) is translated into a supervisor timer interrupt (5) for VS-mode, and a virtual supervisor software interrupt (2) is translated into a supervisor software interrupt (1) for VS-mode. Similar translations may or may not be done for platform interrupt causes (codes 16 and above). | norm:hideleg_trans |
| hvip_sz | Register hvip is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode. Bits of hvip that are not writable are read-only zeros. | norm:hvip_sz_op |
| hvip_op | Register hvip is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode. Bits of hvip that are not writable are read-only zeros. | norm:hvip_sz_op |
| HVIP_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hvip_img | |
| hvip_acc | The standard portion (bits 15:0) of hvip is formatted as shown in . Bits VSEIP, VSTIP, and VSSIP of hvip are writable. Setting VSEIP=1 in hvip asserts a VS-level external interrupt; setting VSTIP asserts a VS-level timer interrupt; and setting VSSIP asserts a VS-level software interrupt. | norm:hvip_acc |
| hip_hie_sz | Registers hip and hie are HSXLEN-bit read/write registers that supplement HS-level’s sip and sie respectively. |
norm:hip_hie_sz_acc |
| hip_hie_acc | Registers hip and hie are HSXLEN-bit read/write registers that supplement HS-level’s sip and sie respectively. |
norm:hip_hie_sz_acc |
| hip_op | The hip register indicates pending VS-level and hypervisor-specific interrupts |
norm:hip_op |
| hie_op | hie contains enable bits for the same interrupts | norm:hie_op |
| HIP_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hip_img | |
| HIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hie_img | |
| sie_hip_hie_mutex | For each writable bit in sie, the corresponding bit shall be read-only zero in both hip and hie. Hence, the nonzero bits in sie and hie are always mutually exclusive, and likewise for sip and hip. | norm:sie_hip_hie_mutex |
| hideleg_hs | An interrupt i will trap to HS-mode whenever all of the following are true: (a) either the current operating mode is HS-mode and the SIE bit in the sstatus register is set, or the current operating mode has less privilege than HS-mode; (b) bit i is set in both sip and sie, or in both hip and hie; and (c) bit i is not set in hideleg. | norm:hideleg_hs |
| hip_acc | If bit i of sie is read-only zero, the same bit in register hip may be writable or may be read-only. When bit i in hip is writable, a pending interrupt i can be cleared by writing 0 to this bit. If interrupt i can become pending in hip but bit i in hip is read-only, then either the interrupt can be cleared by clearing bit i of hvip, or the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment). | norm:hip_acc |
| hie_acc | A bit in hie shall be writable if the corresponding interrupt can ever become pending in hip. Bits of hie that are not writable shall be read-only zero. | norm:hie_acc |
| hip_sgeip_sgeie_acc | Bits hip.SGEIP and hie.SGEIE are the interrupt-pending and interrupt-enable bits for guest external interrupts at supervisor level (HS-level). SGEIP is read-only in hip, and is 1 if and only if the bitwise logical-AND of CSRs hgeip and hgeie is nonzero in any bit. (See .) | norm:hip_sgeip_sgeie_acc_op |
| hip_sgeip_sgeie_op | Bits hip.SGEIP and hie.SGEIE are the interrupt-pending and interrupt-enable bits for guest external interrupts at supervisor level (HS-level). SGEIP is read-only in hip, and is 1 if and only if the bitwise logical-AND of CSRs hgeip and hgeie is nonzero in any bit. (See .) | norm:hip_sgeip_sgeie_acc_op |
| hip_vseip_vseie_op | Bits hip.VSEIP and hie.VSEIE are the interrupt-pending and interrupt-enable bits for VS-level external interrupts. VSEIP is read-only in hip, and is the logical-OR of these interrupt sources: | norm:hip_vseip_vseie_op |
| hip_vstip_vstie_acc | Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and, when the Sstc extension is implemented, the timer interrupt signal resulting from vstimecmp. The hip.VSTIP bit, in response to timer interrupts generated by vstimecmp, is set by writing vstimecmp with a value that is less than or equal to the sum of time and htimedelta, truncated to 64 bits; it is cleared by writing vstimecmp with a greater value. The hip.VSTIP bit remains defined while V=0 as well as V=1. | norm:hip_vstip_vstie_acc_op |
| hip_vstip_vstie_op | Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and, when the Sstc extension is implemented, the timer interrupt signal resulting from vstimecmp. The hip.VSTIP bit, in response to timer interrupts generated by vstimecmp, is set by writing vstimecmp with a value that is less than or equal to the sum of time and htimedelta, truncated to 64 bits; it is cleared by writing vstimecmp with a greater value. The hip.VSTIP bit remains defined while V=0 as well as V=1. | norm:hip_vstip_vstie_acc_op |
| hip_vssip_vssie_op | Bits hip.VSSIP and hie.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in hip is an alias (writable) of the same bit in hvip. | norm:hip_vssip_vssie_op |
| hsint_priority | Multiple simultaneous interrupts destined for HS-mode are handled in the following decreasing priority order: SEI, SSI, STI, SGEI, VSEI, VSSI, VSTI, LCOFI. | norm:hsint_priority |
| hgeip_sz | The hgeip register is an HSXLEN-bit read-only register, formatted as shown in hgeipreg, that indicates pending guest external interrupts for this hart. |
norm:hgeip_sz_acc_op |
| hgeip_acc | The hgeip register is an HSXLEN-bit read-only register, formatted as shown in hgeipreg, that indicates pending guest external interrupts for this hart. |
norm:hgeip_sz_acc_op |
| hgeip_op | The hgeip register is an HSXLEN-bit read-only register, formatted as shown in hgeipreg, that indicates pending guest external interrupts for this hart. |
norm:hgeip_sz_acc_op |
| hgeie_sz | The hgeie register is an HSXLEN-bit read/write register, formatted as shown in norm:hgeie_img, that contains enable bits for the guest external interrupts at this hart. |
norm:hgeie_sz_acc_op |
| hgeie_acc | The hgeie register is an HSXLEN-bit read/write register, formatted as shown in norm:hgeie_img, that contains enable bits for the guest external interrupts at this hart. |
norm:hgeie_sz_acc_op |
| HGEIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hgeie_img | |
| hgeip_hgeie_fields | Guest external interrupt number i corresponds with bit i in both hgeip and hgeie. |
norm:hgeip_hgeie_fields |
| GEILEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie. | norm:geilen | |
| hgeie_op | The hgeie register is an HSXLEN-bit read/write register, formatted as shown in norm:hgeie_img, that contains enable bits for the guest external interrupts at this hart. |
norm:hgeie_sz_acc_op |
| Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN. | norm:hgeie_op | |
| henvcfg_sz | The henvcfg CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment when virtualization mode V=1. | norm:henvcfg_sz_acc_op |
| henvcfg_acc | The henvcfg CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment when virtualization mode V=1. | norm:henvcfg_sz_acc_op |
| henvcfg_op | The henvcfg CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment when virtualization mode V=1. | norm:henvcfg_sz_acc_op |
| henvcfg_fiom_op | If bit FIOM (Fence of I/O implies Memory) is set to one in henvcfg, FENCE instructions executed when V=1 are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1. | norm:henvcfg_fiom_op |
| henvcfg_fiom_order | Similarly, when FIOM=1 and V=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory. | norm:henvcfg_fiom_order |
| henvcfg_pbmte_op | The PBMTE bit controls whether the Svpbmt extension is available for use in VS-stage address translation. When PBMTE=1, Svpbmt is available for VS-stage address translation. When PBMTE=0, the implementation behaves as though Svpbmt were not implemented for VS-stage address translation. If Svpbmt is not implemented, PBMTE is read-only zero. | norm:henvcfg_pbmte_op |
| henvcfg_adue_op | If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation. When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation. When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation. If Svadu is not implemented, ADUE is read-only zero. | norm:henvcfg_adue_op |
| henvcfg_pmm_op | If the Ssnpm extension is implemented, the PMM field enables or disables pointer masking (see ) for VS-mode, according to the values in . When the Ssnpm extension is not implemented, the PMM field is read-only zero. The PMM field is read-only zero for RV32. | norm:henvcfg_pmm_op |
| henvcfg_lpe_op | The Zicfilp extension adds the LPE field in henvcfg. When the LPE field is set to 1, the Zicfilp extension is enabled in VS-mode. When the LPE field is 0, the Zicfilp extension is not enabled in VS-mode and the following rules apply to VS-mode: | norm:henvcfg_lpe_op |
| henvcfg_sse_op | The Zicfiss extension adds the SSE field in henvcfg. If the SSE field is set to 1, the Zicfiss extension is activated in VS-mode. When the SSE field is 0, the Zicfiss extension remains inactive in VS-mode, and the following rules apply when V=1: | norm:henvcfg_sse_op |
| henvcfg_dte_op | The Ssdbltrp extension adds the double-trap-enable (DTE) field in henvcfg. When henvcfg.DTE is zero, the implementation behaves as though Ssdbltrp is not implemented for VS-mode and the vsstatus.SDT bit is read-only zero. | norm:henvcfg_dte_op |
| henvcfgh_sz | When XLEN=32, henvcfgh is a 32-bit read/write register that aliases bits 63:32 of henvcfg. Register henvcfgh does not exist when XLEN=64. | norm:henvcfgh_sz_acc_op |
| henvcfgh_acc | When XLEN=32, henvcfgh is a 32-bit read/write register that aliases bits 63:32 of henvcfg. Register henvcfgh does not exist when XLEN=64. | norm:henvcfgh_sz_acc_op |
| henvcfgh_op | When XLEN=32, henvcfgh is a 32-bit read/write register that aliases bits 63:32 of henvcfg. Register henvcfgh does not exist when XLEN=64. | norm:henvcfgh_sz_acc_op |
| hcounteren_sz | The counter-enable register hcounteren is a 32-bit register that controls the availability of the hardware performance monitoring counters to the guest virtual machine. | norm:hcounteren_sz |
| hcounteren_op | When the CY, TM, IR, or HPMn bit in the hcounteren register is clear, attempts to read the cycle, time, instret, or hpmcounter n register while V=1 will cause a virtual-instruction exception if the same bit in mcounteren is 1. When one of these bits is set, access to the corresponding register is permitted when V=1, unless prevented for some other reason. In VU-mode, a counter is not readable unless the applicable bits are set in both hcounteren and scounteren. | norm:hcounteren_op |
| hcounteren_acc | In addition, when the TM bit in the hcounteren register is clear, attempts to access the vstimecmp register (via stimecmp) while executing in VS-mode will cause a virtual-instruction exception if the same bit in mcounteren is set. When this bit and the same bit in mcounteren are both set, access to the vstimecmp register (if implemented) is permitted in VS-mode. | norm:hcounteren_acc |
| HCOUNTEREN_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| hcounteren must be implemented. However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when V=1. Hence, they are effectively WARL fields. | norm:hcounteren_warl | |
| htimedelta_sz | The htimedelta CSR is a 64-bit read/write register that contains the delta between the value of the time CSR and the value returned in VS-mode or VU-mode. That is, reading the time CSR in VS or VU mode returns the sum of the contents of htimedelta and the actual value of time. |
norm:htimedelta_sz_acc_op |
| htimedelta_acc | The htimedelta CSR is a 64-bit read/write register that contains the delta between the value of the time CSR and the value returned in VS-mode or VU-mode. That is, reading the time CSR in VS or VU mode returns the sum of the contents of htimedelta and the actual value of time. |
norm:htimedelta_sz_acc_op |
| htimedelta_op | The htimedelta CSR is a 64-bit read/write register that contains the delta between the value of the time CSR and the value returned in VS-mode or VU-mode. That is, reading the time CSR in VS or VU mode returns the sum of the contents of htimedelta and the actual value of time. |
norm:htimedelta_sz_acc_op |
| htimedeltah_sz | When XLEN=32, htimedeltah is a 32-bit read/write register that aliases bits 63:32 of htimedelta. Register htimedeltah does not exist when XLEN=64. | norm:htimedeltah_sz_acc_op |
| htimedeltah_acc | When XLEN=32, htimedeltah is a 32-bit read/write register that aliases bits 63:32 of htimedelta. Register htimedeltah does not exist when XLEN=64. | norm:htimedeltah_sz_acc_op |
| htimedeltah_op | When XLEN=32, htimedeltah is a 32-bit read/write register that aliases bits 63:32 of htimedelta. Register htimedeltah does not exist when XLEN=64. | norm:htimedeltah_sz_acc_op |
| time_htimedelta_req | If the time CSR is implemented, htimedelta (and htimedeltah for XLEN=32) must be implemented. | norm:time_htimedelta_req |
| htval_sz | The htval register is an HSXLEN-bit read/write register formatted as shown in . When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap. | norm:htval_sz_acc_op |
| htval_acc | The htval register is an HSXLEN-bit read/write register formatted as shown in . When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap. | norm:htval_sz_acc_op |
| htval_op | The htval register is an HSXLEN-bit read/write register formatted as shown in . When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap. | norm:htval_sz_acc_op |
| HTVAL_TRAPVAL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| When a guest-page-fault trap is taken into HS-mode, htval is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, htval is set to zero, but a future standard or extension may redefine htval’s setting for other traps. | norm:htval_trapval | |
| htval_val | htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:htval_val |
| HTVAL_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:htval_val | |
| htinst_sz | The htinst register is an HSXLEN-bit read/write register formatted as shown in . When a trap is taken into HS-mode, htinst is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap. The values that may be written to htinst on a trap are documented in . | norm:htinst_sz_acc_op |
| htinst_acc | The htinst register is an HSXLEN-bit read/write register formatted as shown in . When a trap is taken into HS-mode, htinst is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap. The values that may be written to htinst on a trap are documented in . | norm:htinst_sz_acc_op |
| htinst_op | The htinst register is an HSXLEN-bit read/write register formatted as shown in . When a trap is taken into HS-mode, htinst is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap. The values that may be written to htinst on a trap are documented in . | norm:htinst_sz_acc_op |
| htinst_val | htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:htinst_val |
| HTINST_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:htinst_val | |
| hgatp_tvm_illegal | When mstatus.TVM=1, attempts to read or write hgatp while executing in HS-mode will raise an illegal-instruction exception. |
norm:hgatp_tvm_illegal |
| hgatp_sz | The hgatp register is an HSXLEN-bit read/write register, formatted as shown in rv32hgatp for HSXLEN=32 and rv64hgatp for HSXLEN=64, which controls G-stage address translation and protection, the second stage of two-stage translation for guest virtual addresses (see two-stage-translation). |
norm:hgatp_sz_acc_op |
| hgatp_acc | The hgatp register is an HSXLEN-bit read/write register, formatted as shown in rv32hgatp for HSXLEN=32 and rv64hgatp for HSXLEN=64, which controls G-stage address translation and protection, the second stage of two-stage translation for guest virtual addresses (see two-stage-translation). |
norm:hgatp_sz_acc_op |
| hgatp_op | The hgatp register is an HSXLEN-bit read/write register, formatted as shown in rv32hgatp for HSXLEN=32 and rv64hgatp for HSXLEN=64, which controls G-stage address translation and protection, the second stage of two-stage translation for guest virtual addresses (see two-stage-translation). |
norm:hgatp_sz_acc_op |
| hgatp_mode_bare | hgatp-mode shows the encodings of the MODE field when HSXLEN=32 and HSXLEN=64. When MODE=Bare, guest physical addresses are equal to supervisor physical addresses, and there is no further memory protection for a guest virtual machine beyond the physical memory protection scheme described in pmp. In this case, software must write zero to the remaining fields in hgatp. |
norm:hgatp_mode_bare |
| hgatp_mode_sv | When HSXLEN=32, the only other valid setting for MODE is Sv32x4, which is a modification of the usual Sv32 paged virtual-memory scheme, extended to support 34-bit guest physical addresses. When HSXLEN=64, modes Sv39x4, Sv48x4, and Sv57x4 are defined as modifications of the Sv39, Sv48, and Sv57 paged virtual-memory schemes. All of these paged virtual-memory schemes are described in . | norm:hgatp_mode_sv |
| HGATP_MODE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| A write to hgatp with an unsupported MODE value is not ignored as it is for satp. Instead, the fields of hgatp are WARL in the normal way, when so indicated. | norm:hgatp_mode_warl | |
| hgatp_ppn_op | As explained in , for the paged virtual-memory schemes (Sv32x4, Sv39x4, Sv48x4, and Sv57x4), the root page table is 16 KiB and must be aligned to a 16-KiB boundary. In these modes, the lowest two bits of the physical page number (PPN) in hgatp always read as zeros. An implementation that supports only the defined paged virtual-memory schemes and/or Bare may make PPN[1:0] read-only zero. | norm:hgatp_ppn_op |
| HGATP_VMID | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The number of VMID bits is UNSPECIFIED and may be zero. | norm:hgatp_vmid | |
| hgatp_vmid_lsbs | The least-significant bits of VMID are implemented first: that is, if VMIDLEN > 0, VMID[VMIDLEN-1:0] is writable. The maximal value of VMIDLEN, termed VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, Sv48x4, and Sv57x4. |
norm:hgatp_vmid_lsbs |
| vsstatus_sz | The vsstatus register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sstatus, formatted as shown in when VSXLEN=32 and when VSXLEN=64. When V=1, vsstatus substitutes for the usual sstatus, so instructions that normally read or modify sstatus actually access vsstatus instead. | norm:vsstatus_sz_acc_op |
| vsstatus_acc | The vsstatus register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sstatus, formatted as shown in when VSXLEN=32 and when VSXLEN=64. When V=1, vsstatus substitutes for the usual sstatus, so instructions that normally read or modify sstatus actually access vsstatus instead. | norm:vsstatus_sz_acc_op |
| vsstatus_op | The vsstatus register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sstatus, formatted as shown in when VSXLEN=32 and when VSXLEN=64. When V=1, vsstatus substitutes for the usual sstatus, so instructions that normally read or modify sstatus actually access vsstatus instead. | norm:vsstatus_sz_acc_op |
| vsstatus_uxl_op | The UXL field controls the effective XLEN for VU-mode, which may differ from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a WARL field that is encoded the same as the MXL field of misa, shown in . In particular, an implementation may make UXL be a read-only copy of field VSXL of hstatus, forcing VU-mode XLEN=VSXLEN. | norm:vsstatus_uxl_op |
| VSSTATUS_UXL_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| The UXL field controls the effective XLEN for VU-mode, which may differ from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a WARL field that is encoded the same as the MXL field of misa, shown in . In particular, an implementation may make UXL be a read-only copy of field VSXL of hstatus, forcing VU-mode XLEN=VSXLEN. | norm:vsstatus_uxl_op | |
| vsstatus_uxl_change | If VSXLEN is changed from 32 to a wider width, and if field UXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new VSXLEN. | norm:vsstatus_uxl_change |
| vsstatus_fs_op | When V=1, both vsstatus.FS and the HS-level sstatus.FS are in effect. Attempts to execute a floating-point instruction when either field is 0 (Off) raise an illegal-instruction exception. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). | norm:vsstatus_fs_op |
| vsstatus_vs_op | Similarly, when V=1, both vsstatus.VS and the HS-level sstatus.VS are in effect. Attempts to execute a vector instruction when either field is 0 (Off) raise an illegal-instruction exception. Modifying the vector state when V=1 causes both fields to be set to 3 (Dirty). | norm:vsstatus_vs_op |
| vsstatus_sd_xs_op | Read-only fields SD and XS summarize the extension context status as it is visible to VS-mode only. For example, the value of the HS-level sstatus.FS does not affect vsstatus.SD. | norm:vsstatus_sd_xs_op |
| VSSTATUS_UBE | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| An implementation may make field UBE be a read-only copy of hstatus.VSBE. | norm:vsstatus_ube | |
| vsstatus_v0 | When V=0, vsstatus does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the mstatus register is used to execute a load or store as though V=1. | norm:vsstatus_v0 |
| vsstatus_spelp_op | The Zicfilp extension adds the SPELP field that holds the previous ELP, and is updated as specified in . The SPELP field is encoded as follows: | norm:vsstatus_spelp_op |
| vsstatus_sdt_op | The Ssdbltrp adds an S-mode-disable-trap (SDT) field extension to address double trap (See ) in VS-mode. | norm:vsstatus_sdt_op |
| vsip_vsie_sz | The vsip and vsie registers are VSXLEN-bit read/write registers that are VS-mode’s versions of supervisor CSRs sip and sie, formatted as shown in and respectively. When V=1, vsip and vsie substitute for the usual sip and sie, so instructions that normally read or modify sip/sie actually access vsip/vsie instead. However, interrupts directed to HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1. | norm:vsip_vsie_sz_acc_op |
| vsip_vsie_acc | The vsip and vsie registers are VSXLEN-bit read/write registers that are VS-mode’s versions of supervisor CSRs sip and sie, formatted as shown in and respectively. When V=1, vsip and vsie substitute for the usual sip and sie, so instructions that normally read or modify sip/sie actually access vsip/vsie instead. However, interrupts directed to HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1. | norm:vsip_vsie_sz_acc_op |
| vsip_vsie_op | The vsip and vsie registers are VSXLEN-bit read/write registers that are VS-mode’s versions of supervisor CSRs sip and sie, formatted as shown in and respectively. When V=1, vsip and vsie substitute for the usual sip and sie, so instructions that normally read or modify sip/sie actually access vsip/vsie instead. However, interrupts directed to HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1. | norm:vsip_vsie_sz_acc_op |
| VSIP_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vsip_img | |
| VSIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vsie_img | |
| vsip_vsie_lcofi | Extension Shlcofideleg supports delegating LCOFI interrupts to VS-mode. If the Shlcofideleg extension is implemented, hideleg bit 13 is writable; otherwise, it is read-only zero. When bit 13 of hideleg is zero, vsip.LCOFIP and vsie.LCOFIE are read-only zeros. Else, vsip.LCOFIP and vsie.LCOFIE are aliases of sip.LCOFIP and sie.LCOFIE. | norm:vsip_vsie_lcofi |
| vsip_vsie_sei | When bit 10 of hideleg is zero, vsip.SEIP and vsie.SEIE are read-only zeros. Else, vsip.SEIP and vsie.SEIE are aliases of hip.VSEIP and hie.VSEIE. | norm:vsip_vsie_sei |
| vsip_vsie_sti | When bit 6 of hideleg is zero, vsip.STIP and vsie.STIE are read-only zeros. Else, vsip.STIP and vsie.STIE are aliases of hip.VSTIP and hie.VSTIE. | norm:vsip_vsie_sti |
| vsip_vsie_ssi | When bit 2 of hideleg is zero, vsip.SSIP and vsie.SSIE are read-only zeros. Else, vsip.SSIP and vsie.SSIE are aliases of hip.VSSIP and hie.VSSIE. | norm:vsip_vsie_ssi |
| vstvec_sz | The vstvec register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register stvec, formatted as shown in . When V=1, vstvec substitutes for the usual stvec, so instructions that normally read or modify stvec actually access vstvec instead. When V=0, vstvec does not directly affect the behavior of the machine. | norm:vstvec_sz_acc_op |
| vstvec_acc | The vstvec register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register stvec, formatted as shown in . When V=1, vstvec substitutes for the usual stvec, so instructions that normally read or modify stvec actually access vstvec instead. When V=0, vstvec does not directly affect the behavior of the machine. | norm:vstvec_sz_acc_op |
| vstvec_op | The vstvec register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register stvec, formatted as shown in . When V=1, vstvec substitutes for the usual stvec, so instructions that normally read or modify stvec actually access vstvec instead. When V=0, vstvec does not directly affect the behavior of the machine. | norm:vstvec_sz_acc_op |
| VSTVEC_MODE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vstvec_img | |
| VSTVEC_BASE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vstvec_img | |
| vsscratch_sz | The vsscratch register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sscratch, formatted as shown in . When V=1, vsscratch substitutes for the usual sscratch, so instructions that normally read or modify sscratch actually access vsscratch instead. The contents of vsscratch never directly affect the behavior of the machine. | norm:vsscratch_sz_acc_op |
| vsscratch_acc | The vsscratch register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sscratch, formatted as shown in . When V=1, vsscratch substitutes for the usual sscratch, so instructions that normally read or modify sscratch actually access vsscratch instead. The contents of vsscratch never directly affect the behavior of the machine. | norm:vsscratch_sz_acc_op |
| vsscratch_op | The vsscratch register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sscratch, formatted as shown in . When V=1, vsscratch substitutes for the usual sscratch, so instructions that normally read or modify sscratch actually access vsscratch instead. The contents of vsscratch never directly affect the behavior of the machine. | norm:vsscratch_sz_acc_op |
| vspec_sz | The vsepc register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sepc, formatted as shown in . When V=1, vsepc substitutes for the usual sepc, so instructions that normally read or modify sepc actually access vsepc instead. When V=0, vsepc does not directly affect the behavior of the machine. | norm:vspec_sz_acc_op |
| vspec_acc | The vsepc register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sepc, formatted as shown in . When V=1, vsepc substitutes for the usual sepc, so instructions that normally read or modify sepc actually access vsepc instead. When V=0, vsepc does not directly affect the behavior of the machine. | norm:vspec_sz_acc_op |
| vspec_op | The vsepc register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register sepc, formatted as shown in . When V=1, vsepc substitutes for the usual sepc, so instructions that normally read or modify sepc actually access vsepc instead. When V=0, vsepc does not directly affect the behavior of the machine. | norm:vspec_sz_acc_op |
| VSEPC_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| vsepc is a WARL register that must be able to hold the same set of values that sepc can hold. | norm:vsepc_warl | |
| vscause_sz | The vscause register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register scause, formatted as shown in . When V=1, vscause substitutes for the usual scause, so instructions that normally read or modify scause actually access vscause instead. When V=0, vscause does not directly affect the behavior of the machine. | norm:vscause_sz_acc_op |
| vscause_acc | The vscause register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register scause, formatted as shown in . When V=1, vscause substitutes for the usual scause, so instructions that normally read or modify scause actually access vscause instead. When V=0, vscause does not directly affect the behavior of the machine. | norm:vscause_sz_acc_op |
| vscause_op | The vscause register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register scause, formatted as shown in . When V=1, vscause substitutes for the usual scause, so instructions that normally read or modify scause actually access vscause instead. When V=0, vscause does not directly affect the behavior of the machine. | norm:vscause_sz_acc_op |
| VSCAUSE_WLRL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WLRL | Implementation-defined behavior category | |
| vscause is a WLRL register that must be able to hold the same set of values that scause can hold. | norm:vscause_wlrl | |
| vstval_sz | The vstval register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register stval, formatted as shown in . When V=1, vstval substitutes for the usual stval, so instructions that normally read or modify stval actually access vstval instead. When V=0, vstval does not directly affect the behavior of the machine. | norm:vstval_sz_acc_op |
| vstval_acc | The vstval register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register stval, formatted as shown in . When V=1, vstval substitutes for the usual stval, so instructions that normally read or modify stval actually access vstval instead. When V=0, vstval does not directly affect the behavior of the machine. | norm:vstval_sz_acc_op |
| vstval_op | The vstval register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register stval, formatted as shown in . When V=1, vstval substitutes for the usual stval, so instructions that normally read or modify stval actually access vstval instead. When V=0, vstval does not directly affect the behavior of the machine. | norm:vstval_sz_acc_op |
| VSTVAL_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| vstval is a WARL register that must be able to hold the same set of values that stval can hold. | norm:vstval_warl | |
| vsatp_sz | The vsatp register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register satp, formatted as shown in for VSXLEN=32 and for VSXLEN=64. When V=1, vsatp substitutes for the usual satp, so instructions that normally read or modify satp actually access vsatp instead. vsatp controls VS-stage address translation, the first stage of two-stage translation for guest virtual addresses (see ). | norm:vsatp_sz_acc_op |
| vsatp_acc | The vsatp register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register satp, formatted as shown in for VSXLEN=32 and for VSXLEN=64. When V=1, vsatp substitutes for the usual satp, so instructions that normally read or modify satp actually access vsatp instead. vsatp controls VS-stage address translation, the first stage of two-stage translation for guest virtual addresses (see ). | norm:vsatp_sz_acc_op |
| vsatp_op | The vsatp register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register satp, formatted as shown in for VSXLEN=32 and for VSXLEN=64. When V=1, vsatp substitutes for the usual satp, so instructions that normally read or modify satp actually access vsatp instead. vsatp controls VS-stage address translation, the first stage of two-stage translation for guest virtual addresses (see ). | norm:vsatp_sz_acc_op |
| vsatp_ppn_sv32_sz | The vsatp register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register satp, formatted as shown in for VSXLEN=32 and for VSXLEN=64. When V=1, vsatp substitutes for the usual satp, so instructions that normally read or modify satp actually access vsatp instead. vsatp controls VS-stage address translation, the first stage of two-stage translation for guest virtual addresses (see ). | norm:vsatp_sz_acc_op |
| 22-bit physical page number (PPN) | norm:satp_ppn_sv32_sz | |
| vsatp_ppn_sv39_sv48_sv57_sz | The vsatp register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register satp, formatted as shown in for VSXLEN=32 and for VSXLEN=64. When V=1, vsatp substitutes for the usual satp, so instructions that normally read or modify satp actually access vsatp instead. vsatp controls VS-stage address translation, the first stage of two-stage translation for guest virtual addresses (see ). | norm:vsatp_sz_acc_op |
| 44-bit PPN | norm:satp_ppn_sv39_sz | |
| 44-bit PPN | norm:satp_ppn_sv48_sz | |
| 44-bit PPN | norm:satp_ppn_sv57_sz | |
| vsatp_mode_unsupported_v0 | When V=0, a write to vsatp with an unsupported MODE value is either ignored as it is for satp, or the fields of vsatp are treated as WARL in the normal way. |
norm:vsatp_mode_unsupported_v0 |
| VSATP_MODE_UNSUPPORTED_V0_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| When V=0, a write to vsatp with an unsupported MODE value is either ignored as it is for satp, or the fields of vsatp are treated as WARL in the normal way. |
norm:vsatp_mode_unsupported_v0 | |
| vsatp_mode_unsupported_v1 | However, when V=1, a write to satp with an unsupported MODE value is ignored and no write to vsatp is effected. |
norm:vsatp_mode_unsupported_v1 |
| vsatp_v0 | When V=0, vsatp does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the mstatus register is used to execute a load or store as though V=1. | norm:vsatp_v0 |
| vs_stage_speculative_a_bit | when vsatp is active, VS-stage page-table entries’ A bits must not be set as a result of speculative execution, unless the effective privilege mode is VS or VU. |
norm:vs_stage_speculative_a_bit |
| hlsv_priv | Each instruction performs an explicit memory access with an effective privilege mode of VS or VU. The effective privilege mode of the explicit memory access is VU when hstatus.SPVP=0, and VS when hstatus.SPVP=1. |
norm:hlsv_priv |
| hlsv_trans | As usual for VS-mode and VU-mode, two-stage address translation is applied, and the HS-level sstatus.SUM is ignored. |
norm:hlsv_trans |
| hlsv_sstatus_mxr | HS-level sstatus.MXR makes execute-only pages readable by explicit loads for both stages of address translation (VS-stage and G-stage) |
norm:hlsv_sstatus_mxr |
| hlsv_vsstatus_mxr | vsstatus.MXR affects only the first translation stage (VS-stage). |
norm:hlsv_vsstatus_mxr |
| hlsv_mode | The hypervisor virtual-machine load and store instructions are valid only in M-mode or HS-mode, or in U-mode when hstatus.HU=1. |
norm:hlsv_mode |
| hlsv_op | For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D. For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D. Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course. | norm:hlsv_op |
| hlsv_u_op | Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation. That is, the memory being read must be executable in both stages of address translation, but read permission is not required. For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine’s physical memory attributes as modified by physical memory protection, , for supervisor level.) | norm:hlsv_u_op |
| hlvx-wu_valid32 | HLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.) | norm:hlvx-wu_valid32 |
| hlsv_virtinst | Attempts to execute a virtual-machine load/store instruction (HLV, HLVX, or HSV) when V=1 cause a virtual-instruction exception. |
norm:hlsv_virtinst |
| hlsv_illegalinst | Attempts to execute one of these same instructions from U-mode when hstatus.HU=0 cause an illegal-instruction exception. |
norm:hlsv_illegalinst |
| hfence-vvma_hfence-gvma_op | The hypervisor memory-management fence instructions, HFENCE.VVMA and HFENCE.GVMA, perform a function similar to SFENCE.VMA (), except applying to the VS-level memory-management data structures controlled by CSR vsatp (HFENCE.VVMA) or the guest-physical memory-management data structures controlled by CSR hgatp (HFENCE.GVMA). Instruction SFENCE.VMA applies only to the memory-management data structures controlled by the current satp (either the HS-level satp when V=0 or vsatp when V=1). | norm:hfence-vvma_hfence-gvma_op |
| hfence-vvma_mode | HFENCE.VVMA is valid only in M-mode or HS-mode. Its effect is much the same as temporarily entering VS-mode and executing SFENCE.VMA. Executing an HFENCE.VVMA guarantees that any previous stores already visible to the current hart are ordered before all implicit reads by that hart done for VS-stage address translation for instructions that | norm:hfence-vvma_mode |
| hfence-vvma_limits | Implicit reads need not be ordered when hgatp.VMID is different than at the time HFENCE.VVMA executed. If operand rs1≠x0, it specifies a single guest virtual address, and if operand rs2≠x0, it specifies a single guest address-space identifier (ASID). | norm:hfence-vvma_limits |
| hfence-vvma_asid | When rs2≠x0, bits XLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use. Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations. Furthermore, if ASIDLEN < ASIDMAX, the implementation shall ignore bits ASIDMAX-1:ASIDLEN of the value held in rs2. | norm:hfence-vvma_asid |
| hfence-vvma_tvm | Neither mstatus.TVM nor hstatus.VTVM causes HFENCE.VVMA to trap. | norm:hfence-vvma_tvm |
| hfence-gvma_op | HFENCE.GVMA is valid only in HS-mode when mstatus.TVM=0, or in M-mode (irrespective of mstatus.TVM). Executing an HFENCE.GVMA instruction guarantees that any previous stores already visible to the current hart are ordered before all implicit reads by that hart done for G-stage address translation for instructions that follow the HFENCE.GVMA. If operand rs1≠x0, it specifies a single guest physical address, shifted right by 2 bits, and if operand rs2≠x0, it specifies a single virtual machine identifier (VMID). | norm:hfence-gvma_op |
| hfence-gvma_vmid | When rs2≠x0, bits XLEN-1:VMIDMAX of the value held in rs2 are reserved for future standard use. Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations. Furthermore, if VMIDLEN < VMIDMAX, the implementation shall ignore bits VMIDMAX-1:VMIDLEN of the value held in rs2. | norm:hfence-gvma_vmid |
| hfence-gvma_mode | If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0 (and rs2 set to either x0 or the VMID) must be executed to order subsequent guest translations with the MODE change—even if the old MODE or new MODE is Bare. | norm:hfence-gvma_mode |
| hfence-vvma_hfence-gvma_exceptions | Attempts to execute HFENCE.VVMA or HFENCE.GVMA when V=1 cause a virtual-instruction exception, while attempts to do the same in U-mode cause an illegal-instruction exception. Attempting to execute HFENCE.GVMA in HS-mode when mstatus.TVM=1 also causes an illegal-instruction exception. | norm:hfence-vvma_hfence-gvma_exceptions |
| mstatus_mpv_op | The MPV bit (Machine Previous Virtualization Mode) is written by the implementation whenever a trap is taken into M-mode. Just as the MPP field is set to the (nominal) privilege mode at the time of the trap, the MPV bit is set to the value of the virtualization mode V at the time of the trap. When an MRET instruction is executed, the virtualization mode V is set to MPV, unless MPP=3, in which case V remains 0. | norm:mstatus_mpv_op |
| mstatus_gva_op | Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into M-mode. For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to mtval, GVA is set to 1. For any other trap into M-mode, GVA is set to 0. | norm:mstatus_gva_op |
| mstatus_modes | The TSR and TVM fields of mstatus affect execution only in HS-mode, not in VS-mode. The TW field affects execution in all modes except M-mode. | norm:mstatus_modes |
| mstatus_tvm_hs | Setting TVM=1 prevents HS-mode from accessing hgatp or executing HFENCE.GVMA or HINVAL.GVMA, but has no effect on accesses to vsatp or instructions HFENCE.VVMA or HINVAL.VVMA. | norm:mstatus_tvm_hs |
| mstatus_mprv_hypervisor | The hypervisor extension changes the behavior of the Modify Privilege field, MPRV, of mstatus. When MPRV=0, translation and protection behave as normal. When MPRV=1, explicit memory accesses are translated and protected, and endianness is applied, as though the current virtualization mode were set to MPV and the current nominal privilege mode were set to MPP. enumerates the cases. | norm:mstatus_mprv_hypervisor |
| mstatus_mprv_hlsv | MPRV does not affect the virtual-machine load/store instructions, HLV, HLVX, and HSV. The explicit loads and stores of these instructions always act as though V=1 and the nominal privilege mode were hstatus.SPVP, overriding MPRV. | norm:mstatus_mprv_hlsv |
| mideleg_acc_h | When the hypervisor extension is implemented, bits 10, 6, and 2 of mideleg (corresponding to the standard VS-level interrupts) are each read-only one. Furthermore, if any guest external interrupts are implemented (GEILEN is nonzero), bit 12 of mideleg (corresponding to supervisor-level guest external interrupts) is also read-only one. VS-level interrupts and guest external interrupts are always delegated past M-mode to HS-mode. | norm:mideleg_acc_h |
| mideleg_hroz | For bits of mideleg that are zero, the corresponding bits in hideleg, hip, and hie are read-only zeros. | norm:mideleg_hroz |
| mip_mie_vs | The hypervisor extension gives registers mip and mie additional active bits for the hypervisor-added interrupts. and show the standard portions (bits 15:0) of registers mip and mie when the hypervisor extension is implemented. | norm:mip_mie_vs |
| mip_mie_alias | Bits SGEIP, VSEIP, VSTIP, and VSSIP in mip are aliases for the same bits in hypervisor CSR hip, while SGEIE, VSEIE, VSTIE, and VSSIE in mie are aliases for the same bits in hie. | norm:mip_mie_alias |
| mtval2_sz | The mtval2 register is an MXLEN-bit read/write register formatted as shown in . When a trap is taken into M-mode, mtval2 is written with additional exception-specific information, alongside mtval, to assist software in handling the trap. | norm:mtval2_sz_acc_op |
| mtval2_acc | The mtval2 register is an MXLEN-bit read/write register formatted as shown in . When a trap is taken into M-mode, mtval2 is written with additional exception-specific information, alongside mtval, to assist software in handling the trap. | norm:mtval2_sz_acc_op |
| mtval2_op | The mtval2 register is an MXLEN-bit read/write register formatted as shown in . When a trap is taken into M-mode, mtval2 is written with additional exception-specific information, alongside mtval, to assist software in handling the trap. | norm:mtval2_sz_acc_op |
| MTVAL2_TRAPVAL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| When a guest-page-fault trap is taken into M-mode, mtval2 is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, mtval2 is set to zero, but a future standard or extension may redefine mtval2’s setting for other traps. | norm:mtval2_trapval | |
| mtval2_trapval_vstrans | If a guest-page fault is due to an implicit memory access during first-stage (VS-stage) address translation, a guest physical address written to mtval2 is that of the implicit memory access that faulted. Additional information is provided in CSR mtinst to disambiguate such situations. | norm:mtval2_trapval_vstrans |
| mtval2_trapval_other | Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in mtval2 corresponds to the faulting portion of the access as indicated by the virtual address in mtval. For instruction guest-page faults on systems with variable-length instructions, a nonzero mtval2 corresponds to the faulting portion of the instruction as indicated by the virtual address in mtval. | norm:mtval2_trapval_other |
| mtval2_val | mtval2 is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:mtval2_val |
| MTVAL2_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| mtval2 is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:mtval2_val | |
| mtval2_Ssdbltrap | The Ssdbltrap extension (See ) requires the implementation of the mtval2 CSR. | norm:mtval2_Ssdbltrap |
| mtinst_sz | The mtinst register is an MXLEN-bit read/write register formatted as shown in . When a trap is taken into M-mode, mtinst is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap. The values that may be written to mtinst on a trap are documented in . | norm:mtinst_sz_acc_op |
| mtinst_acc | The mtinst register is an MXLEN-bit read/write register formatted as shown in . When a trap is taken into M-mode, mtinst is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap. The values that may be written to mtinst on a trap are documented in . | norm:mtinst_sz_acc_op |
| mtinst_op | The mtinst register is an MXLEN-bit read/write register formatted as shown in . When a trap is taken into M-mode, mtinst is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap. The values that may be written to mtinst on a trap are documented in . | norm:mtinst_sz_acc_op |
| mtinst_val | mtinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:mtinst_val |
| MTINST_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| mtinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:mtinst_val | |
| H_vm_twostage | Whenever the current virtualization mode V is 1, two-stage address translation and protection is in effect. For any virtual memory access, the original virtual address is converted in the first stage by VS-level address translation, as controlled by the vsatp register, into a guest physical address. The guest physical address is then converted in the second stage by guest physical address translation, as controlled by the hgatp register, into a supervisor physical address. The two stages are known also as VS-stage and G-stage translation. Although there is no option to disable two-stage address translation when V=1, either stage of translation can be effectively disabled by zeroing the corresponding vsatp or hgatp register. | norm:H_vm_twostage |
| vsstatus_mxr_vm | The vsstatus field MXR, which makes execute-only pages readable by explicit loads, only overrides VS-stage page protection. Setting MXR at VS-level does not override guest-physical page protections. |
norm:vsstatus_mxr_vm |
| sstatus_mxr_vm | Setting MXR at HS-level, however, overrides both VS-stage and G-stage execute-only permissions. |
norm:sstatus_mxr_vm |
| H_vm_gstagetrans | When V=1, memory accesses that would normally bypass address translation are subject to G-stage address translation alone. This includes memory accesses made in support of VS-stage address translation, such as reads and writes of VS-level page tables. | norm:H_vm_gstagetrans |
| H_pmp | Machine-level physical memory protection applies to supervisor physical addresses and is in effect regardless of virtualization mode. | norm:H_pmp |
| hgatp_mode_bare_trans | When the address translation scheme selected by the MODE field of hgatp is Bare, guest physical addresses are equal to supervisor physical addresses without modification, and no memory protection applies in the trivial translation of guest physical addresses to supervisor physical addresses. | norm:hgatp_mode_bare_trans |
| hgatp_mode_x4 | When hgatp.MODE specifies a translation scheme of Sv32x4, Sv39x4, Sv48x4, or Sv57x4, G-stage address translation is a variation on the usual page-based virtual address translation scheme of Sv32, Sv39, Sv48, or Sv57, respectively. In each case, the size of the incoming address is widened by 2 bits (to 34, 41, 50, or 59 bits). To accommodate the 2 extra bits, the root page table (only) is expanded by a factor of four to be 16 KiB instead of the usual 4 KiB. Matching its larger size, the root page table also must be aligned to a 16 KiB boundary instead of the usual 4 KiB page boundary. Except as noted, all other aspects of Sv32, Sv39, Sv48, or Sv57 are adopted unchanged for G-stage translation. Non-root page tables and all page table entries (PTEs) have the same formats as documented in , , , and . | norm:hgatp_mode_x4 |
| hgatp_mode_sv32x4 | For Sv32x4, an incoming guest physical address is partitioned into a virtual page number (VPN) and page offset as shown in . This partitioning is identical to that for an Sv32 virtual address as depicted in , except with 2 more bits at the high end in VPN[1]. (Note that the fields of a partitioned guest physical address also correspond one-for-one with the structure that Sv32 assigns to a physical address, depicted in .) | norm:hgatp_mode_sv32x4 |
| hgatp_mode_sv39x4 | For Sv39x4, an incoming guest physical address is partitioned as shown in . This partitioning is identical to that for an Sv39 virtual address as depicted in , except with 2 more bits at the high end in VPN[2]. Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs. | norm:hgatp_mode_sv39x4 |
| hgatp_mode_sv48x4 | For Sv48x4, an incoming guest physical address is partitioned as shown in . This partitioning is identical to that for an Sv48 virtual address as depicted in , except with 2 more bits at the high end in VPN[3]. Address bits 63:50 must all be zeros, or else a guest-page-fault exception occurs. | norm:hgatp_mode_sv48x4 |
| hgatp_mode_sv57x4 | For Sv57x4, an incoming guest physical address is partitioned as shown in . This partitioning is identical to that for an Sv57 virtual address as depicted in , except with 2 more bits at the high end in VPN[4]. Address bits 63:59 must all be zeros, or else a guest-page-fault exception occurs. | norm:hgatp_mode_sv57x4 |
| H_vm_gpatrans | The conversion of an Sv32x4, Sv39x4, Sv48x4, or Sv57x4 guest physical address is accomplished with the same algorithm used for Sv32, Sv39, Sv48, or Sv57, as presented in , except that: | norm:H_vm_gpatrans |
| H_vm_gpapriv | For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be user-level accesses, as though executed in U-mode. Access type permissions—readable, writable, or executable—are checked during G-stage translation the same as for VS-stage translation. For a memory access made to support VS-stage address translation (such as to read/write a VS-level page table), permissions and the need to set A and/or D bits at the G-stage level are checked as though for an implicit load or store, not for the original access type. However, any exception is always reported for the original access type (instruction, load, or store/AMO). | norm:H_vm_gpapriv |
| H_vm_gpa_g | The G bit in all G-stage PTEs is currently not used. Until its use is defined by a standard extension, it should be cleared by software for forward compatibility, and must be ignored by hardware. | norm:H_vm_gpa_g |
| H_guest_page_fault | Guest-page-fault traps may be delegated from M-mode to HS-mode under the control of CSR medeleg, but cannot be delegated to other privilege modes. On a guest-page fault, CSR mtval or stval is written with the faulting guest virtual address as usual, and mtval2 or htval is written either with zero or with the faulting guest physical address, shifted right by 2 bits. CSR mtinst or htinst may also be written with information about the faulting instruction or other reason for the access, as explained in . | norm:H_guest_page_fault |
| H_straddle | When an instruction fetch or a misaligned memory access straddles a page boundary, two different address translations are involved. When a guest-page fault occurs in such a circumstance, the faulting virtual address written to mtval/stval is the same as would be required for a regular page fault. Thus, the faulting virtual address may be a page-boundary address that is higher than the instruction’s original virtual address, if the byte at that page boundary is among the accessed bytes. | norm:H_straddle |
| mtval2_htval_virtaddr | When a guest-page fault is not due to an implicit memory access for VS-stage address translation, a nonzero guest physical address written to mtval2/htval shall correspond to the exact virtual address written to mtval/stval. | norm:mtval2_htval_virtaddr |
| sfence_vma_v0 | The behavior of the SFENCE.VMA instruction is affected by the current virtualization mode V. When V=0, the virtual-address argument is an HS-level virtual address, and the ASID argument is an HS-level ASID. The instruction orders stores only to HS-level address-translation structures with subsequent HS-level address translations. | norm:sfence_vma_v0 |
| sfence_vma_v1 | When V=1, the virtual-address argument to SFENCE.VMA is a guest virtual address within the current virtual machine, and the ASID argument is a VS-level ASID within the current virtual machine. The current virtual machine is identified by the VMID field of CSR hgatp, and the effective ASID can be considered to be the combination of this VMID with the VS-level ASID. The SFENCE.VMA instruction orders stores only to the VS-level address-translation structures with subsequent VS-stage address translations for the same virtual machine, i.e., only when hgatp.VMID is the same as when the SFENCE.VMA executed. | norm:sfence_vma_v1 |
| H_cause | The hypervisor extension augments the trap cause encoding. lists the possible M-mode and HS-mode trap cause codes when the hypervisor extension is implemented. Codes are added for VS-level interrupts (interrupts 2, 6, 10), for supervisor-level guest external interrupts (interrupt 12), for virtual-instruction exceptions (exception 22), and for guest-page faults (exceptions 20, 21, 23). Furthermore, environment calls from VS-mode are assigned cause 10, whereas those from HS-mode or S-mode use cause 9 as usual. | norm:H_cause |
| H_cause_ecall | HS-mode and VS-mode ECALLs use different cause values so they can be delegated separately. | norm:H_cause_ecall |
| H_cause_virtual_instruction | When V=1, a virtual-instruction exception (code 22) is normally raised instead of an illegal-instruction exception if the attempted instruction is HS-qualified but is prevented from executing when V=1 either due to insufficient privilege or because the instruction is expressly disabled by a supervisor or hypervisor CSR such as scounteren or hcounteren. An instruction is HS-qualified if it would be valid to execute in HS-mode (for some values of the instruction’s register operands), assuming fields TSR and TVM of CSR mstatus are both zero. | norm:H_cause_virtual_instruction |
| H_cause_virtual_instruction_high | A special rule applies for CSR instructions that access 32-bit high-half CSRs such as cycleh and htimedeltah. When V=1 and XLEN=32, an invalid attempt to access a high-half CSR raises a virtual-instruction exception instead of an illegal-instruction exception if the same CSR instruction for the corresponding low-half CSR (e.g.cycle or htimedelta) is HS-qualified. | norm:H_cause_virtual_instruction_high |
| H_illegal_high_half | When XLEN>32, an attempt to access a high-half CSR always raises an illegal-instruction exception. | norm:H_illegal_high_half |
| H_virtinst_vs_nonhighctr_h0_m1 | in VS-mode, attempts to access a non-high-half counter CSR when the corresponding bit in hcounteren is 0 and the same bit in mcounteren is 1; |
norm:H_virtinst_vs_nonhighctr_h0_m1 |
| H_virtinst_vs32_highctr_h0_m1 | in VS-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in hcounteren is 0 and the same bit in mcounteren is 1; |
norm:H_virtinst_vs32_highctr_h0_m1 |
| H_virtinst_vu_nonhighctr_h0_s0_m1 | in VU-mode, attempts to access a non-high-half counter CSR when the corresponding bit in either hcounteren or scounteren is 0 and the same bit in mcounteren is 1; |
norm:H_virtinst_vu_nonhighctr_h0_s0_m1 |
| H_virtinst_vu32_highctr_h0_s0_m1 | in VU-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in either hcounteren or scounteren is 0 and the same bit in mcounteren is 1; |
norm:H_virtinst_vu32_highctr_h0_s0_m1 |
| H_virtinst_vu_vs_hinst | in VS-mode or VU-mode, attempts to execute a hypervisor instruction (HLV, HLVX, HSV, or HFENCE); |
norm:H_virtinst_vu_vs_hinst |
| H_virtinst_vu_vs_nonhigh_allowedhs_tvm0 | in VS-mode or VU-mode, attempts to access an implemented non-high-half hypervisor CSR or VS CSR when the same access (read/write) would be allowed in HS-mode, assuming mstatus.TVM=0; |
norm:H_virtinst_vu_vs_nonhigh_allowedhs_tvm0 |
| H_virtinst_vu_vs32_high_allowedhs_tvm0 | in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented high-half hypervisor CSR or high-half VS CSR when the same access (read/write) to the CSR"s low-half partner would be allowed in HS-mode, assuming mstatus.TVM=0; |
norm:H_virtinst_vu_vs32_high_allowedhs_tvm0 |
| H_virtinst_vu_wfi_tw0 | in VU-mode, attempts to execute WFI when mstatus.TW=0 | norm:H_virtinst_vu_wfi_tw0 |
| H_virtinst_vu_sret_sfence | or to execute a supervisor instruction (SRET or SFENCE); |
norm:H_virtinst_vu_sret_sfence |
| H_virtinst_vu_nonhigh_supervisor_allowedhs_tvm0 | in VU-mode, attempts to access an implemented non-high-half supervisor CSR when the same access (read/write) would be allowed in HS-mode, assuming mstatus.TVM=0; |
norm:H_virtinst_vu_nonhigh_supervisor_allowedhs_tvm0 |
| H_virtinst_vu32_high_supervisor_allowedhs_tvm0 | in VU-mode, if XLEN=32, attempts to access an implemented high-half supervisor CSR when the same access to the CSR's low-half partner would be allowed in HS-mode, assuming mstatus.TVM=0; |
norm:H_virtinst_vu32_high_supervisor_allowedhs_tvm0 |
| H_virtinst_wfi_vtw1_tw0 | in VS-mode, attempts to execute WFI when hstatus.VTW=1 and mstatus.TW=0, unless the instruction completes within an implementation-specific, bounded time; |
norm:H_virtinst_wfi_vtw1_tw0 |
| H_virtinst_vs_sret_vtsr1 | in VS-mode, attempts to execute SRET when hstatus.VTSR=1 | norm:H_virtinst_vs_sret_vtsr1 |
| H_virtinst_vs_sfence_sinval_satp_vtvm1 | in VS-mode, attempts to execute an SFENCE.VMA or SINVAL.VMA instruction or to access satp, when hstatus.VTVM=1. |
norm:H_virtinst_vs_sfence_sinval_satp_vtvm1 |
| H_virtinst_xtval | On a virtual-instruction trap, mtval or stval is written the same as for an illegal-instruction trap. | norm:H_virtinst_xtval |
| H_illegalinst_xstatus_fs_vs | Fields FS and VS in registers sstatus and vsstatus deviate from the usual HS-qualified rule. If an instruction is prevented from executing because FS or VS is zero in either sstatus or vsstatus, the exception raised is always an illegal-instruction exception, never a virtual-instruction exception. | norm:H_illegalinst_xstatus_fs_vs |
| H_exception_priority | If an instruction may raise multiple synchronous exceptions, the decreasing priority order of indicates which exception is taken and reported in mcause or scause. | norm:H_exception_priority |
| H_trap_deleg | When a trap occurs in HS-mode or U-mode, it goes to M-mode, unless delegated by medeleg or mideleg, in which case it goes to HS-mode. When a trap occurs in VS-mode or VU-mode, it goes to M-mode, unless delegated by medeleg or mideleg, in which case it goes to HS-mode, unless further delegated by hedeleg or hideleg, in which case it goes to VS-mode. | norm:H_trap_deleg |
| H_trap_m_csrwrites | When a trap is taken into M-mode, virtualization mode V gets set to 0, and fields MPV and MPP in mstatus (or mstatush) are set according to . A trap into M-mode also writes fields GVA, MPIE, and MIE in mstatus/mstatush and writes CSRs mepc, mcause, mtval, mtval2, and mtinst. | norm:H_trap_m_csrwrites |
| H_trap_hs_csrwrites | When a trap is taken into HS-mode, virtualization mode V is set to 0, and hstatus.SPV and sstatus.SPP are set according to . If V was 1 before the trap, field SPVP in hstatus is set the same as sstatus.SPP; otherwise, SPVP is left unchanged. A trap into HS-mode also writes field GVA in hstatus, fields SPIE and SIE in sstatus, and CSRs sepc, scause, stval, htval, and htinst. | norm:H_trap_hs_csrwrites |
| H_trap_vs_csrwrites | When a trap is taken into VS-mode, vsstatus.SPP is set according to . Register hstatus and the HS-level sstatus are not modified, and the virtualization mode V remains 1. A trap into VS-mode also writes fields SPIE and SIE in vsstatus and writes CSRs vsepc, vscause, and vstval. | norm:H_trap_vs_csrwrites |
| H_trap_xtinst | On any trap into M-mode or HS-mode, one of these values is written automatically into the appropriate trap instruction CSR, mtinst or htinst: | norm:H_trap_xtinst |
| H_trap_xtinst_interrupt | On an interrupt, the value written to the trap instruction register is always zero. |
norm:H_trap_xtinst_interrupt |
| H_trap_xtinst_exception | On a synchronous exception, if a nonzero value is written, one of the following shall be true about the value: |
norm:H_trap_xtinst_exception_lead-in |
| Bit 0 is 1, and replacing bit 1 with 1 makes the value into a valid encoding of a standard instruction. In this case, the instruction that trapped is the same kind as indicated by the register value, and the register value is the transformation of the trapping instruction, as defined later. For example, if bits 1:0 are binary 11 and the register value is the encoding of a standard LW (load word) instruction, then the trapping instruction is LW, and the register value is the transformation of the trapping LW instruction. Bit 0 is 1, and replacing bit 1 with 1 makes the value into an instruction encoding that is explicitly designated for a custom instruction (not an unused reserved encoding). This is a custom value. The instruction that trapped is a non-standard instruction. The interpretation of a custom value is not otherwise specified by this standard. The value is one of the special pseudoinstructions defined later, all of which have bits 1:0 equal to 00. |
norm:H_trap_xtinst_exception_list | |
| H_trap_xtinst_val | shows the values that may be automatically written to the trap instruction register for each standard exception cause. For exceptions that prevent the fetching of an instruction, only zero or a pseudoinstruction value may be written. A custom value may be automatically written only if the instruction that traps is non-standard. A future standard or extension may permit other values to be written, chosen from the set of allowed values established earlier. | norm:H_trap_xtinst_val |
| H_trap_xtinst_guestpage | For guest-page faults, the trap instruction register is written with a special pseudoinstruction value if: (a) the fault is caused by an implicit memory access for VS-stage address translation, and (b) a nonzero value (the faulting guest physical address) is written to mtval2 or htval. If both conditions are met, the value written to mtinst or htinst must be taken from ; zero is not allowed. | norm:H_trap_xtinst_guestpage |
| H_trap_xtinst_guestpage_rw | A write pseudoinstruction (0x00002020 or 0x00003020) is used for the case that the machine is attempting automatically to update bits A and/or D in VS-level page tables. All other implicit memory accesses for VS-stage address translation will be reads. If a machine never automatically updates bits A or D in VS-level page tables (leaving this to software), the write case will never arise. The fact that such a page table update must actually be atomic, not just a simple write, is ignored for the pseudoinstruction. | norm:H_trap_xtinst_guestpage_rw |
| mret_h | The MRET instruction is used to return from a trap taken into M-mode. MRET first determines what the new privilege mode will be according to the values of MPP and MPV in mstatus or mstatush, as encoded in . MRET then in mstatus/mstatush sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1. Lastly, MRET sets the privilege mode as previously determined, and sets pc=mepc. | norm:mret_h |
| sret_h | The SRET instruction is used to return from a trap taken into HS-mode or VS-mode. Its behavior depends on the current virtualization mode. | norm:sret_h |
| mret_v0 | When executed in M-mode or HS-mode (i.e., V=0), SRET first determines what the new privilege mode will be according to the values in hstatus.SPV and sstatus.SPP, as encoded in . SRET then sets hstatus.SPV=0, and in sstatus sets SPP=0, SIE=SPIE, and SPIE=1. Lastly, SRET sets the privilege mode as previously determined, and sets pc=sepc. | norm:mret_v0 |
| mret_v1 | When executed in VS-mode (i.e., V=1), SRET sets the privilege mode according to , in vsstatus sets SPP=0, SIE=SPIE, and SPIE=1, and lastly sets pc=vsepc. | norm:mret_v1 |
| mret_dt | If the Ssdbltrp extension is implemented, when SRET is executed in HS-mode, if the new privilege mode is VU, the SRET instruction sets vsstatus.SDT to 0. When executed in VS-mode, vsstatus.SDT is set to 0. | norm:mret_dt |
| vstimecmp_sz | vstimecmp is a 64-bit CSR with 64-bit precision | Rule's "summary" property |
| The vstimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems. |
norm:vstimecmp_sz | |
| vstimecmp_acc | In RV32, vstimecmp low bits accessed via vstimecmp, high bits via vstimecmph | Rule's "summary" property |
| In RV32 only, accesses to the vstimecmp CSR access the low 32 bits, while accesses to the vstimecmph CSR access the high 32 bits of vstimecmp. |
norm:vstimecmp_acc | |
| hip_vstip_op | VS timer interrupt pending in hip.VSTIP when (time+htimedelta) >= vstimecmp | Rule's "summary" property |
| A virtual supervisor timer interrupt becomes pending, as reflected in the VSTIP bit in the hip register, whenever (time + htimedelta), truncated to 64 bits, contains a value greater than or equal to vstimecmp, treating the values as unsigned integers. |
norm:hip_vstip_op | |
| hip_vstip_clear | hip.VSTIP cleared when vstimecmp > (time+htimedelta) | Rule's "summary" property |
| If the result of this comparison changes, it is guaranteed to be reflected in VSTIP eventually, but not necessarily immediately. The interrupt remains posted until vstimecmp becomes greater than (time + htimedelta), typically as a result of writing vstimecmp. |
norm:hip_vstip_clear | |
| hip_vstip_enable | VS timer interrupt taken based on enable/delegation rules while V=1 | Rule's "summary" property |
| The interrupt will be taken based on the standard interrupt enable and delegation rules while V=1. |
norm:hip_vstip_enable | |
| henvcfg_stce | The Sstc extension adds the STCE (STimecmp Enable) bit to henvcfg CSR. When the Sstc extension is not implemented, STCE is read-only zero. The STCE bit enables vstimecmp for VS-mode when set to one. When STCE bit is henvcfg is zero, an attempt to access stimecmp (really vstimecmp) when V=1 raises a virtual-instruction exception, and VSTIP in hip reverts to its defined behavior as if this extension is not implemented. | norm:henvcfg_stce |
| henvcfg_cbze | The Zicboz extension adds the CBZE (Cache Block Zero instruction enable) field to henvcfg. The CBZE field applies to execution of the cache block zero instruction (CBO.ZERO) in privilege modes VS and VU, and only when the instruction is HS-qualified. If the instruction is not HS-qualified, it raises an illegal-instruction exception. If the instruction is HS-qualified and the CBZE field is set to 1, the instruction is enabled for execution; otherwise, if the CBZE field is set to 0, it raises a virtual-instruction exception. When the Zicboz extension is not implemented, CBZE is read-only zero. | norm:henvcfg_cbze |
| henvcfg_cbcfe | The Zicbom extension adds the CBCFE (Cache Block Clean and Flush instruction Enable) field to henvcfg. When V=1, if the CBO.CLEAN and CBO.FLUSH instructions are not HS-qualified, they raise an illegal-instruction exception. If the instructions are HS-qualified and the CBCFE field is set to 1, the instructions are enabled for execution; otherwise, if the CBCFE field is set to 0, they raise a virtual-instruction exception. When the Zicbom extension is not implemented, CBCFE is read-only zero. | norm:henvcfg_cbcfe |
| henvcfg_cbie | The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to henvcfg. The CBIE field controls execution of the cache block invalidate instruction (CBO.INVAL) in privilege modes VS and VU. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. | norm:henvcfg_cbie |
| HENVCFG_CBIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to henvcfg. The CBIE field controls execution of the cache block invalidate instruction (CBO.INVAL) in privilege modes VS and VU. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. | norm:henvcfg_cbie | |
| cbo-inval_h-mode_veq1_op | When V=1, if the CBO.INVAL instruction is not HS-qualified, it raises an illegal-instruction exception. If the instruction is HS-qualified and the CBIE field is set to 01b or 11b, the instruction is enabled for execution; otherwise, it raises a virtual-instruction exception. | norm:cbo-inval_h-mode_veq1_op |
| cbo-inval_h-mode_op | If CBO.INVAL is enabled in HS-mode to perform a flush operation, then when the instruction is enabled in VS- or VU-mode it performs a flush operation, even if CBIE is set to 11b. Otherwise, when the instruction is enabled for execution, its behavior depends on the CBIE encoding, as follows: |
norm:cbo-inval_h-mode_op0 |
| (No text available) | norm:cbo-inval_h-mode_op1 | |
| (No text available) | norm:cbo-inval_h-mode_op2 |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| csr_access | A CSR accessible via one method may or may not be accessible via the other method. |
norm:csr_access |
| select_value_separate_address_space | Select values are a separate address space from CSR numbers, and from tselect values in the Sdtrig extension. |
norm:select_value_separate_address_space |
| select_value_unrelated | If a CSR is both directly and indirectly accessible, the CSR's select value is unrelated to its CSR number. |
norm:select_value_unrelated |
| csrs_alias | Machine-level and Supervisor-level CSRs with the same select value may be defined by an extension as partial or full aliases with respect to each other. |
norm:csrs_alias |
| miph_csr_number | The mireg* CSR numbers are not consecutive because miph is CSR number 0x354. | norm:miph_csr_number |
| miselect_op | The value of miselect determines which register is accessed upon read or write of each of the machine indirect alias CSRs (mireg*). |
norm:miselect_op |
| miselect_value_range | miselect value ranges are allocated to dependent extensions, which specify the register state accessible via each miregi register, for each miselect value. |
norm:miselect_value_range |
| MISELECT_WARL | extension | Rule's "kind" property |
| Smcsrind | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| miselect is a WARL register. |
norm:miselect_WARL | |
| miselect_min_sz | The miselect register implements at least enough bits to support all implemented miselect values (corresponding to the implemented extensions that utilize miselect/mireg* to indirectly access register state). |
norm:miselect_min_sz |
| miselect_msb_op | Values of miselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs. Values of miselect with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of miselect moves to the new position, retaining its value from before. | norm:miselect_msb_op |
| mireg_access_on_legal_miselect | Attempts to access mireg* while miselect holds a number in an allocated and implemented range results in a specific behavior that, for each combination of miselect and miregi, is defined by the extension to which the miselect value is allocated. | norm:mireg_access_on_legal_miselect |
| mireg_access_behaviour | Ordinarily, each `mireg`i will access register state, access read-only 0 state, or raise an illegal-instruction exception. | norm:mireg_access_behaviour |
| siselect_min_range | The siselect register will support the value range 0..0xFFF at a minimum. |
norm:siselect_min_range |
| siselect_msb_op | Values of siselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs. Values of siselect with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of siselect moves to the new position, retaining its value from before. | norm:siselect_msb_op |
| sireg_access_on_illegal_siselect | The behavior upon accessing sireg* from M-mode or S-mode, while siselect holds a value that is not implemented at supervisor level, is UNSPECIFIED. | norm:sireg_access_on_illegal_siselect |
| sireg_access_on_legal_siselect | Otherwise, attempts to access sireg* from M-mode or S-mode while siselect holds a number in a standard-defined and implemented range result in specific behavior that, for each combination of siselect and siregi, is defined by the extension to which the siselect value is allocated. | norm:sireg_access_on_legal_siselect |
| sireg_access_behaviour | Ordinarily, each `sireg`i will access register state, access read-only 0 state, or, unless executing in a virtual machine (covered in the next section), raise an illegal-instruction exception. | norm:sireg_access_behaviour |
| sscsrind_smode_csrs_sz | Note that the widths of siselect and sireg* are always the current XLEN rather than SXLEN. Hence, for example, if MXLEN = 64 and SXLEN = 32, then these registers are 64 bits when the current privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). | norm:sscsrind_smode_csrs_sz |
| vsiselect_min_range | The vsiselect register will support the value range 0..0xFFF at a minimum. |
norm:vsiselect_min_range |
| vsiselect_msb_op | Values of vsiselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs. Values of vsiselect with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of vsiselect moves to the new position, retaining its value from before. | norm:vsiselect_msb_op |
| sscsrind_virtual_inst_fault | A virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access vsiselect or vsireg*, or attempts from VU-mode to access siselect or sireg*. | norm:sscsrind_virtual_inst_fault |
| vsireg_access_on_legal_vsiselect | Otherwise, while vsiselect holds a number in a standard-defined and implemented range, attempts to access vsireg* from a sufficiently privileged mode, or to access sireg* (really vsireg*) from VS-mode, result in specific behavior that, for each combination of vsiselect and vsiregi, is defined by the extension to which the vsiselect value is allocated. | norm:vsireg_access_on_legal_vsiselect |
| vsireg_access_behaviour | Ordinarily, each vsireg`i will access register state, access read-only 0 state, or raise an exception (either an illegal-instruction exception or, for select accesses from VS-mode, a virtual-instruction exception). | norm:vsireg_access_behaviour |
| vsmode_virtual_inst_fault | When `vsiselect holds a value that is implemented at HS level but not at VS level, attempts to access sireg* (really vsireg*) from VS-mode will typically raise a virtual-instruction exception. | norm:vsmode_virtual_inst_fault |
| sscsrind_vsmode_csrs_sz | Like siselect and sireg*, the widths of vsiselect and vsireg* are always the current XLEN rather than VSXLEN. Hence, for example, if HSXLEN = 64 and VSXLEN = 32, then these registers are 64 bits when accessed by a hypervisor in HS-mode (running RV64 code) but 32 bits for a guest OS in VS-mode (RV32 code). | norm:sscsrind_vsmode_csrs_sz |
| sscsrind_csrs_access_control | If extension Smstateen is implemented together with Smcsrind, bit 60 of state-enable register mstateen0 controls access to siselect, sireg*, vsiselect, and vsireg*. When mstateen0[60]=0, an attempt to access one of these CSRs from a privilege mode less privileged than M-mode results in an illegal-instruction exception. |
norm:sscsrind_csrs_access_control |
| hypervisor_impl_csrs_access_control | If the hypervisor extension is implemented, the same bit is defined also in hypervisor CSR hstateen0, but controls access to only siselect and sireg* (really vsiselect and vsireg*), which is the state potentially accessible to a virtual machine executing in VS or VU-mode. When hstateen0[60]=0 and mstateen0[60]=1, all attempts from VS or VU-mode to access siselect or sireg* raise a virtual-instruction exception, not an illegal-instruction exception, regardless of the value of vsiselect or any other mstateen bit. | norm:hypervisor_impl_csrs_access_control |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| base_integer_variants | There are two primary base integer variants, RV32I and RV64I, described in rv32 and rv64, which provide 32-bit or 64-bit address spaces respectively. |
norm:base_integer_variants |
| xlen_definition | We use the term XLEN to refer to the width of an integer register in bits (either 32 or 64). |
norm:xlen_definition |
| twos_complement_signed_integers | The base integer instruction sets use a two's-complement representation for signed integer values. |
norm:twos_complement_signed_integers |
| EE_IMPL_FLEX | base | Rule's "kind" property |
| Any | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The implementation of a RISC-V execution environment can be pure hardware, pure software, or a combination of hardware and software. For example, opcode traps and software emulation can be used to implement functionality not provided in hardware. |
norm:ee_impl_flex |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| mul_op | MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. |
norm:mul_op |
| mulh_op | MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and rs1×unsigned rs2 multiplication. |
norm:mulh_mulhu_mulhsu_op |
| mulhu_op | MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and rs1×unsigned rs2 multiplication. |
norm:mulh_mulhu_mulhsu_op |
| mulhsu_op | MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and rs1×unsigned rs2 multiplication. |
norm:mulh_mulhu_mulhsu_op |
| div_op | DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. |
norm:div_divu_op |
| divu_op | DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero. |
norm:div_divu_op |
| divw_op | DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers, placing the 32-bit quotient in rd, sign-extended to 64 bits. |
norm:divw_divuw_op |
| divuw_op | DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers, placing the 32-bit quotient in rd, sign-extended to 64 bits. |
norm:divw_divuw_op |
| rem_op | REM and REMU provide the remainder of the corresponding division operation. |
norm:rem_remu_op |
| remu_op | REM and REMU provide the remainder of the corresponding division operation. |
norm:rem_remu_op |
| remw_op | REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations. |
norm:remw_remuw_op |
| remuw_op | REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations. |
norm:remw_remuw_op |
| div_by_zero | The quotient of division by zero has all bits set |
norm:div_by_zero |
| rem_by_zero | the remainder of division by zero equals the dividend. | norm:rem_by_zero |
| signed_div_overflow | Signed division overflow occurs only when the most-negative integer is divided by −1. The quotient of a signed division with overflow is equal to the dividend, and the remainder is zero. |
norm:signed_div_overflow |
| rem_result_sign | For REM, the sign of a nonzero result equals the sign of the dividend. |
norm:rem_result_sign |
| remw_result_sign | Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero. |
norm:remw_remuw_result_sign |
| remuw_result_sign | Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero. |
norm:remw_remuw_result_sign |
| mulw_op | MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register. |
norm:mulw_op |
| mul_misa_M_dis | An illegal instruction exception is raised when the instruction is executed and misa.M is 0. |
Rule's "description" property |
| When a standard extension is disabled by clearing its bit in misa, the instructions and CSRs defined or modified by the extension revert to their defined or reserved behaviors as if the extension is not implemented. | norm:misa_extensions_disabling |
| Rule Name | Rule Description | Origin of Description | |||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| M_highest_priv_mode | machine-mode (M-mode), which is the highest privilege mode in a RISC-V hart. |
norm:M_highest_priv_mode | |||||||||||||||||||||||||||||||
| M_access_all_lower_priv_CSRs | M-mode code can access all CSRs at lower privilege levels. | norm:M_access_all_lower_priv_CSRs | |||||||||||||||||||||||||||||||
| misa_acc | The misa CSR is a WARL read-write register | norm:misa_acc | |||||||||||||||||||||||||||||||
| MISA_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The misa CSR is a WARL read-write register | norm:misa_acc | ||||||||||||||||||||||||||||||||
| misa_always_rd | This register must be readable in any implementation | norm:misa_always_rd | |||||||||||||||||||||||||||||||
| MISA_CSR_IMPLEMENTED | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| a value of zero can be returned to indicate the misa register has not been implemented | norm:misa_csr_implemented | ||||||||||||||||||||||||||||||||
| misa_enc | (No text available) | norm:misa_enc_img | |||||||||||||||||||||||||||||||
| misa_mxl_op | The MXL (Machine XLEN) field encodes the native base integer ISA width as shown in norm:misa_mxl_enc. |
norm:misa_mxl_op_isa | |||||||||||||||||||||||||||||||
| If misa is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN. |
norm:misa_mxl_op_nz | ||||||||||||||||||||||||||||||||
| MXLEN | XLEN in M-mode | Rule's "summary" property | |||||||||||||||||||||||||||||||
| extension | Rule's "kind" property | ||||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If misa is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN. |
norm:misa_mxl_op_nz | ||||||||||||||||||||||||||||||||
| XLEN is never greater than MXLEN, but XLEN might be smaller than MXLEN in less-privileged modes. |
norm:xlen_le_mxlen | ||||||||||||||||||||||||||||||||
| misa_mxl_acc | The MXL field is read-only. | norm:misa_mxl_acc | |||||||||||||||||||||||||||||||
| misa_mxl_enc |
|
norm:misa_mxl_enc | |||||||||||||||||||||||||||||||
| misa_sz | The misa CSR is MXLEN bits wide. | norm:misa_sz | |||||||||||||||||||||||||||||||
| misa_extensions_enc | The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet (bit 0 encodes presence of extension "A" , bit 1 encodes presence of extension "B", through to bit 25 which encodes "Z"). |
norm:misa_extensions_enc_txt | |||||||||||||||||||||||||||||||
|
norm:misa_extensions_enc_tbl | ||||||||||||||||||||||||||||||||
| MISA_EXTENSIONS_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. |
norm:misa_extensions_warl_op | ||||||||||||||||||||||||||||||||
| misa_extensions_op | The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. |
norm:misa_extensions_warl_op | |||||||||||||||||||||||||||||||
| MISA_EXTENSIONS_WRITABLE_BITS | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. |
norm:misa_extensions_warl_op | ||||||||||||||||||||||||||||||||
| misa_extensions_rst | At reset, the Extensions field shall contain the maximal set of supported extensions, and "I" shall be selected over "E" if both are available. |
norm:misa_extensions_rst1 | |||||||||||||||||||||||||||||||
| The misa register is reset to enable the maximal set of supported extensions, as described in misa. |
norm:misa_extensions_rst2 | ||||||||||||||||||||||||||||||||
| misa_extensions_disabling | When a standard extension is disabled by clearing its bit in misa, the instructions and CSRs defined or modified by the extension revert to their defined or reserved behaviors as if the extension is not implemented. | norm:misa_extensions_disabling | |||||||||||||||||||||||||||||||
| misa_extensions_impl_def | For a given RISC-V execution environment, an instruction, extension, or other feature of the RISC-V ISA is ordinarily judged to be implemented or not by the observable execution behavior in that environment. For example, the F extension is said to be implemented for an execution environment if and only if the instructions that the RISC-V Unprivileged ISA defines for F execute as specified. | norm:misa_extensions_impl_def | |||||||||||||||||||||||||||||||
| misa_extensions_disabling_def | With this definition of implemented, disabling an extension by clearing its bit in misa results in the extension being considered not implemented in M-mode. For example, setting misa.F=0 results in the F extension being not implemented for M-mode, because the F extension’s instructions will not act as the Unprivileged ISA requires but may instead raise an illegal-instruction exception. | norm:misa_extensions_disabling_def | |||||||||||||||||||||||||||||||
| misa_extensions_rsv_ret_0 | All bits that are reserved for future use must return zero when read. | norm:misa_extensions_rsv_ret_0 | |||||||||||||||||||||||||||||||
| misa_i_op | The "I" bit will be set for the RV32I and RV64I base ISAs | norm:misa_i_op | |||||||||||||||||||||||||||||||
| misa_e_op | the "E" bit will be set for RV32E and RV64E. | norm:misa_e_op | |||||||||||||||||||||||||||||||
| misa_x_op | The "X" bit will be set if there are any non-standard extensions. | norm:misa_x_op | |||||||||||||||||||||||||||||||
| misa_b_op | When the "B" bit is 1, the implementation supports the instructions provided by the Zba, Zbb, and Zbs extensions. |
norm:misa_b_op | |||||||||||||||||||||||||||||||
| misa_m_op | When the "M" bit is 1, the implementation supports all multiply and division instructions defined by the M extension. |
norm:misa_m_op | |||||||||||||||||||||||||||||||
| misa_s_op | When the "S" bit is 1, the implementation supports supervisor mode. | norm:misa_s_op | |||||||||||||||||||||||||||||||
| misa_u_op | When the "U" bit is 1, the implementation supports user mode. | norm:misa_u_op | |||||||||||||||||||||||||||||||
| misa_e_not_i | Unless misa is all read-only zero, the "E" bit always reads as the complement of the "I" bit. |
norm:misa_e_not_i | |||||||||||||||||||||||||||||||
| Zmmul_misa_m | if the Zmmul extension is supported then the multiply instructions it specifies are supported irrespective of the value of the "M" bit. |
norm:Zmmul_misa_m | |||||||||||||||||||||||||||||||
| misa_e_acc | The "E" bit is read-only. | norm:misa_e_acc | |||||||||||||||||||||||||||||||
| misa_extensions_dependencies | If an ISA feature x depends on an ISA feature y, then attempting to enable feature x but disable feature y results in both features being disabled. |
norm:misa_extensions_dependencies | |||||||||||||||||||||||||||||||
| misa_inc_ialign | Writing misa may increase IALIGN, e.g., by disabling the "C" extension. If an instruction that would write misa increases IALIGN, and the subsequent instruction's address is not IALIGN-bit aligned, the write to misa is suppressed, leaving misa unchanged. |
norm:misa_inc_ialign | |||||||||||||||||||||||||||||||
| mvendorid_sz | The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | |||||||||||||||||||||||||||||||
| mvendorid_acc | The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | |||||||||||||||||||||||||||||||
| mvendorid_op | The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | |||||||||||||||||||||||||||||||
| VENDOR_ID_BANK | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | ||||||||||||||||||||||||||||||||
| VENDOR_ID_OFFSET | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | ||||||||||||||||||||||||||||||||
| mvendorid_always_rd | This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented or that this is a non-commercial implementation. |
norm:mvendorid_always_rd | |||||||||||||||||||||||||||||||
| mvendorid_enc | JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte continuation codes 0x7f, terminated by a one-byte ID not equal to 0x7f, with an odd parity bit in the most-significant bit of each byte. mvendorid encodes the number of one-byte continuation codes in the Bank field, and encodes the final byte in the Offset field, discarding the parity bit. |
norm:mvendorid_enc | |||||||||||||||||||||||||||||||
| marchid_sz | The marchid CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
norm:marchid_sz_acc_op | |||||||||||||||||||||||||||||||
| marchid_acc | The marchid CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
norm:marchid_sz_acc_op | |||||||||||||||||||||||||||||||
| marchid_op | The marchid CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
norm:marchid_sz_acc_op | |||||||||||||||||||||||||||||||
| ARCH_ID | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The marchid CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
norm:marchid_sz_acc_op | ||||||||||||||||||||||||||||||||
| marchid_always_rd | This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented. |
norm:marchid_always_rd | |||||||||||||||||||||||||||||||
| mimpid_op | The mimpid CSR provides a unique encoding of the version of the processor implementation. |
norm:mimpid_op | |||||||||||||||||||||||||||||||
| IMP_ID | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The mimpid CSR provides a unique encoding of the version of the processor implementation. |
norm:mimpid_op | ||||||||||||||||||||||||||||||||
| mimpid_always_rd | This register must be readable in any implementation, but a value of 0 can be returned to indicate that the field is not implemented. |
norm:mimpid_always_rd | |||||||||||||||||||||||||||||||
| mhartid_sz | The mhartid CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
norm:mhartid_sz_acc_op | |||||||||||||||||||||||||||||||
| mhartid_acc | The mhartid CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
norm:mhartid_sz_acc_op | |||||||||||||||||||||||||||||||
| mhartid_op | The mhartid CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
norm:mhartid_sz_acc_op | |||||||||||||||||||||||||||||||
| HART_ID | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The mhartid CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
norm:mhartid_sz_acc_op | ||||||||||||||||||||||||||||||||
| mhartid_always_rd | This register must be readable in any implementation. | norm:mhartid_always_rd | |||||||||||||||||||||||||||||||
| mhartid_one_is_zero | one hart must have a hart ID of zero. | norm:mhartid_one_is_zero | |||||||||||||||||||||||||||||||
| mhartid_unique | Hart IDs must be unique within the execution environment. | norm:mhartid_unique | |||||||||||||||||||||||||||||||
| mstatus_sz | The mstatus register is an MXLEN-bit read/write register formatted as shown in mstatusreg-rv32 for RV32 and mstatusreg for RV64. |
norm:mstatus_sz_acc | |||||||||||||||||||||||||||||||
| mstatus_acc | The mstatus register is an MXLEN-bit read/write register formatted as shown in mstatusreg-rv32 for RV32 and mstatusreg for RV64. |
norm:mstatus_sz_acc | |||||||||||||||||||||||||||||||
| mstatush_sz | For RV32 only, mstatush is a 32-bit read/write register formatted as shown in mstatushreg. | norm:mstatush_sz_acc | |||||||||||||||||||||||||||||||
| mstatush_acc | For RV32 only, mstatush is a 32-bit read/write register formatted as shown in mstatushreg. | norm:mstatush_sz_acc | |||||||||||||||||||||||||||||||
| mstatush_enc | Bits 30:4 of mstatush generally contain the same fields found in bits 62:36 of mstatus for RV64. Fields SD, SXL, and UXL do not exist in mstatush. | norm:mstatush_enc | |||||||||||||||||||||||||||||||
| mstatus_mie_op | Global interrupt-enable bits, MIE and SIE, are provided for M-mode and S-mode respectively. |
norm:mstatus_mie_sie_op1 | |||||||||||||||||||||||||||||||
| When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0. |
norm:mstatus_mie_sie_op2 | ||||||||||||||||||||||||||||||||
| mstatus_sie_op | Global interrupt-enable bits, MIE and SIE, are provided for M-mode and S-mode respectively. |
norm:mstatus_mie_sie_op1 | |||||||||||||||||||||||||||||||
| When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0. |
norm:mstatus_mie_sie_op2 | ||||||||||||||||||||||||||||||||
| mstatus_mie_rst | The mstatus fields MIE and MPRV are reset to 0. | norm:mstatus_mie_mprv_rst | |||||||||||||||||||||||||||||||
| mstatus_mprv_rst | The mstatus fields MIE and MPRV are reset to 0. | norm:mstatus_mie_mprv_rst | |||||||||||||||||||||||||||||||
| mstatus_mie_clr_by_mdt | When the MDT bit is set to 1 by an explicit CSR write, the MIE (Machine Interrupt Enable) bit is cleared to 0. |
norm:mstatus_mie_clr_by_mdt | |||||||||||||||||||||||||||||||
| mstatus_mie_clr_by_mdt_rv64 | When the MDT bit is set to 1 by an explicit CSR write, the MIE (Machine Interrupt Enable) bit is cleared to 0. |
norm:mstatus_mie_clr_by_mdt | |||||||||||||||||||||||||||||||
| For RV64, this clearing occurs regardless of the value written, if any, to the MIE bit by the same write. | norm:mstatus_mie_clr_by_mdt_rv64 | ||||||||||||||||||||||||||||||||
| mstatus_mie_set_mdt_0 | The MIE bit can only be set to 1 by an explicit CSR write if the MDT bit is already 0 |
norm:mstatus_mie_set_mdt_0 | |||||||||||||||||||||||||||||||
| mstatus_mie_set_mdt_0_rv64 | [CONTEXT] The MIE bit can only be set to 1 by an explicit CSR write if the MDT bit is already 0 |
norm:mstatus_mie_set_mdt_0 | |||||||||||||||||||||||||||||||
| or, for RV64, is being set to 0 by the same write | norm:mstatus_mie_set_mdt_0_rv64 | ||||||||||||||||||||||||||||||||
| mstatus_xie_intr_en_dis | Interrupts for lower-privilege modes, w<x, are always globally disabled regardless of the setting of any global wIE bit for the lower-privilege mode. Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode. |
norm:mstatus_xie_intr_en_dis | |||||||||||||||||||||||||||||||
| mstatus_sie_rdonly0 | If supervisor mode is not implemented, then SIE and SPIE are read-only 0. | norm:mstatus_sie_spie_rdonly0 | |||||||||||||||||||||||||||||||
| mstatus_spie_rdonly0 | If supervisor mode is not implemented, then SIE and SPIE are read-only 0. | norm:mstatus_sie_spie_rdonly0 | |||||||||||||||||||||||||||||||
| mstatus_xpie_op | each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode. |
norm:mstatus_xpie_xpp_op | |||||||||||||||||||||||||||||||
| mstatus_xpp_op | each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode. |
norm:mstatus_xpie_xpp_op | |||||||||||||||||||||||||||||||
| mstatus_xpie_trap_op | When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y. |
norm:mstatus_xpie_xie_xpp_trap_op | |||||||||||||||||||||||||||||||
| mstatus_xie_trap_op | When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y. |
norm:mstatus_xpie_xie_xpp_trap_op | |||||||||||||||||||||||||||||||
| mstatus_xpp_trap_op | When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y. |
norm:mstatus_xpie_xie_xpp_trap_op | |||||||||||||||||||||||||||||||
| mstatus_xie_xret_op | When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If y{ne}M, xRET also sets MPRV=0. |
norm:mstatus_xret_op | |||||||||||||||||||||||||||||||
| mstatus_xpie_xret_op | When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If y{ne}M, xRET also sets MPRV=0. |
norm:mstatus_xret_op | |||||||||||||||||||||||||||||||
| mstatus_xpp_xret_op | When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If y{ne}M, xRET also sets MPRV=0. |
norm:mstatus_xret_op | |||||||||||||||||||||||||||||||
| mstatus_mprv_xret_op | When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If y{ne}M, xRET also sets MPRV=0. |
norm:mstatus_xret_op | |||||||||||||||||||||||||||||||
| mstatus_xpp_enc | The xPP fields can only hold privilege modes up to x | norm:mstatus_xpp_enc | |||||||||||||||||||||||||||||||
| mstatus_mpp_sz | MPP is two bits wide | norm:mstatus_mpp_sz | |||||||||||||||||||||||||||||||
| MSTATUS_XPP_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| xPP fields are WARL fields that can hold only privilege mode x and any implemented privilege mode lower than x. | norm:mstatus_xpp_warl | ||||||||||||||||||||||||||||||||
| mstatus_xpp_rdonly0 | If privilege mode x is not implemented, then xPP must be read-only 0. | norm:mstatus_xpp_rdonly0 | |||||||||||||||||||||||||||||||
| mstatus_spp_sz | SPP is one bit wide. | norm:mstatus_spp_sz | |||||||||||||||||||||||||||||||
| mstatus_mdt_sz | The M-mode-disable-trap (MDT) bit is a WARL field introduced by the Smdbltrp extension. | norm:mstatus_mdt_sz_warl | |||||||||||||||||||||||||||||||
| MSTATUS_MDT_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The M-mode-disable-trap (MDT) bit is a WARL field introduced by the Smdbltrp extension. | norm:mstatus_mdt_sz_warl | ||||||||||||||||||||||||||||||||
| mstatus_mdt_rst | Upon reset, the MDT field is set to 1. | norm:mstatus_mdt_rst | |||||||||||||||||||||||||||||||
| mstatus_mdt_not_set_rnmi | A trap caused by an RNMI does not set the MDT bit. | norm:mstatus_mdt_not_set_rnmi | |||||||||||||||||||||||||||||||
| mstatus_mdt_clr_mret_sret | The MRET and SRET instructions, when executed in M-mode, set the MDT bit to 0. | norm:mstatus_mdt_clr_mret_sret | |||||||||||||||||||||||||||||||
| MSTATUS_MDT_CLR_MNRET | The MNRET instruction, provided by the Smrnmi extension, sets the MDT bit to 0 if the new privilege mode is not M. | norm:mstatus_mdt_clr_mnret | |||||||||||||||||||||||||||||||
| MSTATUS_SXL_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | ||||||||||||||||||||||||||||||||
| MSTATUS_UXL_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | ||||||||||||||||||||||||||||||||
| mstatus_sxl_op | For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | |||||||||||||||||||||||||||||||
| mstatus_uxl_op | For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | |||||||||||||||||||||||||||||||
| mstatus_sxl_enc | For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | |||||||||||||||||||||||||||||||
| The encoding of these fields is the same as the MXL field of misa, shown in norm:misa_mxl_enc. | norm:mstatus_sxl_uxl_enc | ||||||||||||||||||||||||||||||||
| mstatus_uxl_enc | For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | |||||||||||||||||||||||||||||||
| The encoding of these fields is the same as the MXL field of misa, shown in norm:misa_mxl_enc. | norm:mstatus_sxl_uxl_enc | ||||||||||||||||||||||||||||||||
| mstatus_sxl_exist_mxlen32 | When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | |||||||||||||||||||||||||||||||
| mstatus_uxl_exist_mxlen32 | When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | |||||||||||||||||||||||||||||||
| mstatus_sxl_acc_mxlen64 | When MXLEN=64, if S-mode is not supported, then SXL is read-only zero. Otherwise, it is a WARL field that encodes the current value of SXLEN. |
norm:mstatus_sxl_acc_mxlen64 | |||||||||||||||||||||||||||||||
| MSTATUS_SXL_RDONLY_MXLEN64 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| an implementation may make SXL be a read-only field whose value always ensures that SXLEN=MXLEN. |
norm:mstatus_sxl_rdonly_mxlen64 | ||||||||||||||||||||||||||||||||
| mstatus_uxl_acc_mxlen64 | When MXLEN=64, if U-mode is not supported, then UXL is read-only zero. Otherwise, it is a WARL field that encodes the current value of UXLEN. |
norm:mstatus_uxl_acc_mxlen64 | |||||||||||||||||||||||||||||||
| mstatus_uxl_rdonly_mxlen64 | an implementation may make UXL be a read-only field whose value always ensures that UXLEN=MXLEN or UXLEN=SXLEN. |
norm:mstatus_uxl_rdonly_mxlen64 | |||||||||||||||||||||||||||||||
| MSTATUS_UXL_LEGAL_VALS_SMODE | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| If S-mode is implemented, the set of legal values that the UXL field may assume excludes those that would cause UXLEN to be greater than SXLEN. | norm:mstatus_uxl_legal_vals_smode | ||||||||||||||||||||||||||||||||
| mstatus_mprv_ldst_op | When MPRV=0, explicit memory accesses behave as normal, using the translation and protection mechanisms of the current privilege mode. When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP. |
norm:mstatus_mprv_ldst_op | |||||||||||||||||||||||||||||||
| mstatus_mprv_inst_xlat_op | Instruction address-translation and protection are unaffected by the setting of MPRV. |
norm:mstatus_mprv_inst_xlat_op | |||||||||||||||||||||||||||||||
| mstatus_mprv_rdonly0_no_umode | MPRV is read-only 0 if U-mode is not supported. | norm:mstatus_mprv_rdonly0_no_umode | |||||||||||||||||||||||||||||||
| mstatus_mprv_clr_mret_sret_less_priv | An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0. |
norm:mstatus_mprv_clr_mret_sret_less_priv | |||||||||||||||||||||||||||||||
| mstatus_mxr_op | When MXR=0, only loads from pages marked readable (R=1 in sv32pte) will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. |
norm:mstatus_mxr_op | |||||||||||||||||||||||||||||||
| mstatus_mxr_rdonly0_no_smode | MXR is read-only 0 if S-mode is not supported. | norm:mstatus_mxr_rdonly0_no_smode | |||||||||||||||||||||||||||||||
| mstatus_sum_op | When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in sv32pte) will fault. When SUM=1, these accesses are permitted. |
norm:mstatus_sum_op | |||||||||||||||||||||||||||||||
| mstatus_sum_op_no-vm | SUM has no effect when page-based virtual memory is not in effect. | norm:mstatus_sum_op_no-vm | |||||||||||||||||||||||||||||||
| mstatus_sum_op_mprv_mpp | while SUM is ordinarily ignored when not executing in S-mode, it is in effect when MPRV=1 and MPP=S. |
norm:mstatus_sum_op_mprv_mpp | |||||||||||||||||||||||||||||||
| mstatus_sum_rdonly0 | SUM is read-only 0 if S-mode is not supported or if satp.MODE is read-only 0. | norm:mstatus_sum_rdonly0 | |||||||||||||||||||||||||||||||
| MSTATUS_MXR_SUM_OP_ACC_FAULT | The MXR and SUM mechanisms only affect the interpretation of permissions encoded in page-table entries. In particular, they have no impact on whether access-fault exceptions are raised due to PMAs or PMP. | norm:mstatus_mxr_sum_op_acc_fault | |||||||||||||||||||||||||||||||
| MSTATUS_MBE_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||||||||||||||||||||||||
| MSTATUS_SBE_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||||||||||||||||||||||||
| MSTATUS_UBE_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||||||||||||||||||||||||
| MSTATUSH_MBE_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||||||||||||||||||||||||
| MSTATUSH_SBE_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||||||||||||||||||||||||
| MSTATUSH_UBE_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||||||||||||||||||||||||
| mstatus_mbe_op | MBE controls whether non-instruction-fetch memory accesses made from M-mode (assuming mstatus.MPRV=0) are little-endian (MBE=0) or big-endian (MBE=1). | norm:mstatus_mbe_op | |||||||||||||||||||||||||||||||
| mstatus_mbe_rst | If little-endian memory accesses are supported, the mstatus/mstatush field MBE is reset to 0. | norm:mstatus_mstatush_mbe_rst | |||||||||||||||||||||||||||||||
| mstatush_mbe_rst | If little-endian memory accesses are supported, the mstatus/mstatush field MBE is reset to 0. | norm:mstatus_mstatush_mbe_rst | |||||||||||||||||||||||||||||||
| mstatus_sbe_op | If S-mode is not supported, SBE is read-only 0. Otherwise, SBE controls whether explicit load and store memory accesses made from S-mode are little-endian (SBE=0) or big-endian (SBE=1). | norm:mstatus_sbe_op | |||||||||||||||||||||||||||||||
| mstatus_sbe_implicit | For implicit accesses to supervisor-level memory management data structures, such as page tables, endianness is always controlled by SBE. |
norm:mstatus_sbe_implicit | |||||||||||||||||||||||||||||||
| mstatus_sbe_change_fence | For implicit accesses to supervisor-level memory management data structures, such as page tables, endianness is always controlled by SBE. |
norm:mstatus_sbe_implicit | |||||||||||||||||||||||||||||||
| Since changing SBE alters the implementation’s interpretation of these data structures, if any such data structures remain in use across a change to SBE, M-mode software must follow such a change to SBE by executing an SFENCE.VMA instruction with rs1=x0 and rs2=x0. |
norm:mstatus_sbe_change_fence | ||||||||||||||||||||||||||||||||
| MSTATUS_SBE_ROCOPY | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If S-mode is supported, an implementation may make SBE be a read-only copy of MBE. |
norm:mstatus_sbe_rocopy | ||||||||||||||||||||||||||||||||
| mstatus_ube_op | If U-mode is not supported, UBE is read-only 0. Otherwise, UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1). | norm:mstatus_ube_op | |||||||||||||||||||||||||||||||
| MSTATUS_UBE_ROCOPY | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If U-mode is supported, an implementation may make UBE be a read-only copy of either MBE or SBE. |
norm:mstatus_ube_rocopy | ||||||||||||||||||||||||||||||||
| MSTATUS_TVM_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported. | norm:mstatus_tvm_warl_op | ||||||||||||||||||||||||||||||||
| mstatus_tvm_op | The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported. | norm:mstatus_tvm_warl_op | |||||||||||||||||||||||||||||||
| MSTATUS_TW_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The TW (Timeout Wait) bit is a WARL field that supports intercepting the WFI instruction (see wfi). |
norm:mstatus_tw_warl | ||||||||||||||||||||||||||||||||
| mstatus_tw_op | When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception. |
norm:mstatus_tw_op | |||||||||||||||||||||||||||||||
| mstatus_tw_umode_op | When S-mode is implemented, then executing WFI in U-mode causes an illegal-instruction exception, regardless of the value of the TW bit, unless the instruction completes within an implementation-specific, bounded time limit. |
norm:mstatus_tw_umode_op | |||||||||||||||||||||||||||||||
| mstatus_tw_acc | TW is read-only 0 when there are no modes less privileged than M. | norm:mstatus_tw_acc | |||||||||||||||||||||||||||||||
| MSTATUS_TW_TIME_LIMIT | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception. |
norm:mstatus_tw_op | ||||||||||||||||||||||||||||||||
| MSTATUS_TW_ALWAYS_ILLEGAL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| An implementation may have WFI always raise an illegal-instruction exception in modes less privileged than M when TW=1, even if there are pending globally-disabled interrupts when the instruction is executed. |
norm:mstatus_tw_always_illegal | ||||||||||||||||||||||||||||||||
| MSTATUS_TSR_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The TSR (Trap SRET) bit is a WARL field that supports intercepting the supervisor exception return instruction, SRET. |
norm:mstatus_tsr_warl | ||||||||||||||||||||||||||||||||
| mstatus_tsr_op | When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal-instruction exception. When TSR=0, this operation is permitted in S-mode. |
norm:mstatus_tsr_op | |||||||||||||||||||||||||||||||
| MSTATUS_TSR_ACC | TSR is read-only 0 when S-mode is not supported. | norm:mstatus_tsr_acc | |||||||||||||||||||||||||||||||
| MSTATUS_FS_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The FS[1:0] and VS[1:0] WARL fields | norm:mstatus_fs_vs_warl | ||||||||||||||||||||||||||||||||
| MSTATUS_VS_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The FS[1:0] and VS[1:0] WARL fields | norm:mstatus_fs_vs_warl | ||||||||||||||||||||||||||||||||
| mstatus_fs_op | The FS field encodes the status of the floating-point unit state, including the floating-point registers f0–f31 and the CSRs fcsr, frm, and fflags. |
norm:mstatus_fs_op | |||||||||||||||||||||||||||||||
| mstatus_vs_op | The VS field encodes the status of the vector extension state, including the vector registers v0–v31 and the CSRs vcsr, vxrm, vxsat, vstart, vl, vtype, and vlenb. |
norm:mstatus_vs_op | |||||||||||||||||||||||||||||||
| A vector context status field, VS, is added to mstatus[10:9] and shadowed in sstatus[10:9]. It is defined analogously to the floating-point context status field, FS. | norm:mstatus_vs_sstatus_vs_op | ||||||||||||||||||||||||||||||||
| mstatus_xs_op | The XS field encodes the status of additional user-mode extensions and associated state. |
norm:mstatus_xs_op1 | |||||||||||||||||||||||||||||||
| The XS field represents a summary of all extensions' status as shown in norm:mstatus_fs_vs_xs_enc. |
norm:mstatus_xs_op2 | ||||||||||||||||||||||||||||||||
| mstatus_fs_enc |
|
norm:mstatus_fs_vs_xs_enc | |||||||||||||||||||||||||||||||
| mstatus_vs_enc |
|
norm:mstatus_fs_vs_xs_enc | |||||||||||||||||||||||||||||||
| mstatus_xs_enc |
|
norm:mstatus_fs_vs_xs_enc | |||||||||||||||||||||||||||||||
| mstatus_fs_acc | If the F extension is implemented, the FS field shall not be read-only zero. | norm:mstatus_fs_acc1 | |||||||||||||||||||||||||||||||
| If neither the F extension nor S-mode is implemented, then FS is read-only zero. | norm:mstatus_fs_acc2 | ||||||||||||||||||||||||||||||||
| MSTATUS_FS_RDONLY0_S_NO_F | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If S-mode is implemented but the F extension is not, FS may optionally be read-only zero. |
norm:mstatus_fs_rdonly0_s_no_f | ||||||||||||||||||||||||||||||||
| mstatus_vs_acc | If the v registers are implemented, the VS field shall not be read-only zero. | norm:mstatus_vs_acc1 | |||||||||||||||||||||||||||||||
| If neither the v registers nor S-mode is implemented, then VS is read-only zero. |
norm:mstatus_vs_acc2 | ||||||||||||||||||||||||||||||||
| MSTATUS_VS_RDONLY0_S_NO_V | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If S-mode is implemented but the v registers are not, VS may optionally be read-only zero. |
norm:mstatus_vs_rdonly0_s_no_v | ||||||||||||||||||||||||||||||||
| mstatus_xs_acc | In harts without additional user extensions requiring new state, the XS field is read-only zero. |
norm:mstatus_xs_acc | |||||||||||||||||||||||||||||||
| mstatus_xs_equiv | Every additional extension with state provides a CSR field that encodes the equivalent of the XS states. |
norm:mstatus_xs_equiv | |||||||||||||||||||||||||||||||
| mstatus_sd_acc | The SD bit is a read-only bit | norm:mstatus_sd_acc | |||||||||||||||||||||||||||||||
| mstatus_sd_op | summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory. |
norm:mstatus_sd_op1 | |||||||||||||||||||||||||||||||
| If mstatus.VS is Dirty, mstatus.SD is 1; otherwise, mstatus.SD is set in accordance with existing specifications. | norm:mstatus_sd_op2 | ||||||||||||||||||||||||||||||||
| mstatus_sd_rdonly0 | If FS, XS, and VS are all read-only zero, then SD is also always zero. | norm:mstatus_sd_rdonly0 | |||||||||||||||||||||||||||||||
| mstatus_fs_vs_xs_off_op | When an extension's status is set to Off, any instruction that attempts to read or write the corresponding state will cause an illegal-instruction exception. |
norm:mstatus_fs_vs_xs_off_op | |||||||||||||||||||||||||||||||
| mstatus_fs_vs_xs_initial_op | When the status is Initial, the corresponding state should have an initial constant value. |
norm:mstatus_fs_vs_xs_initial_op | |||||||||||||||||||||||||||||||
| mstatus_fs_vs_xs_clean_op | When the status is Clean, the corresponding state is potentially different from the initial value, but matches the last value stored on a context swap. |
norm:mstatus_fs_vs_xs_clean_op | |||||||||||||||||||||||||||||||
| mstatus_fs_vs_xs_dirty_op | When the status is Dirty, the corresponding state has potentially been modified since the last context save. |
norm:mstatus_fs_vs_xs_dirty_op | |||||||||||||||||||||||||||||||
| mstatus_fs_vs_xs_update_indep_priv | The status fields will also be updated during execution of instructions, regardless of privilege mode. |
norm:mstatus_fs_vs_xs_update_indep_priv | |||||||||||||||||||||||||||||||
| mstatus_fs_wr | Changing the setting of FS has no effect on the contents of the floating-point register state. In particular, setting FS=Off does not destroy the state, nor does setting FS=Initial clear the contents. |
norm:mstatus_fs_wr | |||||||||||||||||||||||||||||||
| mstatus_vs_wr | the setting of VS has no effect on the contents of the vector register state. |
norm:mstatus_vs_wr | |||||||||||||||||||||||||||||||
| MSTATUS_FS_IMPRECISE | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified. On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty. |
norm:mstatus_fs_imprecise | ||||||||||||||||||||||||||||||||
| MSTATUS_FS_NO_DIRTY_TRACK | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| dirtiness might not be tracked at all, in which case the valid FS states are Off and Dirty, and an attempt to set FS to Initial or Clean causes it to be set to Dirty. |
norm:mstatus_fs_no_dirty_track | ||||||||||||||||||||||||||||||||
| MSTATUS_FS_NO_CHANGE_DIRTY | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If an instruction explicitly or implicitly writes a floating-point register or the fcsr but does not alter its contents, and FS=Initial or FS=Clean, it is implementation-defined whether FS transitions to Dirty. |
norm:mstatus_fs_no_change_dirty | ||||||||||||||||||||||||||||||||
| MSTATUS_VS_IMPRECISE | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| [CONTEXT] Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified. On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty. |
norm:mstatus_fs_imprecise | ||||||||||||||||||||||||||||||||
| Implementations may choose to track the dirtiness of the vector register state in an analogous imprecise fashion, including possibly setting VS to Dirty when software attempts to set VS=Initial or VS=Clean. |
norm:mstatus_vs_imprecise | ||||||||||||||||||||||||||||||||
| MSTATUS_VS_NO_CHANGE_DIRTY | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| When VS=Initial or VS=Clean, it is implementation-defined whether an instruction that writes a vector register or vector CSR but does not alter its contents causes VS to transition to Dirty. |
norm:mstatus_vs_no_change_dirty | ||||||||||||||||||||||||||||||||
| mstatus_spelp_op | The Zicfilp extension adds the SPELP and MPELP fields that hold the previous ELP, and are updated as specified in ZICFILP_FORWARD_TRAPS. |
norm:mstatus_spelp_mpelp_op | |||||||||||||||||||||||||||||||
| To store the previous ELP state on trap delivery to S/HS-mode, an SPELP bit is provided in the mstatus CSR. |
norm:cfi_mstatus_spelp_op | ||||||||||||||||||||||||||||||||
| mstatus_mpelp_op | The Zicfilp extension adds the SPELP and MPELP fields that hold the previous ELP, and are updated as specified in ZICFILP_FORWARD_TRAPS. |
norm:mstatus_spelp_mpelp_op | |||||||||||||||||||||||||||||||
| To store the previous ELP state on trap delivery to M-mode, an MPELP bit is provided in the mstatus CSR. |
norm:cfi_mstatus_mpelp_op | ||||||||||||||||||||||||||||||||
| mstatus_spelp_enc | The x`PELP` fields are encoded as follows: | norm:mstatus_spelp_mpelp_enc_lead-in | |||||||||||||||||||||||||||||||
| 0 - NO_LP_EXPECTED - no landing pad instruction expected. 1 - LP_EXPECTED - a landing pad instruction is expected. |
norm:mstatus_spelp_mpelp_enc_list | ||||||||||||||||||||||||||||||||
| mstatus_mpelp_enc | The x`PELP` fields are encoded as follows: | norm:mstatus_spelp_mpelp_enc_lead-in | |||||||||||||||||||||||||||||||
| 0 - NO_LP_EXPECTED - no landing pad instruction expected. 1 - LP_EXPECTED - a landing pad instruction is expected. |
norm:mstatus_spelp_mpelp_enc_list | ||||||||||||||||||||||||||||||||
| sstatus_sdt_clr_mret_sret | The MRET and SRET instructions, when executed in M-mode, set the MDT bit to 0. | norm:mstatus_mdt_clr_mret_sret | |||||||||||||||||||||||||||||||
| If the new privilege mode is U, VS, or VU, then sstatus.SDT is also set to 0. | norm:sstatus_sdt_clr_mret_sret | ||||||||||||||||||||||||||||||||
| sstatus_sdt_clr_mnret | The MNRET instruction, provided by the Smrnmi extension, sets the MDT bit to 0 if the new privilege mode is not M. | norm:mstatus_mdt_clr_mnret | |||||||||||||||||||||||||||||||
| If it is U, VS, or VU, then sstatus.SDT is also set to 0. | norm:sstatus_sdt_clr_mnret | ||||||||||||||||||||||||||||||||
| vsstatus_sdt_clr_mret_sret | The MRET and SRET instructions, when executed in M-mode, set the MDT bit to 0. | norm:mstatus_mdt_clr_mret_sret | |||||||||||||||||||||||||||||||
| Additionally, if it is VU, then vsstatus.SDT is also set to 0. | norm:vsstatus_sdt_clr_mret_sret | ||||||||||||||||||||||||||||||||
| vsstatus_sdt_clr_mnret | The MNRET instruction, provided by the Smrnmi extension, sets the MDT bit to 0 if the new privilege mode is not M. | norm:mstatus_mdt_clr_mnret | |||||||||||||||||||||||||||||||
| Additionally, if it is VU, then vsstatus.SDT is also set to 0. | norm:vsstatus_sdt_clr_mnret | ||||||||||||||||||||||||||||||||
| mtvec_enc | (No text available) | norm:mtvec_enc | |||||||||||||||||||||||||||||||
| mtvec_sz | The mtvec register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). |
norm:mtvec_sz_warl_acc | |||||||||||||||||||||||||||||||
| mtvec_acc | The mtvec register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). |
norm:mtvec_sz_warl_acc | |||||||||||||||||||||||||||||||
| MTVEC_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The mtvec register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). |
norm:mtvec_sz_warl_acc | ||||||||||||||||||||||||||||||||
| mtvec_mandatory | The mtvec register must always be implemented | norm:mtvec_mandatory | |||||||||||||||||||||||||||||||
| MTVEC_RDONLY | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| [CONTEXT] The mtvec register must always be implemented | norm:mtvec_mandatory | ||||||||||||||||||||||||||||||||
| can contain a read-only value. | norm:mtvec_rdonly | ||||||||||||||||||||||||||||||||
| mtvec_base_align_4B | The value in the BASE field must always be aligned on a 4-byte boundary |
norm:mtvec_base_align_4B | |||||||||||||||||||||||||||||||
| MTVEC_BASE_ALIGN_FUNC_MODE | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| the MODE setting may impose additional alignment constraints on the value in the BASE field. |
norm:mtvec_base_align_func_mode | ||||||||||||||||||||||||||||||||
| mtvec_mode_enc |
|
norm:mtvec_mode_enc | |||||||||||||||||||||||||||||||
| mtvec_mode_direct_op | When MODE=Direct, all traps into machine mode cause the pc to be set to the address in the BASE field. |
norm:mtvec_mode_direct_op | |||||||||||||||||||||||||||||||
| mtvec_mode_vectored_op | When MODE=Vectored, all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number. |
norm:mtvec_mode_vectored_op | |||||||||||||||||||||||||||||||
| MEDELEG_OP | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| implementations can provide individual read/write bits within medeleg and mideleg to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. |
norm:medeleg_mideleg_op1 | ||||||||||||||||||||||||||||||||
| setting a bit in medeleg or mideleg will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler. |
norm:medeleg_mideleg_op2 | ||||||||||||||||||||||||||||||||
| MIDELEG_OP | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| implementations can provide individual read/write bits within medeleg and mideleg to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. |
norm:medeleg_mideleg_op1 | ||||||||||||||||||||||||||||||||
| setting a bit in medeleg or mideleg will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler. |
norm:medeleg_mideleg_op2 | ||||||||||||||||||||||||||||||||
| medeleg_enc | (No text available) | norm:medeleg_enc_img | |||||||||||||||||||||||||||||||
| medeleg has a bit position allocated for every synchronous exception shown in norm:mcause_exccode_enc_img, with the index of the bit position equal to the value returned in the mcause register |
norm:medeleg_enc_txt | ||||||||||||||||||||||||||||||||
| mideleg_enc | (No text available) | norm:mideleg_enc_img | |||||||||||||||||||||||||||||||
| mideleg holds trap delegation bits for individual interrupts, with the layout of bits matching those in the mip register |
norm:mideleg_enc_txt | ||||||||||||||||||||||||||||||||
| medelegh_sz_xlen32 | When XLEN=32, medelegh is a 32-bit read/write register that aliases bits 63:32 of medeleg. |
norm:medelegh_sz_acc_enc_xlen32 | |||||||||||||||||||||||||||||||
| medelegh_acc_xlen32 | When XLEN=32, medelegh is a 32-bit read/write register that aliases bits 63:32 of medeleg. |
norm:medelegh_sz_acc_enc_xlen32 | |||||||||||||||||||||||||||||||
| medelegh_enc_xlen32 | When XLEN=32, medelegh is a 32-bit read/write register that aliases bits 63:32 of medeleg. |
norm:medelegh_sz_acc_enc_xlen32 | |||||||||||||||||||||||||||||||
| MEDELEGH_OMIT_XLEN64 | The medelegh register does not exist when XLEN=64. | norm:medelegh_omit_xlen64 | |||||||||||||||||||||||||||||||
| medeleg_sz | The machine exception delegation register (medeleg) is a 64-bit read/write register. | norm:medeleg_sz_acc | |||||||||||||||||||||||||||||||
| medeleg_acc | The machine exception delegation register (medeleg) is a 64-bit read/write register. | norm:medeleg_sz_acc | |||||||||||||||||||||||||||||||
| mideleg_sz | The machine interrupt delegation (mideleg) register is an MXLEN-bit read/write register. |
norm:mideleg_sz_acc | |||||||||||||||||||||||||||||||
| mideleg_acc | The machine interrupt delegation (mideleg) register is an MXLEN-bit read/write register. |
norm:mideleg_sz_acc | |||||||||||||||||||||||||||||||
| medeleg_mandatory_S_mode | In harts with S-mode, the medeleg and mideleg registers must exist |
norm:medeleg_mideleg_mandatory_S_mode | |||||||||||||||||||||||||||||||
| mideleg_mandatory_S_mode | In harts with S-mode, the medeleg and mideleg registers must exist |
norm:medeleg_mideleg_mandatory_S_mode | |||||||||||||||||||||||||||||||
| medeleg_omit_wo_S_mode | In harts without S-mode, the medeleg and mideleg registers should not exist. | norm:medeleg_mideleg_omit_wo_S_mode | |||||||||||||||||||||||||||||||
| mideleg_omit_wo_S_mode | In harts without S-mode, the medeleg and mideleg registers should not exist. | norm:medeleg_mideleg_omit_wo_S_mode | |||||||||||||||||||||||||||||||
| MEDELEG_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in medeleg or mideleg to see which bit positions hold a one. |
norm:medeleg_mideleg_warl | ||||||||||||||||||||||||||||||||
| MIDELEG_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in medeleg or mideleg to see which bit positions hold a one. |
norm:medeleg_mideleg_warl | ||||||||||||||||||||||||||||||||
| medeleg_no_rd1 | An implementation shall not have any bits of medeleg be read-only one | norm:medeleg_no_rd1 | |||||||||||||||||||||||||||||||
| mideleg_no_rd1 | an implementation shall not fix as read-only one any bits of mideleg corresponding to machine-level interrupts |
norm:mideleg_no_rd1 | |||||||||||||||||||||||||||||||
| MIDELEG_RD1_LOWER_LEVEL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| may do so for lower-level interrupts | norm:mideleg_rd1_lower_level | ||||||||||||||||||||||||||||||||
| medeleg_when_rd0 | For exceptions that cannot occur in less privileged modes, the corresponding medeleg bits should be read-only zero. In particular, medeleg[11] is read-only zero. |
norm:medeleg_when_rd0 | |||||||||||||||||||||||||||||||
| medeleg_16_no_rd0 | The medeleg[16] is read-only zero as double trap is not delegatable. | norm:medeleg_16_no_rd0 | |||||||||||||||||||||||||||||||
| mip_sz | The mip register is an MXLEN-bit read/write register containing information on pending interrupts |
norm:mip_sz_acc | |||||||||||||||||||||||||||||||
| mip_acc | The mip register is an MXLEN-bit read/write register containing information on pending interrupts |
norm:mip_sz_acc | |||||||||||||||||||||||||||||||
| mie_sz | mie is the corresponding MXLEN-bit read/write register containing interrupt enable bits. |
norm:mie_sz_acc | |||||||||||||||||||||||||||||||
| mie_acc | mie is the corresponding MXLEN-bit read/write register containing interrupt enable bits. |
norm:mie_sz_acc | |||||||||||||||||||||||||||||||
| mip_enc | Interrupt cause number i (as reported in CSR mcause, mcause) corresponds with bit i in both mip and mie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. |
norm:mip_mie_enc_txt | |||||||||||||||||||||||||||||||
| (No text available) | norm:mip_enc_img | ||||||||||||||||||||||||||||||||
| mie_enc | Interrupt cause number i (as reported in CSR mcause, mcause) corresponds with bit i in both mip and mie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. |
norm:mip_mie_enc_txt | |||||||||||||||||||||||||||||||
| (No text available) | norm:mie_enc_img | ||||||||||||||||||||||||||||||||
| mip_std_enc | The standard portions (bits 15:0) of the mip and mie registers are formatted as shown in norm:mip_std_enc_img and norm:mie_std_enc_img respectively. |
norm:mip_mie_std_enc_txt | |||||||||||||||||||||||||||||||
| (No text available) | norm:mip_std_enc_img | ||||||||||||||||||||||||||||||||
| mie_std_enc | The standard portions (bits 15:0) of the mip and mie registers are formatted as shown in norm:mip_std_enc_img and norm:mie_std_enc_img respectively. |
norm:mip_mie_std_enc_txt | |||||||||||||||||||||||||||||||
| (No text available) | norm:mie_std_enc_img | ||||||||||||||||||||||||||||||||
| MIP_BITS_WR_OR_RDONLY | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Each individual bit in register mip may be writable or may be read-only. | norm:mip_bits_wr_or_rdonly | ||||||||||||||||||||||||||||||||
| mip_bits_wr_op | When bit i in mip is writable, a pending interrupt i can be cleared by writing 0 to this bit. |
norm:mip_bits_wr_op | |||||||||||||||||||||||||||||||
| mip_bits_rdonly_op | If interrupt i can become pending but bit i in mip is read-only, the implementation must provide some other mechanism for clearing the pending interrupt. |
norm:mip_bits_rdonly_op | |||||||||||||||||||||||||||||||
| mie_bits_wr | A bit in mie must be writable if the corresponding interrupt can ever become pending. | norm:mie_bits_wr | |||||||||||||||||||||||||||||||
| mie_bits_rdonly0 | Bits of mie that are not writable must be read-only zero. | norm:mie_bits_rdonly0 | |||||||||||||||||||||||||||||||
| mip_meip_op | Bits mip.MEIP and mie.MEIE are the interrupt-pending and interrupt-enable bits for machine-level external interrupts. |
norm:mip_meip_mie_meie_op | |||||||||||||||||||||||||||||||
| mie_meie_op | Bits mip.MEIP and mie.MEIE are the interrupt-pending and interrupt-enable bits for machine-level external interrupts. |
norm:mip_meip_mie_meie_op | |||||||||||||||||||||||||||||||
| mip_meip_rdonly | MEIP is read-only in mip, and is set and cleared by a platform-specific interrupt controller. |
norm:mip_meip_rdonly | |||||||||||||||||||||||||||||||
| mip_mtip_op | Bits mip.MTIP and mie.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. |
norm:mip_mtip_mie_mtie_op | |||||||||||||||||||||||||||||||
| mie_mtie_op | Bits mip.MTIP and mie.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. |
norm:mip_mtip_mie_mtie_op | |||||||||||||||||||||||||||||||
| mip_mtip_rdonly | MTIP is read-only in the mip register, and is cleared by writing to the memory-mapped machine-mode timer compare register. |
norm:mip_mtip_rdonly | |||||||||||||||||||||||||||||||
| mip_msip_op | Bits mip.MSIP and mie.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. |
norm:mip_msip_mie_msie_op | |||||||||||||||||||||||||||||||
| mie_msie_op | Bits mip.MSIP and mie.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. |
norm:mip_msip_mie_msie_op | |||||||||||||||||||||||||||||||
| mip_msip_rdonly | MSIP is read-only in mip, and is written by accesses to memory-mapped control registers, which are used to provide machine-level interprocessor interrupts. |
norm:mip_msip_rdonly | |||||||||||||||||||||||||||||||
| MIP_MSIP_MAYBE_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then mip.MSIP and mie.MSIE may both be read-only zeros. |
norm:mip_msip_mie_msie_maybe_rdonly0 | ||||||||||||||||||||||||||||||||
| MIE_MSIE_MAYBE_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then mip.MSIP and mie.MSIE may both be read-only zeros. |
norm:mip_msip_mie_msie_maybe_rdonly0 | ||||||||||||||||||||||||||||||||
| mip_seip_rdonly0 | If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie are read-only zeros. |
norm:mip_sxip_mie_sxie_rdonly0 | |||||||||||||||||||||||||||||||
| mip_stip_rdonly0 | If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie are read-only zeros. |
norm:mip_sxip_mie_sxie_rdonly0 | |||||||||||||||||||||||||||||||
| mip_ssip_rdonly0 | If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie are read-only zeros. |
norm:mip_sxip_mie_sxie_rdonly0 | |||||||||||||||||||||||||||||||
| mie_seie_rdonly0 | If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie are read-only zeros. |
norm:mip_sxip_mie_sxie_rdonly0 | |||||||||||||||||||||||||||||||
| mie_stie_rdonly0 | If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie are read-only zeros. |
norm:mip_sxip_mie_sxie_rdonly0 | |||||||||||||||||||||||||||||||
| mie_ssie_rdonly0 | If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie are read-only zeros. |
norm:mip_sxip_mie_sxie_rdonly0 | |||||||||||||||||||||||||||||||
| mip_seip_op | If supervisor mode is implemented, bits mip.SEIP and mie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. |
norm:mip_seip_mie_seie_op | |||||||||||||||||||||||||||||||
| mie_seie_op | If supervisor mode is implemented, bits mip.SEIP and mie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. |
norm:mip_seip_mie_seie_op | |||||||||||||||||||||||||||||||
| mip_seip_acc | SEIP is writable in mip | norm:mip_seip_acc | |||||||||||||||||||||||||||||||
| mip_seip_rdcsr | When mip is read with a CSR instruction, the value of the SEIP bit returned in the rd destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller |
norm:mip_seip_rdcsr | |||||||||||||||||||||||||||||||
| mip_seip_wrcsr | the signal from the interrupt controller is not used to calculate the value written to SEIP. Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction. |
norm:mip_seip_wrcsr | |||||||||||||||||||||||||||||||
| mip_stip_no_stimecmp_acc | If the stimecmp register is not implemented, STIP is writable in mip |
norm:mip_stip_no_stimecmp_acc | |||||||||||||||||||||||||||||||
| mip_stip_no_stimecmp_op | If supervisor mode is implemented, its mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. |
norm:mip_stip_mie_stie_op | |||||||||||||||||||||||||||||||
| [CONTEXT] If the stimecmp register is not implemented, STIP is writable in mip |
norm:mip_stip_no_stimecmp_acc | ||||||||||||||||||||||||||||||||
| may be written by M-mode software to deliver timer interrupts to S-mode. |
norm:mip_stip_no_stimecmp_op2 | ||||||||||||||||||||||||||||||||
| mip_stip_stimecmp_acc | If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip |
norm:mip_stip_stimecmp_acc | |||||||||||||||||||||||||||||||
| mip_stip_stimecmp_op | If supervisor mode is implemented, its mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. |
norm:mip_stip_mie_stie_op | |||||||||||||||||||||||||||||||
| [CONTEXT] If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip |
norm:mip_stip_stimecmp_acc | ||||||||||||||||||||||||||||||||
| reflects the supervisor-level timer interrupt signal resulting from stimecmp. |
norm:mip_stip_stimecmp_op2 | ||||||||||||||||||||||||||||||||
| mip_stip_stimecmp_clr | This timer interrupt signal is cleared by writing stimecmp with a value greater than the current time value. |
norm:mip_stip_stimecmp_clr | |||||||||||||||||||||||||||||||
| mip_stie_op | If supervisor mode is implemented, its mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. |
norm:mip_stip_mie_stie_op | |||||||||||||||||||||||||||||||
| mip_ssip_acc | SSIP is writable in mip | norm:mip_ssip_acc | |||||||||||||||||||||||||||||||
| mip_ssip_op | If supervisor mode is implemented, bits mip.SSIP and mie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. |
norm:mip_ssip_mie_ssie_op | |||||||||||||||||||||||||||||||
| mie_ssie_op | If supervisor mode is implemented, bits mip.SSIP and mie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. |
norm:mip_ssip_mie_ssie_op | |||||||||||||||||||||||||||||||
| mip_ssip_intr_ctrl | [CONTEXT] SSIP is writable in mip | norm:mip_ssip_acc | |||||||||||||||||||||||||||||||
| may also be set to 1 by a platform-specific interrupt controller. |
norm:mip_ssip_intr_ctrl | ||||||||||||||||||||||||||||||||
| mip_lcofip_op | If the Sscofpmf extension is implemented, bits mip.LCOFIP and mie.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. |
norm:mip_lcofip_mie_lcofie_op | |||||||||||||||||||||||||||||||
| reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the mhpmeventn.OF bits being set. |
norm:mip_lcofip_op2 | ||||||||||||||||||||||||||||||||
| When an OF bit is set, it eventually, but not necessarily immediately, sets the LCOFIP bit in the mip/sip registers. |
norm:LCOFIP_op | ||||||||||||||||||||||||||||||||
| mie_lcofie_op | If the Sscofpmf extension is implemented, bits mip.LCOFIP and mie.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. |
norm:mip_lcofip_mie_lcofie_op | |||||||||||||||||||||||||||||||
| mip_lcofip_acc | LCOFIP is read-write in mip | norm:mip_lcofip_acc | |||||||||||||||||||||||||||||||
| mip_lcofip_rdonly0 | If the Sscofpmf extension is not implemented, mip.LCOFIP and mie.LCOFIE are read-only zeros. |
norm:mip_lcofip_mie_lcofie_rdonly0 | |||||||||||||||||||||||||||||||
| mie_lcofie_rdonly0 | If the Sscofpmf extension is not implemented, mip.LCOFIP and mie.LCOFIE are read-only zeros. |
norm:mip_lcofip_mie_lcofie_rdonly0 | |||||||||||||||||||||||||||||||
| msip_sz | A hart's memory-mapped msip register is a 32-bit read/write register | norm:msip_sz_acc | |||||||||||||||||||||||||||||||
| msip_acc | A hart's memory-mapped msip register is a 32-bit read/write register | norm:msip_sz_acc | |||||||||||||||||||||||||||||||
| msip_enc | bits 31--1 read as zero and bit 0 contains the MSIP bit. | norm:msip_enc | |||||||||||||||||||||||||||||||
| MSIP_UPDATE_MAX_TIME | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| When the memory-mapped msip register changes, it is guaranteed to be reflected in mip.MSIP eventually, but not necessarily immediately. |
norm:msip_update_max_time | ||||||||||||||||||||||||||||||||
| mcycle_op | The mcycle CSR counts the number of clock cycles executed by the processor core on which the hart is running. |
norm:mcycle_op | |||||||||||||||||||||||||||||||
| mcycle_sz | The mcycle and minstret registers have 64-bit precision on all RV32 and RV64 harts. | norm:mcycle_minstret_sz | |||||||||||||||||||||||||||||||
| mcycle_rst | The counter registers have an arbitrary value after the hart is reset, and can be written with a given value. |
norm:mcycle_minstret_rst | |||||||||||||||||||||||||||||||
| mcycle_wr | Any CSR write takes effect after the writing instruction has otherwise completed. | norm:mcycle_minstret_wr | |||||||||||||||||||||||||||||||
| MCYCLE_SHARED | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The mcycle CSR may be shared between harts on the same core, in which case writes to mcycle will be visible to those harts. |
norm:mcycle_shared | ||||||||||||||||||||||||||||||||
| m_mode_perf_monitoring | M-mode includes a basic hardware performance-monitoring facility. | norm:m_mode_perf_monitoring | |||||||||||||||||||||||||||||||
| time_csr_architectural_availability | Implementations can convert reads of the time and timeh CSRs into loads to the memory-mapped mtime register, or emulate this functionality on behalf of less-privileged modes in M-mode software. |
norm:time_csr_architectural_availability | |||||||||||||||||||||||||||||||
| mcycleh_op | reads of the mcycleh, minstreth, mhpmcounternh, and mhpmeventnh CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32. |
norm:mcycleh_minstreth_mhpmh_op | |||||||||||||||||||||||||||||||
| minstreth_op | reads of the mcycleh, minstreth, mhpmcounternh, and mhpmeventnh CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32. |
norm:mcycleh_minstreth_mhpmh_op | |||||||||||||||||||||||||||||||
| mhpmcounterh_op | reads of the mcycleh, minstreth, mhpmcounternh, and mhpmeventnh CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32. |
norm:mcycleh_minstreth_mhpmh_op | |||||||||||||||||||||||||||||||
| mhpmeventh_op | reads of the mcycleh, minstreth, mhpmcounternh, and mhpmeventnh CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32. |
norm:mcycleh_minstreth_mhpmh_op | |||||||||||||||||||||||||||||||
| mhpmeventh_presence | The mhpmeventnh CSRs are provided only if the Sscofpmf extension is implemented. | norm:mhpmeventh_presence | |||||||||||||||||||||||||||||||
| minstret_op | The minstret CSR counts the number of instructions the hart has retired. | norm:minstret_op | |||||||||||||||||||||||||||||||
| minstret_sz | The mcycle and minstret registers have 64-bit precision on all RV32 and RV64 harts. | norm:mcycle_minstret_sz | |||||||||||||||||||||||||||||||
| minstret_rst | The counter registers have an arbitrary value after the hart is reset, and can be written with a given value. |
norm:mcycle_minstret_rst | |||||||||||||||||||||||||||||||
| minstret_wr | Any CSR write takes effect after the writing instruction has otherwise completed. | norm:mcycle_minstret_wr | |||||||||||||||||||||||||||||||
| mhpmcounter_num | The hardware performance monitor includes 29 additional 64-bit event counters, mhpmcounter3-mhpmcounter31. |
norm:mhpmcounter_num | |||||||||||||||||||||||||||||||
| MHPMCOUNTER_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The mhpmcounters are WARL registers | norm:mhpmcounter_warl | ||||||||||||||||||||||||||||||||
| mhpmcounter_mandatory | All counters should be implemented | norm:mhpmcounter_mandatory | |||||||||||||||||||||||||||||||
| MHPMCOUNTER_N_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| a legal implementation is to make both the counter and its corresponding event selector be read-only 0. | norm:mhpmcounter_mhpmevent_rdonly0 | ||||||||||||||||||||||||||||||||
| MHPMCOUNTER_N_SZ | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| support up to 64 bits of precision on RV32 and RV64. | norm:mhpmcounter_sz | ||||||||||||||||||||||||||||||||
| mhpmevent_sz | The event selector CSRs, mhpmevent3-mhpmevent31, are 64-bit WARL registers that control which event causes the corresponding counter to increment. |
norm:mhpmevent_sz_warl_op | |||||||||||||||||||||||||||||||
| mhpmevent_op | The event selector CSRs, mhpmevent3-mhpmevent31, are 64-bit WARL registers that control which event causes the corresponding counter to increment. |
norm:mhpmevent_sz_warl_op | |||||||||||||||||||||||||||||||
| MHPMEVENT_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The event selector CSRs, mhpmevent3-mhpmevent31, are 64-bit WARL registers that control which event causes the corresponding counter to increment. |
norm:mhpmevent_sz_warl_op | ||||||||||||||||||||||||||||||||
| mhpmevent_enc | The meaning of these events is defined by the platform, but event 0 is defined to mean "no event." |
norm:mhpmevent_enc | |||||||||||||||||||||||||||||||
| MHPMEVENT_N_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| a legal implementation is to make both the counter and its corresponding event selector be read-only 0. | norm:mhpmcounter_mhpmevent_rdonly0 | ||||||||||||||||||||||||||||||||
| mcounteren_sz | The counter-enable mcounteren register is a 32-bit register | norm:mcounteren_sz | |||||||||||||||||||||||||||||||
| mcounteren_op | controls the availability of the hardware performance-monitoring counters to the next-lower privileged mode. |
norm:mcounteren_op | |||||||||||||||||||||||||||||||
| mcounteren_inc_inaccessible | The settings in this register only control accessibility. The act of reading or writing this register does not affect the underlying counters, which continue to increment even when not accessible. |
norm:mcounteren_inc_inaccessible | |||||||||||||||||||||||||||||||
| mcounteren_enc | (No text available) | norm:mcounteren_enc_img | |||||||||||||||||||||||||||||||
| mcounteren_clr_ill_inst_exc | When the CY, TM, IR, or HPMn bit in the mcounteren register is clear, attempts to read the cycle, time, instret, or hpmcountern register while executing in S-mode or U-mode will cause an illegal-instruction exception. |
norm:mcounteren_clr_ill_inst_exc | |||||||||||||||||||||||||||||||
| mcounteren_set_nxt_priv | When one of these bits is set, access to the corresponding register is permitted in the next implemented privilege mode (S-mode if implemented, otherwise U-mode). |
norm:mcounteren_set_nxt_priv | |||||||||||||||||||||||||||||||
| mcounteren_tm_clr | when the TM bit in the mcounteren register is clear, attempts to access the stimecmp or vstimecmp register while executing in a mode less privileged than M will cause an illegal-instruction exception. |
norm:mcounteren_tm_clr | |||||||||||||||||||||||||||||||
| mcounteren_tm_set | When this bit is set, access to the stimecmp or vstimecmp register is permitted in S-mode if implemented, and access to the vstimecmp register (via stimecmp) is permitted in VS-mode if implemented and not otherwise prevented by the TM bit in hcounteren. |
norm:mcounteren_tm_set | |||||||||||||||||||||||||||||||
| mcounteren_flds_mandatory | In harts with U-mode, the mcounteren must be implemented, but all fields are WARL |
norm:mcounteren_flds_mandatory_warl | |||||||||||||||||||||||||||||||
| MCOUNTEREN_FLDS_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| In harts with U-mode, the mcounteren must be implemented, but all fields are WARL |
norm:mcounteren_flds_mandatory_warl | ||||||||||||||||||||||||||||||||
| MCOUNTEREN_CY_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||||||||||||||||||||||||
| MCOUNTEREN_TM_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||||||||||||||||||||||||
| MCOUNTEREN_IR_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||||||||||||||||||||||||
| MCOUNTEREN_HPM_N_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||||||||||||||||||||||||
| mcounteren_presence | In harts without U-mode, the mcounteren register should not exist. | norm:mcounteren_presence | |||||||||||||||||||||||||||||||
| cycle_op | The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter n, respectively. | norm:cycle_instret_hpmcounter_op_rdonly | |||||||||||||||||||||||||||||||
| instret_op | The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter n, respectively. | norm:cycle_instret_hpmcounter_op_rdonly | |||||||||||||||||||||||||||||||
| hpmcounter_op | The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter n, respectively. | norm:cycle_instret_hpmcounter_op_rdonly | |||||||||||||||||||||||||||||||
| cycle_rdonly | The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter n, respectively. | norm:cycle_instret_hpmcounter_op_rdonly | |||||||||||||||||||||||||||||||
| instret_rdonly | The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter n, respectively. | norm:cycle_instret_hpmcounter_op_rdonly | |||||||||||||||||||||||||||||||
| hpmcounter_rdonly | The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter n, respectively. | norm:cycle_instret_hpmcounter_op_rdonly | |||||||||||||||||||||||||||||||
| time_op | The time CSR is a read-only shadow of the memory-mapped mtime register. | norm:time_op_rdonly | |||||||||||||||||||||||||||||||
| time_rdonly | The time CSR is a read-only shadow of the memory-mapped mtime register. | norm:time_op_rdonly | |||||||||||||||||||||||||||||||
| time_visibility_mtime | When mtime changes, it is guaranteed to be reflected in time and timeh eventually, but not necessarily immediately. |
norm:time_timeh_visibility_mtime | |||||||||||||||||||||||||||||||
| cycleh_op | when XLEN=32, the cycleh, instreth and hpmcounternh CSRs are read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively. |
norm:cycleh_instreth_hpmcounternh_op_rdonly | |||||||||||||||||||||||||||||||
| instreth_op | when XLEN=32, the cycleh, instreth and hpmcounternh CSRs are read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively. |
norm:cycleh_instreth_hpmcounternh_op_rdonly | |||||||||||||||||||||||||||||||
| hpmcounternh_op | when XLEN=32, the cycleh, instreth and hpmcounternh CSRs are read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively. |
norm:cycleh_instreth_hpmcounternh_op_rdonly | |||||||||||||||||||||||||||||||
| cycleh_rdonly | when XLEN=32, the cycleh, instreth and hpmcounternh CSRs are read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively. |
norm:cycleh_instreth_hpmcounternh_op_rdonly | |||||||||||||||||||||||||||||||
| instreth_rdonly | when XLEN=32, the cycleh, instreth and hpmcounternh CSRs are read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively. |
norm:cycleh_instreth_hpmcounternh_op_rdonly | |||||||||||||||||||||||||||||||
| hpmcounternh_rdonly | when XLEN=32, the cycleh, instreth and hpmcounternh CSRs are read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively. |
norm:cycleh_instreth_hpmcounternh_op_rdonly | |||||||||||||||||||||||||||||||
| timeh_op | When XLEN=32, the timeh CSR is a read-only shadow of the upper 32 bits of the memory-mapped mtime register |
norm:timeh_op_rdonly | |||||||||||||||||||||||||||||||
| timeh_rdonly | When XLEN=32, the timeh CSR is a read-only shadow of the upper 32 bits of the memory-mapped mtime register |
norm:timeh_op_rdonly | |||||||||||||||||||||||||||||||
| timeh_visibility_mtime | When mtime changes, it is guaranteed to be reflected in time and timeh eventually, but not necessarily immediately. |
norm:time_timeh_visibility_mtime | |||||||||||||||||||||||||||||||
| mcountinhibit_enc | (No text available) | norm:mcountinhibit_enc_img | |||||||||||||||||||||||||||||||
| mcountinhibit_sz | The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
norm:mcountinhibit_sz_warl_op1 | |||||||||||||||||||||||||||||||
| MCOUNTINHIBIT_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
norm:mcountinhibit_sz_warl_op1 | ||||||||||||||||||||||||||||||||
| mcountinhibit_only_inc | The settings in this register only control whether the counters increment; their accessibility is not affected by the setting of this register. |
norm:mcountinhibit_only_inc | |||||||||||||||||||||||||||||||
| mcountinhibit_op | The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
norm:mcountinhibit_sz_warl_op1 | |||||||||||||||||||||||||||||||
| When the CY, IR, or HPMn bit in the mcountinhibit register is clear, the mcycle, minstret, or mhpmcountern register increments as usual. When the CY, IR, or HPMn bit is set, the corresponding counter does not increment. |
norm:mcountinhibit_op2 | ||||||||||||||||||||||||||||||||
| mcountinhibit_cy_shared | The mcycle CSR may be shared between harts on the same core, in which case the mcountinhibit.CY field is also shared between those harts, and so writes to mcountinhibit.CY will be visible to those harts. |
norm:mcountinhibit_cy_shared | |||||||||||||||||||||||||||||||
| mcountinhibit_not_impl | If the mcountinhibit register is not implemented, the implementation behaves as though the register were set to zero. |
norm:mcountinhibit_not_impl | |||||||||||||||||||||||||||||||
| mscratch_sz | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
norm:mscratch_sz_acc | |||||||||||||||||||||||||||||||
| mscratch_acc | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
norm:mscratch_sz_acc | |||||||||||||||||||||||||||||||
| mscratch_enc | (No text available) | norm:mscratch_enc_img | |||||||||||||||||||||||||||||||
| mepc_sz | mepc is an MXLEN-bit read/write register | norm:mepc_sz_acc | |||||||||||||||||||||||||||||||
| mepc_acc | mepc is an MXLEN-bit read/write register | norm:mepc_sz_acc | |||||||||||||||||||||||||||||||
| mepc_align | The low bit of mepc (mepc[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (mepc[1:0]) are always zero. | norm:mepc_align | |||||||||||||||||||||||||||||||
| mepc_bit1_dyn_ialign_op | If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), then, whenever IALIGN=32, bit mepc[1] is masked on reads so that it appears to be 0. This masking occurs also for the implicit read by the MRET instruction. Though masked, mepc[1] remains writable when IALIGN=32. |
norm:mepc_bit1_dyn_ialign_op | |||||||||||||||||||||||||||||||
| MEPC_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| mepc is a WARL register | norm:mepc_warl | ||||||||||||||||||||||||||||||||
| MEPC_INV_ADDR_CONV | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Prior to writing mepc, implementations may convert an invalid address into some other invalid address that mepc is capable of holding. |
norm:mepc_inv_addr_conv | ||||||||||||||||||||||||||||||||
| mepc_op | When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mepc is never written by the implementation, though it may be explicitly written by software. |
norm:mepc_op | |||||||||||||||||||||||||||||||
| mepc_enc | (No text available) | norm:mepc_enc_img | |||||||||||||||||||||||||||||||
| mepc_varlen_wr | [CONTEXT] If mtval is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then mtval will contain the virtual address of the portion of the instruction that caused the fault |
norm:mtval_varlen_wr | |||||||||||||||||||||||||||||||
| mepc will point to the beginning of the instruction. | norm:mepc_varlen_wr | ||||||||||||||||||||||||||||||||
| mcause_sz | The mcause register is an MXLEN-bit read-write register | norm:mcause_sz_acc | |||||||||||||||||||||||||||||||
| mcause_acc | The mcause register is an MXLEN-bit read-write register | norm:mcause_sz_acc | |||||||||||||||||||||||||||||||
| mcause_enc | (No text available) | norm:mcause_enc_img | |||||||||||||||||||||||||||||||
| mcause_op | When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. Otherwise, mcause is never written by the implementation, though it may be explicitly written by software. |
norm:mcause_op | |||||||||||||||||||||||||||||||
| mcause_intr_op | The Interrupt bit in the mcause register is set if the trap was caused by an interrupt. |
norm:mcause_intr_op | |||||||||||||||||||||||||||||||
| mcause_exccode_op | The Exception Code field contains a code identifying the last exception or interrupt. |
norm:mcause_exccode_op | |||||||||||||||||||||||||||||||
| mcause_exccode_enc |
|
norm:mcause_exccode_enc_img | |||||||||||||||||||||||||||||||
| MCAUSE_EXCCODE_WLRL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WLRL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The Exception Code is a WLRL field, so is only guaranteed to hold supported exception codes. | norm:mcause_exccode_wlrl | ||||||||||||||||||||||||||||||||
| mcause_exccode_ld_ldrsv | Note that load and load-reserved instructions generate load exceptions | norm:mcause_exccode_ld_ldrsv | |||||||||||||||||||||||||||||||
| mcause_exccode_st_sc_amo | store, store-conditional, and AMO instructions generate store/AMO exceptions. |
norm:mcause_exccode_st_sc_amo | |||||||||||||||||||||||||||||||
| mcause_exccode_pri | If an instruction may raise multiple synchronous exceptions, the decreasing priority order of norm:exc_priority indicates which exception is taken and reported in mcause. |
norm:mcause_exccode_pri1 | |||||||||||||||||||||||||||||||
| Load/store/AMO address-misaligned exceptions may have either higher or lower priority than load/store/AMO page-fault and access-fault exceptions. |
norm:mcause_exccode_pri2 | ||||||||||||||||||||||||||||||||
| mtval_sz | The mtval register is an MXLEN-bit read-write register formatted as shown in norm:mtval_enc_img |
norm:mtval_sz_acc | |||||||||||||||||||||||||||||||
| mtval_acc | The mtval register is an MXLEN-bit read-write register formatted as shown in norm:mtval_enc_img |
norm:mtval_sz_acc | |||||||||||||||||||||||||||||||
| mtval_enc | (No text available) | norm:mtval_enc_img | |||||||||||||||||||||||||||||||
| mtval_vaddr_and_0_sz | must be able to hold all valid virtual addresses and the value zero. | norm:mtval_vaddr_and_0_sz | |||||||||||||||||||||||||||||||
| mtval_instr_bits_sz | If the feature to return the faulting instruction bits is implemented, mtval must also be able to hold all values less than 2N, where N is the smaller of MXLEN and ILEN. |
norm:mtval_instr_bits_sz | |||||||||||||||||||||||||||||||
| mtval_op | When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap. Otherwise, mtval is never written by the implementation, though it may be explicitly written by software. |
norm:mtval_op | |||||||||||||||||||||||||||||||
| MTVAL_PER_EXC_BEHAVIOR | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The hardware platform will specify which exceptions must set mtval informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception. |
norm:mtval_per_exc_behavior | ||||||||||||||||||||||||||||||||
| MTVAL_RDONLY0 | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If the hardware platform specifies that no exceptions set mtval to a nonzero value, then mtval is read-only zero. |
norm:mtval_rdonly0 | ||||||||||||||||||||||||||||||||
| mtval_vaddr_wr1 | If mtval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address. |
norm:mtval_vaddr_wr1 | |||||||||||||||||||||||||||||||
| mtval_vaddr_not_paddr | When page-based virtual memory is enabled, mtval is written with the faulting virtual address, even for physical-memory access-fault exceptions. |
norm:mtval_vaddr_not_paddr | |||||||||||||||||||||||||||||||
| mtval_vaddr_wr2 | If mtval is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then mtval will contain the virtual address of the portion of the access that caused the fault. |
norm:mtval_vaddr_wr2 | |||||||||||||||||||||||||||||||
| MTVAL_VARLEN_WR | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If mtval is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then mtval will contain the virtual address of the portion of the instruction that caused the fault |
norm:mtval_varlen_wr | ||||||||||||||||||||||||||||||||
| mtval_instr_bits | The mtval register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception |
norm:mtval_instr_bits_lead-in | |||||||||||||||||||||||||||||||
| the actual faulting instruction the first ILEN bits of the faulting instruction the first MXLEN bits of the faulting instruction |
norm:mtval_instr_bits_list | ||||||||||||||||||||||||||||||||
| mtval_ill_instr_exc_in_low_bits | The value loaded into mtval on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero. |
norm:mtval_ill_instr_exc_in_low_bits | |||||||||||||||||||||||||||||||
| mtval_swchk | On a trap caused by a software-check exception, the mtval register holds the cause for the exception. The following encodings are defined: |
norm:mtval_swchk_lead-in | |||||||||||||||||||||||||||||||
| 0 - No information provided. 2 - Landing Pad Fault. Defined by the Zicfilp extension (). 3 - Shadow Stack Fault. Defined by the Zicfiss extension (). |
norm:mtval_swchk_list | ||||||||||||||||||||||||||||||||
| mtval_other_traps_zero | For other traps, mtval is set to zero | norm:mtval_other_traps_zero | |||||||||||||||||||||||||||||||
| MTVAL_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| If mtval is not read-only zero, it is a WARL register | norm:mtval_warl | ||||||||||||||||||||||||||||||||
| MTVAL_INV_ADDR_CONV | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Prior to writing mtval, implementations may convert an invalid address into some other invalid address that mtval is capable of holding. |
norm:mtval_inv_addr_conv | ||||||||||||||||||||||||||||||||
| mconfigptr_sz | The mconfigptr register is an MXLEN-bit read-only CSR formatted as shown in norm:mconfigptr_enc_img | norm:mconfigptr_sz_acc | |||||||||||||||||||||||||||||||
| mconfigptr_acc | The mconfigptr register is an MXLEN-bit read-only CSR formatted as shown in norm:mconfigptr_enc_img | norm:mconfigptr_sz_acc | |||||||||||||||||||||||||||||||
| mconfigptr_enc | (No text available) | norm:mconfigptr_enc_img | |||||||||||||||||||||||||||||||
| mconfigptr_op | holds the physical address of a configuration data structure. | norm:mconfigptr_op | |||||||||||||||||||||||||||||||
| mconfigptr_align | The pointer alignment in bits must be no smaller than MXLEN: i.e., if MXLEN is 8{times}n, then mconfigptr[log2n-1:0] must be zero. |
norm:mconfigptr_align | |||||||||||||||||||||||||||||||
| mconfigptr_mandatory | The mconfigptr register must be implemented | norm:mconfigptr_mandatory | |||||||||||||||||||||||||||||||
| MCONFIGPTR_VAL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| it may be zero to indicate the configuration data structure does not exist or that an alternative mechanism must be used to locate it. |
norm:mconfigptr_val | ||||||||||||||||||||||||||||||||
| menvcfg_sz | The menvcfg CSR is a 64-bit read/write register, formatted as shown in norm:menvcfg_enc_img |
norm:menvcfg_sz_acc | |||||||||||||||||||||||||||||||
| menvcfg_acc | The menvcfg CSR is a 64-bit read/write register, formatted as shown in norm:menvcfg_enc_img |
norm:menvcfg_sz_acc | |||||||||||||||||||||||||||||||
| menvcfg_op | controls certain characteristics of the execution environment for modes less privileged than M. |
norm:menvcfg_op | |||||||||||||||||||||||||||||||
| menvcfg_enc | (No text available) | norm:menvcfg_enc_img | |||||||||||||||||||||||||||||||
| menvcfg_fiom_fence_op | If bit FIOM (Fence of I/O implies Memory) is set to one in menvcfg, FENCE instructions executed in modes less privileged than M are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. norm:menvcfg_fiom_fence_presuc_op details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO for modes less privileged than M when FIOM=1. |
norm:menvcfg_fiom_fence_op | |||||||||||||||||||||||||||||||
| menvcfg_fiom_atomic_op | for modes less privileged than M when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory. |
norm:menvcfg_fiom_atomic_op | |||||||||||||||||||||||||||||||
| menvcfg_fiom_fence_presuc_op |
|
norm:menvcfg_fiom_fence_presuc_op | |||||||||||||||||||||||||||||||
| MENVCFG_FIOM_RDONLY0_OK | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If S-mode is not supported, or if satp.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero. |
norm:menvcfg_fiom_rdonly0_ok | ||||||||||||||||||||||||||||||||
| menvcfg_no_U_mode | If U-mode is not supported, then registers menvcfg and menvcfgh do not exist. |
norm:menvcfg_menvcfgh_no_U_mode | |||||||||||||||||||||||||||||||
| menvcfg_pbmte_op | The PBMTE bit controls whether the Svpbmt extension is available for use in S-mode and G-stage address translation (i.e., for page tables pointed to by satp or hgatp). When PBMTE=1, Svpbmt is available for S-mode and G-stage address translation. When PBMTE=0, the implementation behaves as though Svpbmt were not implemented. |
norm:menvcfg_pbmte_op | |||||||||||||||||||||||||||||||
| menvcfg_pbmte_rdonly0 | If Svpbmt is not implemented, PBMTE is read-only zero. | norm:menvcfg_pbmte_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_pbmte_henvcfg_pbmte_rdonly0 | for implementations with the hypervisor extension, henvcfg.PBMTE is read-only zero if menvcfg.PBMTE is zero. |
norm:menvcfg_pbmte_henvcfg_pbmte_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_pbmte_fence | After changing menvcfg.PBMTE, executing an SFENCE.VMA instruction with rs1=x0 and rs2=x0 suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' PBMT fields. |
norm:menvcfg_pbmte_fence | |||||||||||||||||||||||||||||||
| menvcfg_adue_op | If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for S-mode and G-stage address translations. When ADUE=1, hardware updating of PTE A/D bits is enabled during S-mode address translation, and the implementation behaves as though the Svade extension were not implemented for S-mode address translation. When the hypervisor extension is implemented, if ADUE=1, hardware updating of PTE A/D bits is enabled during G-stage address translation, and the implementation behaves as though the Svade extension were not implemented for G-stage address translation. When ADUE=0, the implementation behaves as though Svade were implemented for S-mode and G-stage address translation. |
norm:menvcfg_adue_op | |||||||||||||||||||||||||||||||
| menvcfg_adue_rdonly0 | If Svadu is not implemented, ADUE is read-only zero. | norm:menvcfg_adue_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_adue_henvcfg_adue_rdonly0 | for implementations with the hypervisor extension, henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. |
norm:menvcfg_adue_henvcfg_adue_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_adue_fence | After changing menvcfg.ADUE, executing an SFENCE.VMA instruction with rs1=x0 and rs2=x0 suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' A/D bits. |
norm:menvcfg_adue_fence | |||||||||||||||||||||||||||||||
| menvcfg_cde_op | If the Smcdeleg extension is implemented, the CDE (Counter Delegation Enable) bit controls whether Zicntr and Zihpm counters can be delegated to S-mode. When CDE=1, the Smcdeleg extension is enabled, see smcdeleg. When CDE=0, the Smcdeleg and Ssccfg extensions appear to be not implemented. |
norm:menvcfg_cde_op | |||||||||||||||||||||||||||||||
| menvcfg_cde_rdonly0 | If Smcdeleg is not implemented, CDE is read-only zero. | norm:menvcfg_cde_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_stce_op | The Sstc extension adds the STCE (STimecmp Enable) bit to menvcfg CSR. | norm:menvcfg_stce_op1 | |||||||||||||||||||||||||||||||
| The STCE bit enables stimecmp for S-mode when set to one. When this extension is implemented and STCE in menvcfg is zero, an attempt to access stimecmp in a mode other than M-mode raises an illegal-instruction exception, STCE in henvcfg is read-only zero, and STIP in mip and sip reverts to its defined behavior as if this extension is not implemented. Further, if the H extension is implemented, then hip.VSTIP also reverts its defined behavior as if this extension is not implemented. |
norm:menvcfg_stce_op2 | ||||||||||||||||||||||||||||||||
| menvcfg_stce_rdonly0 | When the Sstc extension is not implemented, STCE is read-only zero. | norm:menvcfg_stce_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_cbze_op | The Zicboz extension adds the CBZE (Cache Block Zero instruction enable) field to menvcfg. When the CBZE field is set to 1, it enables execution of the cache block zero instruction, CBO.ZERO, in modes less privileged than M. Otherwise, the instruction raises an illegal-instruction exception in modes less privileged than M. |
norm:menvcfg_cbze_op | |||||||||||||||||||||||||||||||
| menvcfg_cbze_rdonly0 | When the Zicboz extension is not implemented, CBZE is read-only zero. | norm:menvcfg_cbze_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_cbcfe_op | The Zicbom extension adds the CBCFE (Cache Block Clean and Flush instruction Enable) field to menvcfg. When the CBCFE field is set to 1, it enables execution of the cache block clean instruction (CBO.CLEAN) and the cache block flush instruction (CBO.FLUSH) in modes less privileged than M. Otherwise, these instructions raise an illegal-instruction exception in modes less privileged than M. |
norm:menvcfg_cbcfe_op | |||||||||||||||||||||||||||||||
| menvcfg_cbcfe_rdonly0 | When the Zicbom extension is not implemented, CBCFE is read-only zero. | norm:menvcfg_cbcfe_rdonly0 | |||||||||||||||||||||||||||||||
| MENVCFG_CBIE_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to menvcfg to control execution of the cache block invalidate instruction (CBO.INVAL) in modes less privileged than M. When CBIE is set to 00b, the instruction raises an illegal-instruction exception in modes less privileged than M. |
norm:menvcfg_cbie_warl_op | ||||||||||||||||||||||||||||||||
| menvcfg_cbie_op | The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to menvcfg to control execution of the cache block invalidate instruction (CBO.INVAL) in modes less privileged than M. When CBIE is set to 00b, the instruction raises an illegal-instruction exception in modes less privileged than M. |
norm:menvcfg_cbie_warl_op | |||||||||||||||||||||||||||||||
| menvcfg_cbie_rdonly0 | When the Zicbom extension is not implemented, CBIE is read-only zero. | norm:menvcfg_cbie_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_cbie_cbo-inval_op | When CBIE is set to 01b or 11b, and when enabled for execution in modes less privileged than M, it behaves as follows: |
norm:menvcfg_cbie_cbo-inval_op_lead-in | |||||||||||||||||||||||||||||||
| 01b — The instruction is executed and performs a flush operation, even if configured by a mode less privileged than M to perform an invalidate operation. 11b — The instruction is executed and performs an invalidate operation, unless configured by a mode less privileged than M to perform a flush operation. |
norm:menvcfg_cbie_cbo-inval_op_list | ||||||||||||||||||||||||||||||||
| menvcfg_pmm_op | If the Smnpm extension is implemented, the PMM field enables or disables pointer masking (see Zpm) for the next-lower privilege mode (S-/HS-mode if S-mode is implemented, or U-mode otherwise), according to the values in norm:menvcfg_pmm_enc. |
norm:menvcfg_pmm_op | |||||||||||||||||||||||||||||||
| menvcfg_pmm_rdonly0 | If Smnpm is not implemented, PMM is read-only zero. The PMM field is read-only zero for RV32. |
norm:menvcfg_pmm_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_pmm_enc |
|
norm:menvcfg_pmm_enc | |||||||||||||||||||||||||||||||
| menvcfg_lpe_op | The Zicfilp extension adds the LPE field in menvcfg. When the LPE field is set to 1 and S-mode is implemented, the Zicfilp extension is enabled in S-mode. If LPE field is set to 1 and S-mode is not implemented, the Zicfilp extension is enabled in U-mode. When the LPE field is 0, the Zicfilp extension is not enabled in S-mode, and the following rules apply to S-mode. If the LPE field is 0 and S-mode is not implemented, then the same rules apply to U-mode. |
norm:menvcfg_lpe_op_lead-in | |||||||||||||||||||||||||||||||
| The hart does not update the ELP state; it remains as NO_LP_EXPECTED. The LPAD instruction operates as a no-op. |
norm:menvcfg_lpe_op_list | ||||||||||||||||||||||||||||||||
| menvcfg_sse_op | The Zicfiss extension adds the SSE field to menvcfg. When the SSE field is set to 1 the Zicfiss extension is activated in S-mode. When SSE field is 0, the following rules apply to privilege modes that are less than M: |
norm:menvcfg_sse_op_lead-in | |||||||||||||||||||||||||||||||
| 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. The pte.xwr=010b encoding in VS/S-stage page tables becomes reserved. SSAMOSWAP.W/D raises an illegal-instruction exception. |
norm:menvcfg_sse_op_list | ||||||||||||||||||||||||||||||||
| menvcfg_sse_rdonly0 | When menvcfg.SSE is 0, the henvcfg.SSE and senvcfg.SSE fields are read-only zero. |
norm:menvcfg_sse_rdonly0 | |||||||||||||||||||||||||||||||
| menvcfg_dte_op | The Ssdbltrp extension adds the double-trap-enable (DTE) field in menvcfg. When menvcfg.DTE is zero, the implementation behaves as though Ssdbltrp is not implemented. When Ssdbltrp is not implemented sstatus.SDT, vsstatus.SDT, and henvcfg.DTE bits are read-only zero. |
norm:menvcfg_dte_op | |||||||||||||||||||||||||||||||
| menvcfgh_sz | When XLEN=32, menvcfgh is a 32-bit read/write register that aliases bits 63:32 of menvcfg. The menvcfgh register does not exist when XLEN=64. |
norm:menvcfgh_sz_acc_op | |||||||||||||||||||||||||||||||
| menvcfgh_acc | When XLEN=32, menvcfgh is a 32-bit read/write register that aliases bits 63:32 of menvcfg. The menvcfgh register does not exist when XLEN=64. |
norm:menvcfgh_sz_acc_op | |||||||||||||||||||||||||||||||
| menvcfgh_op | When XLEN=32, menvcfgh is a 32-bit read/write register that aliases bits 63:32 of menvcfg. The menvcfgh register does not exist when XLEN=64. |
norm:menvcfgh_sz_acc_op | |||||||||||||||||||||||||||||||
| menvcfgh_no_U_mode | If U-mode is not supported, then registers menvcfg and menvcfgh do not exist. |
norm:menvcfg_menvcfgh_no_U_mode | |||||||||||||||||||||||||||||||
| mseccfg_sz | mseccfg is a 64-bit read/write register, formatted as shown in norm:mseccfg_enc_img, that controls security features. |
norm:mseccfg_sz_acc | |||||||||||||||||||||||||||||||
| mseccfg_acc | mseccfg is a 64-bit read/write register, formatted as shown in norm:mseccfg_enc_img, that controls security features. |
norm:mseccfg_sz_acc | |||||||||||||||||||||||||||||||
| mseccfg_enc | (No text available) | norm:mseccfg_enc_img | |||||||||||||||||||||||||||||||
| mseccfg_presence | It exists if any extension that adds a field to mseccfg is implemented. Otherwise, it is reserved. | norm:mseccfg_presence | |||||||||||||||||||||||||||||||
| mseccfg_sseed_presence | The Zkr extension adds the SSEED and USEED fields to the mseccfg CSR to control access to the seed CSR from modes less privileged than M. | norm:mseccfg_sseed_useed_presence | |||||||||||||||||||||||||||||||
| mseccfg_useed_presence | The Zkr extension adds the SSEED and USEED fields to the mseccfg CSR to control access to the seed CSR from modes less privileged than M. | norm:mseccfg_sseed_useed_presence | |||||||||||||||||||||||||||||||
| mseccfg_useed_U-mode_op | When USEED is 0, access to the seed CSR in U-mode raises an illegal-instruction exception. When USEED is 1, read-write access to the seed CSR from U-mode is allowed; all other types of accesses raise an illegal-instruction exception. |
norm:mseccfg_useed_U-mode_op | |||||||||||||||||||||||||||||||
|
norm:mseccfg_sseed_useed_op_tbl | ||||||||||||||||||||||||||||||||
| mseccfg_useed_rdonly0 | If Zkr or U-mode is not implemented, USEED is read-only zero. | norm:mseccfg_useed_rdonly0 | |||||||||||||||||||||||||||||||
| mseccfg_sseed_S_mode_op | When SSEED is 0, access to the seed CSR from S-/HS-mode raises an illegal-instruction exception. When SSEED is 1, read-write access to the seed CSR from S-/HS-mode is allowed; all other types of accesses raise an illegal-instruction exception. |
norm:mseccfg_sseed_SorHS-mode_op | |||||||||||||||||||||||||||||||
|
norm:mseccfg_sseed_useed_op_tbl | ||||||||||||||||||||||||||||||||
| mseccfg_sseed_HS_mode_op | When SSEED is 0, access to the seed CSR from S-/HS-mode raises an illegal-instruction exception. When SSEED is 1, read-write access to the seed CSR from S-/HS-mode is allowed; all other types of accesses raise an illegal-instruction exception. |
norm:mseccfg_sseed_SorHS-mode_op | |||||||||||||||||||||||||||||||
|
norm:mseccfg_sseed_useed_op_tbl | ||||||||||||||||||||||||||||||||
| mseccfg_sseed_rdonly0 | If Zkr or S-mode is not implemented, SSEED is read-only zero. | norm:mseccfg_sseed_rdonly0 | |||||||||||||||||||||||||||||||
| mseccfg_sseed_VS_mode_op | When the H extension is also implemented, access to the seed CSR from an HS-qualified instruction leads to a virtual-instruction exception in VS and VU modes; all other types of accesses raise an illegal-instruction exception. |
norm:mseccfg_sseed_VSorVU-mode_op | |||||||||||||||||||||||||||||||
|
norm:mseccfg_sseed_useed_op_tbl | ||||||||||||||||||||||||||||||||
| mseccfg_sseed_VU_mode_op | When the H extension is also implemented, access to the seed CSR from an HS-qualified instruction leads to a virtual-instruction exception in VS and VU modes; all other types of accesses raise an illegal-instruction exception. |
norm:mseccfg_sseed_VSorVU-mode_op | |||||||||||||||||||||||||||||||
|
norm:mseccfg_sseed_useed_op_tbl | ||||||||||||||||||||||||||||||||
| mseccfg_rlb_presence | The Smepmp extension adds the RLB, MMWP, and the MML fields in mseccfg. | norm:mseccfg_rlb_mmwp_mml_presence | |||||||||||||||||||||||||||||||
| mseccfg_mmwp_presence | The Smepmp extension adds the RLB, MMWP, and the MML fields in mseccfg. | norm:mseccfg_rlb_mmwp_mml_presence | |||||||||||||||||||||||||||||||
| mseccfg_mml_presence | The Smepmp extension adds the RLB, MMWP, and the MML fields in mseccfg. | norm:mseccfg_rlb_mmwp_mml_presence | |||||||||||||||||||||||||||||||
| mseccfg_rlb_op | When mseccfg.RLB (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify Locked PMP rules. When mseccfg.RLB is 1, locked PMP rules may be removed or modified and locked PMP rules may be edited. When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset. | norm:mseccfg_rlb_op_warl | |||||||||||||||||||||||||||||||
| MSECCFG_RLB_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| When mseccfg.RLB (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify Locked PMP rules. When mseccfg.RLB is 1, locked PMP rules may be removed or modified and locked PMP rules may be edited. When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset. | norm:mseccfg_rlb_op_warl | ||||||||||||||||||||||||||||||||
| mseccfg_mmwp_op | The mseccfg.MMWP (Machine-Mode Allowlist Policy) is a WARL field. This field changes the default PMP policy for Machine mode when accessing memory regions that don’t have a matching PMP rule. This is a sticky bit, meaning that once set it cannot be unset until a PMP reset. When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching PMP rule, to denied instead of ignored. | norm:mseccfg_mmwp_op_warl | |||||||||||||||||||||||||||||||
| MSECCFG_MMWP_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The mseccfg.MMWP (Machine-Mode Allowlist Policy) is a WARL field. This field changes the default PMP policy for Machine mode when accessing memory regions that don’t have a matching PMP rule. This is a sticky bit, meaning that once set it cannot be unset until a PMP reset. When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching PMP rule, to denied instead of ignored. | norm:mseccfg_mmwp_op_warl | ||||||||||||||||||||||||||||||||
| MSECCFG_MML_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The mseccfg.MML (Machine Mode Lockdown) is a WARL field. | norm:mseccfg_mml_warl | ||||||||||||||||||||||||||||||||
| mseccfg_mml_sticky | This is a sticky bit, meaning that once set it cannot be unset until a PMP reset. |
norm:mseccfg_mml_sticky | |||||||||||||||||||||||||||||||
| mseccfg_mml_pmpcfg_L_op | [CONTEXT] When mseccfg.MML is set the system's behavior changes in the following way: | norm:mseccfg_mml_set | |||||||||||||||||||||||||||||||
| The meaning of pmpcfg.L changes: Instead of marking a rule as locked and enforced in all modes, it now marks a rule as M-mode-only when set and S/U-mode-only when unset. The formerly reserved encoding of pmpcfg.RW=01, and the encoding pmpcfg.LRWX=1111, now encode a Shared-Region. |
norm:mseccfg_mml_pmpcfg_L_op | ||||||||||||||||||||||||||||||||
| mseccfg_mml_M_rule_op | [CONTEXT] When mseccfg.MML is set the system's behavior changes in the following way: | norm:mseccfg_mml_set | |||||||||||||||||||||||||||||||
| An M-mode-only rule is enforced on Machine mode and denied in Supervisor or User mode. It also remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set. |
norm:mseccfg_mml_M_rule_op | ||||||||||||||||||||||||||||||||
| mseccfg_mml_SorU_rule_op | [CONTEXT] When mseccfg.MML is set the system's behavior changes in the following way: | norm:mseccfg_mml_set | |||||||||||||||||||||||||||||||
| An S/U-mode-only rule is enforced on Supervisor and User modes and denied on Machine mode. |
norm:mseccfg_mml_SorU_rule_op | ||||||||||||||||||||||||||||||||
| mseccfg_mml_shared_rule_op | [CONTEXT] When mseccfg.MML is set the system's behavior changes in the following way: | norm:mseccfg_mml_set | |||||||||||||||||||||||||||||||
| A Shared-Region rule is enforced on all modes, with restrictions depending on the pmpcfg.L and pmpcfg.X bits: |
norm:mseccfg_mml_shared_rule_op | ||||||||||||||||||||||||||||||||
| A Shared-Region rule where pmpcfg.L is not set can be used for sharing data between M-mode and S/U-mode, so is not executable. M-mode has read/write access to that region, and S/U-mode has read access if pmpcfg.X is not set, or read/write access if pmpcfg.X is set. |
norm:mseccfg_mml_shared_L0_op | ||||||||||||||||||||||||||||||||
| A Shared-Region rule where pmpcfg.L is set can be used for sharing code between M-mode and S/U-mode, so is not writable. Both M-mode and S/U-mode have execute access on the region, and M-mode also has read access if pmpcfg.X is set. The rule remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set. |
norm:mseccfg_mml_shared_L1_op | ||||||||||||||||||||||||||||||||
| The encoding pmpcfg.LRWX=1111 can be used for sharing data between M-mode and S/U mode, where both modes only have read-only access to the region. The rule remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set. |
norm:mseccfg_mml_shared_LRWX_1111_op | ||||||||||||||||||||||||||||||||
| mseccfg_mml_X_restrict | Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. This restriction can be temporarily lifted by setting mseccfg.RLB |
norm:mseccfg_mml_X_restrict | |||||||||||||||||||||||||||||||
| mseccfg_mml_exec_code | Executing code with Machine mode privileges is only possible from memory regions with a matching M-mode-only rule or a locked Shared-Region rule with executable privileges. Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied. |
norm:mseccfg_mml_exec_code | |||||||||||||||||||||||||||||||
| mseccfg_pmm_presence | If the Smmpm extension is implemented, the PMM field enables or disables pointer masking (see Zpm) for M-mode according to the values in norm:mseccfg_pmm_enc. |
norm:mseccfg_pmm_presence_op | |||||||||||||||||||||||||||||||
| mseccfg_pmm_op | If the Smmpm extension is implemented, the PMM field enables or disables pointer masking (see Zpm) for M-mode according to the values in norm:mseccfg_pmm_enc. |
norm:mseccfg_pmm_presence_op | |||||||||||||||||||||||||||||||
| mseccfg_pmm_rdonly0 | If Smmpm is not implemented, PMM is read-only zero. The PMM field is read-only zero for RV32. |
norm:mseccfg_pmm_rdonly0 | |||||||||||||||||||||||||||||||
| mseccfg_pmm_enc |
|
norm:mseccfg_pmm_enc | |||||||||||||||||||||||||||||||
| MSECCFG_PMM_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
|
norm:mseccfg_pmm_enc | ||||||||||||||||||||||||||||||||
| mseccfg_mlpe_presence | The Zicfilp extension adds the MLPE field in mseccfg. | norm:mseccfg_mlpe_presence | |||||||||||||||||||||||||||||||
| mseccfg_mlpe_set_op | When MLPE field is 1, Zicfilp extension is enabled in M-mode. | norm:mseccfg_mlpe_set_op | |||||||||||||||||||||||||||||||
| mseccfg_mlpe_clr_op | When the MLPE field is 0, the Zicfilp extension is not enabled in M-mode and the following rules apply to M-mode. |
norm:mseccfg_mlpe_clr_op_lead-in | |||||||||||||||||||||||||||||||
| The hart does not update the ELP state; it remains as NO_LP_EXPECTED. The LPAD instruction operates as a no-op. |
norm:mseccfg_mlpe_clr_op_list | ||||||||||||||||||||||||||||||||
| mseccfgh_sz | When XLEN=32 only, mseccfgh is a 32-bit read/write register that aliases bits 63:32 of mseccfg. |
norm:mseccfgh_sz_acc_op | |||||||||||||||||||||||||||||||
| mseccfgh_acc | When XLEN=32 only, mseccfgh is a 32-bit read/write register that aliases bits 63:32 of mseccfg. |
norm:mseccfgh_sz_acc_op | |||||||||||||||||||||||||||||||
| mseccfgh_op | When XLEN=32 only, mseccfgh is a 32-bit read/write register that aliases bits 63:32 of mseccfg. |
norm:mseccfgh_sz_acc_op | |||||||||||||||||||||||||||||||
| mseccfgh_presence | Register mseccfgh exists when XLEN=32 and mseccfg is implemented; it does not exist when XLEN=64. |
norm:mseccfgh_presence | |||||||||||||||||||||||||||||||
| mtime_acc | Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, mtime. |
norm:mtime_acc | |||||||||||||||||||||||||||||||
| mtime_op | mtime must increment at constant frequency | norm:mtime_op | |||||||||||||||||||||||||||||||
| MTIME_TICK_PERIOD | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| the platform must provide a mechanism for determining the period of an mtime tick. |
norm:mtime_tick_period | ||||||||||||||||||||||||||||||||
| mtime_wrap | The mtime register will wrap around if the count overflows. | norm:mtime_wrap | |||||||||||||||||||||||||||||||
| mtime_sz | The mtime register has a 64-bit precision on all RV32 and RV64 systems. | norm:mtime_sz | |||||||||||||||||||||||||||||||
| mtime_intr_pending | A machine timer interrupt becomes pending whenever mtime contains a value greater than or equal to mtimecmp, treating the values as unsigned integers. The interrupt remains posted until mtimecmp becomes greater than mtime |
norm:mtime_intr_pending | |||||||||||||||||||||||||||||||
| mtime_intr_taken | The interrupt will only be taken if interrupts are enabled and the MTIE bit is set in the mie register. |
norm:mtime_intr_taken | |||||||||||||||||||||||||||||||
| mtime_intr_mtip_visibility | If the result of the comparison between mtime and mtimecmp changes, it is guaranteed to be reflected in MTIP eventually, but not necessarily immediately. |
norm:mtime_intr_mtip_visibility | |||||||||||||||||||||||||||||||
| mtime_enc | (No text available) | norm:mtime_enc_img | |||||||||||||||||||||||||||||||
| mtime_rv64_wr | For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are additionally supported and are atomic. |
norm:mtime_mtimecmp_rv64_wr | |||||||||||||||||||||||||||||||
| mtimecmp_sz | Platforms provide a 64-bit memory-mapped machine-mode timer compare register (mtimecmp). |
norm:mtimecmp_sz | |||||||||||||||||||||||||||||||
| mtimecmp_enc | (No text available) | norm:mtimecmp_enc_img | |||||||||||||||||||||||||||||||
| mtimecmp_rv32_wr | In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part of the register. |
norm:mtimecmp_rv32_wr | |||||||||||||||||||||||||||||||
| mtimecmp_rv64_wr | For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are additionally supported and are atomic. |
norm:mtime_mtimecmp_rv64_wr | |||||||||||||||||||||||||||||||
| ecall_epc_value | ECALL and EBREAK cause the receiving privilege mode’s epc register to be set to the address of the ECALL or EBREAK instruction itself, not the address of the following instruction. |
norm:ecall_ebreak_epc_value | |||||||||||||||||||||||||||||||
| ebreak_epc_value | ECALL and EBREAK cause the receiving privilege mode’s epc register to be set to the address of the ECALL or EBREAK instruction itself, not the address of the following instruction. |
norm:ecall_ebreak_epc_value | |||||||||||||||||||||||||||||||
| ecall_no_minstret_inc | As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the minstret CSR. |
norm:ecall_ebreak_no_minstret_inc | |||||||||||||||||||||||||||||||
| ebreak_no_minstret_inc | As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the minstret CSR. |
norm:ecall_ebreak_no_minstret_inc | |||||||||||||||||||||||||||||||
| mret_enc | (No text available) | norm:xret_enc_img | |||||||||||||||||||||||||||||||
| sret_enc | (No text available) | norm:xret_enc_img | |||||||||||||||||||||||||||||||
| mret_presence | MRET is always provided. | norm:mret_presence | |||||||||||||||||||||||||||||||
| sret_presence | SRET must be provided if supervisor mode is supported, and should raise an illegal-instruction exception otherwise. |
norm:sret_presence | |||||||||||||||||||||||||||||||
| sret_ill_inst_exc_rst | SRET should also raise an illegal-instruction exception when TSR=1 in mstatus, as described in virt-control. |
norm:sret_ill_inst_exc_rst | |||||||||||||||||||||||||||||||
| sret_in_M_mode | An xRET instruction can be executed in privilege mode x or higher, where executing a lower-privilege xRET instruction will pop the relevant lower-privilege interrupt enable and privilege mode stack. |
norm:xret_in_higher_mode | |||||||||||||||||||||||||||||||
| mret_in_S_mode | Attempting to execute an xRET instruction in a mode less privileged than x will raise an illegal-instruction exception. |
norm:xret_in_lower_mode | |||||||||||||||||||||||||||||||
| mret_in_U_mode | Attempting to execute an xRET instruction in a mode less privileged than x will raise an illegal-instruction exception. |
norm:xret_in_lower_mode | |||||||||||||||||||||||||||||||
| sret_in_U_mode | Attempting to execute an xRET instruction in a mode less privileged than x will raise an illegal-instruction exception. |
norm:xret_in_lower_mode | |||||||||||||||||||||||||||||||
| mret_op | In addition to manipulating the privilege stack as described in privstack, xRET sets the pc to the value stored in the xepc register. |
norm:xret_op | |||||||||||||||||||||||||||||||
| sret_op | In addition to manipulating the privilege stack as described in privstack, xRET sets the pc to the value stored in the xepc register. |
norm:xret_op | |||||||||||||||||||||||||||||||
| MRET_CLR_LR_RESV | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If the A extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to. |
norm:xret_clr_lr_resv | ||||||||||||||||||||||||||||||||
| SRET_CLR_LR_RESV | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| If the A extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to. |
norm:xret_clr_lr_resv | ||||||||||||||||||||||||||||||||
| wfi_op | The Wait for Interrupt instruction (WFI) informs the implementation that the current hart can be stalled until an interrupt might need servicing. Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart. |
norm:wfi_op | |||||||||||||||||||||||||||||||
| wfi_enc | (No text available) | norm:wfi_enc_img | |||||||||||||||||||||||||||||||
| wfi_all_privileged_modes | WFI is available in all privileged modes | norm:wfi_all_privileged_modes | |||||||||||||||||||||||||||||||
| WFI_OPT_U_MODE | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| optionally available to U-mode. | norm:wfi_opt_U_mode | ||||||||||||||||||||||||||||||||
| wfi_ill_exc | This instruction may raise an illegal-instruction exception when TW=1 in mstatus, as described in virt-control. |
norm:wfi_ill_exc | |||||||||||||||||||||||||||||||
| wfi_mepc_val | If an enabled interrupt is present or later becomes present while the hart is stalled, the interrupt trap will be taken on the following instruction, i.e., execution resumes in the trap handler and mepc = pc + 4. |
norm:wfi_mepc_val | |||||||||||||||||||||||||||||||
| WFI_RESUME_REASON | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Implementations are permitted to resume execution for any reason, even if an enabled interrupt has not become pending. Hence, a legal implementation is to simply implement the WFI instruction as a NOP. |
norm:wfi_resume_reason | ||||||||||||||||||||||||||||||||
| wfi_intr_dis | The WFI instruction can also be executed when interrupts are disabled. | norm:wfi_intr_dis | |||||||||||||||||||||||||||||||
| wfi_unaffected_conditions | The operation of WFI must be unaffected by the global interrupt bits in mstatus (MIE and SIE) and the delegation register mideleg (i.e., the hart must resume if a locally enabled interrupt becomes pending, even if it has been delegated to a less-privileged mode), but should honor the individual interrupt enables (e.g, MTIE) (i.e., implementations should avoid resuming the hart if the interrupt is pending but not individually enabled). WFI is also required to resume execution for locally enabled interrupts pending at any privilege level, regardless of the global interrupt enable at each privilege level. |
norm:wfi_unaffected_conditions | |||||||||||||||||||||||||||||||
| wfi_no_intr_pc | If the event that causes the hart to resume execution does not cause an interrupt to be taken, execution will resume at pc + 4 |
norm:wfi_no_intr_pc | |||||||||||||||||||||||||||||||
| M_mode_at_rst | M-mode is used for low-level access to a hardware platform and is the first mode entered at reset. |
norm:M-mode_at_rst1 | |||||||||||||||||||||||||||||||
| Upon reset, a hart’s privilege mode is set to M. | norm:M-mode_at_rst2 | ||||||||||||||||||||||||||||||||
| ld_rsv_rst | For implementations with the "A" standard extension, there is no valid load reservation. |
norm:ld_rsv_rst | |||||||||||||||||||||||||||||||
| pc_rst | The pc is set to an implementation-defined reset vector. | norm:pc_rst | |||||||||||||||||||||||||||||||
| MCAUSE_RST_VAL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The mcause register is set to a value indicating the cause of the reset. | norm:mcause_rst1_val | ||||||||||||||||||||||||||||||||
| The mcause values after reset have implementation-specific interpretation |
norm:mcause_rst2_val | ||||||||||||||||||||||||||||||||
| mcause_rst_zero | the value 0 should be returned on implementations that do not distinguish different reset conditions. Implementations that distinguish different reset conditions should only use 0 to indicate the most complete reset. |
norm:mcause_rst_zero | |||||||||||||||||||||||||||||||
| PMP_A_L_RST | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers’ A and L fields. |
norm:pmp_A_L_rst | ||||||||||||||||||||||||||||||||
| hgatp_vsatp_mode_rst | If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE fields are reset to 0. |
norm:hgatp_vsatp_mode_rst | |||||||||||||||||||||||||||||||
| mnstatus_nmie_rst | If the Smrnmi extension is implemented, the mnstatus.NMIE field is reset to 0. | norm:mnstatus_nmie_rst | |||||||||||||||||||||||||||||||
| WARL_RST | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| No WARL field contains an illegal value. | norm:warl_rst | ||||||||||||||||||||||||||||||||
| mseccfg_mlpe_rst | If the Zicfilp extension is implemented, the mseccfg.MLPE field is reset to 0. | norm:mseccfg_mlpe_rst | |||||||||||||||||||||||||||||||
| MSECCFG_MML_MMWP_RLB_RST | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The MML, MMWP, and RLB fields of the mseccfg register are set to 0, unless the platform mandates a different reset value. |
norm:mseccfg_mml_mmwp_rlb_rst | ||||||||||||||||||||||||||||||||
| MSECCFG_USEED_SSEED_RST | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The USEED and SSEED fields of the mseccfg CSR must have defined reset values. The system must not allow them to be in an undefined state after reset. |
norm:mseccfg_useed_sseed_rst | ||||||||||||||||||||||||||||||||
| MCAUSE_RST_ALIAS_OK | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| mcause reset values may alias mcause values following synchronous exceptions |
norm:mcause_rst_alias_ok | ||||||||||||||||||||||||||||||||
| pma_indep_exec_context | PMAs do not vary by execution context. |
norm:pma_indep_exec_context | |||||||||||||||||||||||||||||||
| pma_rtcfg_mmr | Where the attributes are run-time configurable, platform-specific memory-mapped control registers can be provided |
norm:pma_rtcfg_mmr | |||||||||||||||||||||||||||||||
| pma_chk_paddr | PMAs are checked for any access to physical memory, including accesses that have undergone virtual to physical memory translation. |
norm:pma_chk_paddr | |||||||||||||||||||||||||||||||
| pma_precise_recom | we strongly recommend that, where possible, RISC-V processors precisely trap physical memory accesses that fail PMA checks. Precisely trapped PMA violations manifest as instruction, load, or store access-fault exceptions, distinct from virtual-memory page-fault exceptions. |
norm:pma_precise_recom | |||||||||||||||||||||||||||||||
| pma_imprecise_ok | Precise PMA traps might not always be possible, for example, when probing a legacy bus architecture that uses access failures as part of the discovery mechanism. In this case, error responses from peripheral devices will be reported as imprecise bus-error interrupts. |
norm:pma_imprecise_ok | |||||||||||||||||||||||||||||||
| pma_mm_vs_io_def | The most important characterization of a given memory address range is whether it holds regular main memory or I/O devices. Regular main memory is required to have a number of properties, specified below, whereas I/O devices can have a much broader range of attributes. Memory regions that do not fit into regular main memory, for example, device scratchpad RAMs, are categorized as I/O regions. | norm:pma_mm_vs_io_def | |||||||||||||||||||||||||||||||
| pma_mm_rw | Main memory regions always support read and write of all access widths required by the attached devices |
norm:pma_mm_rw | |||||||||||||||||||||||||||||||
| PMA_MM_IFETCH | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| [CONTEXT] Main memory regions always support read and write of all access widths required by the attached devices |
norm:pma_mm_rw | ||||||||||||||||||||||||||||||||
| can specify whether instruction fetch is supported. | norm:pma_mm_ifetch | ||||||||||||||||||||||||||||||||
| pma_mm_mandatory_sz | the design of a processor or device accessing main memory might support other widths, but must be able to function with the types supported by the main memory. |
norm:pma_mm_mandatory_sz | |||||||||||||||||||||||||||||||
| pma_io_rwx_per_sz | I/O regions can specify which combinations of read, write, or execute accesses to which data widths are supported. |
norm:pma_io_rwx_per_sz | |||||||||||||||||||||||||||||||
| pma_vm_hw_tbl_acc | For systems with page-based virtual memory, I/O and memory regions can specify which combinations of hardware page-table reads and hardware page-table writes are supported. |
norm:pma_vm_hw_tbl_acc | |||||||||||||||||||||||||||||||
| PMA_CACHE_MM_ALL_ATOMICS | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Some platforms might mandate that all of cacheable main memory support all atomic operations |
norm:pma_cache_mm_all_atomics | ||||||||||||||||||||||||||||||||
| pma_amo_levels | Within AMOs, there are four levels of support: AMONone, AMOSwap, AMOLogical, and AMOArithmetic. AMONone indicates that no AMO operations are supported. AMOSwap indicates that only amoswap instructions are supported in this address range. AMOLogical indicates that swap instructions plus all the logical AMOs (amoand, amoor, amoxor) are supported. AMOArithmetic indicates that all RISC-V AMOs defined by the A extension are supported. |
norm:pma_amo_levels | |||||||||||||||||||||||||||||||
| pma_amo_sz_support | For each level of support, naturally aligned AMOs of a given width are supported if the underlying memory region supports reads and writes of that width. |
norm:pma_amo_sz_support | |||||||||||||||||||||||||||||||
| pma_amo_far_subset_proc | Main memory and I/O regions may only support a subset or none of the processor-supported atomic operations. | norm:pma_amo_far_subset_proc | |||||||||||||||||||||||||||||||
| pma_amo_zacas_levels | The Zacas extension defines three additional levels of support: AMOCASW, AMOCASD, and AMOCASQ. |
norm:pma_amo_zacas_levels1 | |||||||||||||||||||||||||||||||
| AMOCASW indicates that in addition to instructions indicated by AMOArithmetic level support, the AMOCAS.W instruction is supported. AMOCASD indicates that in addition to instructions indicated by AMOCASW level support, the AMOCAS.D instruction is supported. AMOCASQ indicates that in addition to instructions indicated by AMOCASD level support, the AMOCAS.Q instruction is supported. |
norm:pma_amo_zacas_levels2 | ||||||||||||||||||||||||||||||||
| pma_amo_zacas_req_arith | AMOCASW/D/Q require AMOArithmetic level support as the AMOCAS.W/D/Q instructions require ability to perform an arithmetic comparison and a swap operation. |
norm:pma_amo_zacas_req_arith | |||||||||||||||||||||||||||||||
| pma_amo_zabha_req | The AMOs specified by the Zabha extension require the same level of support as the corresponding instructions in the A standard extension or the Zacas extension. |
norm:pma_amo_zabha_req | |||||||||||||||||||||||||||||||
| pma_rsrv_levels | For LR/SC, there are three levels of support indicating combinations of the reservability and eventuality properties: RsrvNone, RsrvNonEventual, and RsrvEventual. RsrvNone indicates that no LR/SC operations are supported (the location is non-reservable). RsrvNonEventual indicates that the operations are supported (the location is reservable), but without the eventual success guarantee described in the unprivileged ISA specification. RsrvEventual indicates that the operations are supported and provide the eventual success guarantee. |
norm:pma_rsrv_levels | |||||||||||||||||||||||||||||||
| pma_mag_def | The misaligned atomicity granule PMA provides constrained support for misaligned AMOs. This PMA, if present, specifies the size of a misaligned atomicity granule, a naturally aligned power-of-two number of bytes. Specific supported values for this PMA are represented by MAGNN, e.g., MAG16 indicates the misaligned atomicity granule is at least 16 bytes. | norm:pma_mag_def | |||||||||||||||||||||||||||||||
| pma_mag_insts | The misaligned atomicity granule PMA applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions, and compressed encodings thereof. |
norm:pma_mag_insts | |||||||||||||||||||||||||||||||
| pma_mag_op_within | if all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO--i.e., it will execute atomically. |
norm:pma_mag_op_within | |||||||||||||||||||||||||||||||
| pma_mag_op_amo | If a misaligned AMO accesses a region that does not specify a misaligned atomicity granule PMA, or if not all accessed bytes lie within the same misaligned atomicity granule, then an exception is raised. |
norm:pma_mag_op_amo | |||||||||||||||||||||||||||||||
| PMA_MAG_OP_LDST | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| [CONTEXT] If a misaligned AMO accesses a region that does not specify a misaligned atomicity granule PMA, or if not all accessed bytes lie within the same misaligned atomicity granule, then an exception is raised. |
norm:pma_mag_op_amo | ||||||||||||||||||||||||||||||||
| For regular loads and stores that access such a region or for which not all accessed bytes lie within the same atomicity granule, then either an exception is raised, or the access proceeds but is not guaranteed to be atomic. |
norm:pma_mag_op_ldst | ||||||||||||||||||||||||||||||||
| PMA_MAG_EXC | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Implementations may raise access-fault exceptions instead of address-misaligned exceptions for some misaligned accesses, indicating the instruction should not be emulated by a trap handler. |
norm:pma_mag_exc | ||||||||||||||||||||||||||||||||
| pma_mag_op_rsrv | LR/SC instructions are unaffected by this PMA and so always raise an exception when misaligned. |
norm:pma_mag_op_rsrv | |||||||||||||||||||||||||||||||
| pma_mag_op_vec | Vector memory accesses are also unaffected, so might execute non-atomically even when contained within a misaligned atomicity granule. |
norm:pma_mag_op_vec | |||||||||||||||||||||||||||||||
| pma_mag_op_implicit | Implicit accesses are similarly unaffected by this PMA. | norm:pma_mag_op_implicit | |||||||||||||||||||||||||||||||
| pma_mo_io_chan_0 | [CONTEXT] Each strongly ordered I/O region specifies a numbered ordering channel, which is a mechanism by which ordering guarantees can be provided between different I/O regions. |
norm:pma_mo_io_chan_def | |||||||||||||||||||||||||||||||
| Channel 0 is used to indicate point-to-point strong ordering only, where only accesses by the hart to the single associated I/O region are strongly ordered. |
norm:pma_mo_io_chan_0 | ||||||||||||||||||||||||||||||||
| pma_mo_io_chan_1 | [CONTEXT] Each strongly ordered I/O region specifies a numbered ordering channel, which is a mechanism by which ordering guarantees can be provided between different I/O regions. |
norm:pma_mo_io_chan_def | |||||||||||||||||||||||||||||||
| Channel 1 is used to provide global strong ordering across all I/O regions. Any accesses by a hart to any I/O region associated with channel 1 can only be observed to have occurred in program order by all other harts and I/O devices, including relative to accesses made by that hart to relaxed I/O regions or strongly ordered I/O regions with different channel numbers. In other words, any access to a region in channel 1 is equivalent to executing a fence io,io instruction before and after the instruction. | norm:pma_mo_io_chan_1 | ||||||||||||||||||||||||||||||||
| pma_mo_io_chan_other | [CONTEXT] Each strongly ordered I/O region specifies a numbered ordering channel, which is a mechanism by which ordering guarantees can be provided between different I/O regions. |
norm:pma_mo_io_chan_def | |||||||||||||||||||||||||||||||
| Other larger channel numbers provide program ordering to accesses by that hart across any regions with the same channel number | norm:pma_mo_io_chan_other | ||||||||||||||||||||||||||||||||
| PMA_MO_DYN | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Systems might support dynamic configuration of ordering properties on each memory region. | norm:pma_mo_dyn | ||||||||||||||||||||||||||||||||
| pma_non_cacheable | If a PMA indicates non-cacheability, then accesses to that region must be satisfied by the memory itself, not by any caches. |
norm:pma_non_cacheable | |||||||||||||||||||||||||||||||
| pma_idp_mm | Main memory regions are assumed to be idempotent. | norm:pma_idp_mm | |||||||||||||||||||||||||||||||
| pma_idp_no_spec | hardware should always be designed to avoid speculative or redundant accesses to memory regions marked as non-idempotent |
norm:pma_idp_no_spec | |||||||||||||||||||||||||||||||
| pma_idp_misaligned_exc | Non-idempotent regions might not support misaligned accesses. Misaligned accesses to such regions should raise access-fault exceptions rather than address-misaligned exceptions |
norm:pma_idp_misaligned_exc | |||||||||||||||||||||||||||||||
| pma_idp_implicit_ok | For non-idempotent regions, implicit reads and writes must not be performed early or speculatively, with the following exceptions. When a non-speculative implicit read is performed, an implementation is permitted to additionally read any of the bytes within a naturally aligned power-of-2 region containing the address of the non-speculative implicit read. Furthermore, when a non-speculative instruction fetch is performed, an implementation is permitted to additionally read any of the bytes within the next naturally aligned power-of-2 region of the same size (with the address of the region taken modulo 2XLEN). |
norm:pma_idp_implicit_ok | |||||||||||||||||||||||||||||||
| PMA_IDP_IMPLICIT_SZ | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| [CONTEXT] For non-idempotent regions, implicit reads and writes must not be performed early or speculatively, with the following exceptions. When a non-speculative implicit read is performed, an implementation is permitted to additionally read any of the bytes within a naturally aligned power-of-2 region containing the address of the non-speculative implicit read. Furthermore, when a non-speculative instruction fetch is performed, an implementation is permitted to additionally read any of the bytes within the next naturally aligned power-of-2 region of the same size (with the address of the region taken modulo 2XLEN). |
norm:pma_idp_implicit_ok | ||||||||||||||||||||||||||||||||
| The size of these naturally aligned power-of-2 regions is implementation-defined, but, for systems with page-based virtual memory, must not exceed the smallest supported page size. |
norm:pma_idp_implicit_sz | ||||||||||||||||||||||||||||||||
| trap_exp | When a trap is to be taken into M-mode, if the MDT bit is currently 0, it is then set to 1, and the trap is delivered as expected. | norm:trap_exp | |||||||||||||||||||||||||||||||
| trap_unexp | When a trap is to be taken into M-mode, if the MDT bit is currently 0, it is then set to 1, and the trap is delivered as expected. | norm:trap_exp | |||||||||||||||||||||||||||||||
| However, if MDT is already set to 1, then this is an unexpected trap. | norm:trap_unexp_mdt_1 | ||||||||||||||||||||||||||||||||
| trap_unexp_rnmi | When the Smrnmi extension is implemented, a trap caused by an RNMI is not considered an unexpected trap irrespective of the state of the MDT bit. |
norm:trap_unexp_rnmi | |||||||||||||||||||||||||||||||
| trap_unexp_mnstatus_nmie_0 | a trap that occurs when executing in M-mode with mnstatus.NMIE set to 0 is an unexpected trap. |
norm:trap_unexp_mnstatus_nmie_0 | |||||||||||||||||||||||||||||||
| trap_unexp_hndl_rnmi | In the event of a unexpected trap, the handling is as follows: | norm:trap_unexp_hndl_lead-in | |||||||||||||||||||||||||||||||
| When the Smrnmi extension is implemented and mnstatus.NMIE is 1, the hart traps to the RNMI handler. To deliver this trap, the mnepc and mncause registers are written with the values that the unexpected trap would have written to the mepc and mcause registers respectively. The privilege mode information fields in the mnstatus register are written to indicate M-mode and its NMIE field is set to 0. |
norm:trap_unexp_hndl_rnmi | ||||||||||||||||||||||||||||||||
| trap_unexp_hndl_no_rnmi | In the event of a unexpected trap, the handling is as follows: | norm:trap_unexp_hndl_lead-in | |||||||||||||||||||||||||||||||
| When the Smrnmi extension is not implemented, or if the Smrnmi extension is implemented and mnstatus.NMIE is 0, the hart enters a critical-error state without updating any architectural state, including the pc. This state involves ceasing execution, disabling all interrupts (including NMIs), and asserting a critical-error signal to the platform. |
norm:trap_unexp_hndl_no_rnmi | ||||||||||||||||||||||||||||||||
| CRITICAL_ERROR | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The actions performed by the platform when a hart asserts a critical-error signal are platform-specific. The range of possible actions include restarting the affected hart or restarting the entire platform, among others. |
norm:critical_error | ||||||||||||||||||||||||||||||||
| trap_def_M_mode | By default, all traps at any privilege level are handled in machine mode |
norm:trap_def_M_mode | |||||||||||||||||||||||||||||||
| trap_del_S_mode_op | [CONTEXT] When a trap is delegated to S-mode | norm:trap_del_S-mode | |||||||||||||||||||||||||||||||
| the scause register is written with the trap cause; the sepc register is written with the virtual address of the instruction that took the trap; the stval register is written with an exception-specific datum; the SPP field of mstatus is written with the active privilege mode at the time of the trap; the SPIE field of mstatus is written with the value of the SIE field at the time of the trap; and the SIE field of mstatus is cleared. |
norm:trap_del_S_mode_op | ||||||||||||||||||||||||||||||||
| trap_del_S_mode_no_M_mode | [CONTEXT] When a trap is delegated to S-mode | norm:trap_del_S-mode | |||||||||||||||||||||||||||||||
| The mcause, mepc, and mtval registers and the MPP and MPIE fields of mstatus are not written. |
norm:trap_del_S_mode_no_M_mode | ||||||||||||||||||||||||||||||||
| trap_never_trans_lower | Traps never transition from a more-privileged mode to a less-privileged mode. For example, if M-mode has delegated illegal-instruction exceptions to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode. |
norm:trap_never_trans_lower | |||||||||||||||||||||||||||||||
| trap_horiz | traps may be taken horizontally. Using the same example, if M-mode has delegated illegal-instruction exceptions to S-mode, and S-mode software later executes an illegal instruction, the trap is taken in S-mode. |
norm:trap_horiz | |||||||||||||||||||||||||||||||
| trap_del_intr_priv_lvl | Delegated interrupts result in the interrupt being masked at the delegator privilege level. For example, if the supervisor timer interrupt (STI) is delegated to S-mode by setting mideleg[5], STIs will not be taken when executing in M-mode. By contrast, if mideleg[5] is clear, STIs can be taken in any mode and regardless of current mode will transfer control to M-mode. |
norm:trap_del_intr_priv_lvl | |||||||||||||||||||||||||||||||
| exc_priority |
|
norm:exc_priority | |||||||||||||||||||||||||||||||
| intr_mip_mie_op | An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg. |
norm:intr_mip_mie_op | |||||||||||||||||||||||||||||||
| intr_mip_mie_bounded_time | [CONTEXT] An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg. |
norm:intr_mip_mie_op | |||||||||||||||||||||||||||||||
| These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in mip, |
norm:intr_mip_mie_bounded_time | ||||||||||||||||||||||||||||||||
| intr_mip_mie_xret_csrwr | [CONTEXT] An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg. |
norm:intr_mip_mie_op | |||||||||||||||||||||||||||||||
| be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including mip, mie, mstatus, and mideleg). |
norm:intr_mip_mie_xret_csrwr | ||||||||||||||||||||||||||||||||
| intr_M_mode_highest_pri | Interrupts to M-mode take priority over any interrupts to lower privilege modes. | norm:intr_M_mode_highest_pri | |||||||||||||||||||||||||||||||
| intr_sei_op | Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller. |
norm:intr_sei_op | |||||||||||||||||||||||||||||||
| intr_M_mode_pri | Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI. |
norm:intr_M_mode_pri | |||||||||||||||||||||||||||||||
| nmi_op | cause an immediate jump to an implementation-defined NMI vector running in M-mode regardless of the state of a hart’s interrupt enable bits. The mepc register is written with the virtual address of the instruction that was interrupted, |
norm:nmi_op | |||||||||||||||||||||||||||||||
| NMI_MCAUSE_VAL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| mcause is set to a value indicating the source of the NMI. |
norm:nmi_mcause_val1 | ||||||||||||||||||||||||||||||||
| The values written to mcause on an NMI are implementation-defined. | norm:nmi_mcause_val2 | ||||||||||||||||||||||||||||||||
| nmi_mcause_restrictions | The high Interrupt bit of mcause should be set to indicate that this was an interrupt. An Exception Code of 0 is reserved to mean "unknown cause" and implementations that do not distinguish sources of NMIs via the mcause register should return 0 in the Exception Code. |
norm:nmi_mcause_restrictions | |||||||||||||||||||||||||||||||
| nmi_no_rst | NMIs do not reset processor state | norm:nmi_no_rst | |||||||||||||||||||||||||||||||
| SXLEN | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively. | norm:sxlen_uxlen | ||||||||||||||||||||||||||||||||
| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | ||||||||||||||||||||||||||||||||
| UXLEN | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively. | norm:sxlen_uxlen | ||||||||||||||||||||||||||||||||
| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | ||||||||||||||||||||||||||||||||
| xlen_reduction_op | Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register. Similarly, pc bits above XLEN are ignored, and when the pc is written, it is sign-extended to fill the widest supported XLEN. | norm:xlen_reduction_op | |||||||||||||||||||||||||||||||
| XLEN_REDUCTION_HINT_OP | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., c.addi x8, 0. When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits MXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1. | norm:xlen_reduction_hint_op1 | ||||||||||||||||||||||||||||||||
| This definition allows implementations to elide register write-back for some HINTs, while allowing them to execute other HINTs in the same manner as other integer computational instructions. The implementation choice is observable only by privilege modes with an XLEN setting greater than the current XLEN; it is invisible to the current privilege mode. |
norm:xlen_reduction_hint_op2 | ||||||||||||||||||||||||||||||||
| endianness_inst_fetch_little | Instruction fetches are always little-endian. | norm:endianness_inst_fetch_little | |||||||||||||||||||||||||||||||
| RST_ADDR | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Reset and NMI vector locations are given in a platform specification. | norm:rst_and_nmi_addr | ||||||||||||||||||||||||||||||||
| NMI_ADDR | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Reset and NMI vector locations are given in a platform specification. | norm:rst_and_nmi_addr | ||||||||||||||||||||||||||||||||
| uncached_ignores_cached | For implementations with a cacheability-control mechanism, the situation may arise that a program uncacheably accesses a memory location that is currently cache-resident. In this situation, the cached copy must be ignored. This constraint is necessary to prevent more-privileged modes’ speculative cache refills from affecting the behavior of less-privileged modes’ uncacheable accesses. |
norm:uncached_ignores_cached | |||||||||||||||||||||||||||||||
| PMP_GRANULARITY | Minimum PMP region granularity supported by the platform | Rule's "summary" property | |||||||||||||||||||||||||||||||
| extension | Rule's "kind" property | ||||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| The granularity of PMP access control settings are platform-specific, but the standard PMP encoding supports regions as small as four bytes. |
norm:pmp_granularity | ||||||||||||||||||||||||||||||||
| pmp_mmode_only_regions | Certain regions’ privileges can be hardwired—for example, some regions might only ever be visible in machine mode but in no lower-privilege layers. |
norm:pmp_mmode_only_regions | |||||||||||||||||||||||||||||||
| pmp_check_priv_modes | PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches and data accesses in S and U mode, and data accesses in M-mode when the MPRV bit in mstatus is set and the MPP field in mstatus contains S or U. |
norm:pmp_check_priv_modes | |||||||||||||||||||||||||||||||
| pmp_check_pagetable_access | PMP checks are also applied to page-table accesses for virtual-address translation, for which the effective privilege mode is S. |
norm:pmp_check_pagetable_access | |||||||||||||||||||||||||||||||
| pmp_mmode_locking | Optionally, PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset. |
norm:pmp_mmode_locking | |||||||||||||||||||||||||||||||
| pmp_violation_precise_trap | PMP violations are always trapped precisely at the processor. | norm:pmp_violation_precise_trap | |||||||||||||||||||||||||||||||
| pmp_entry_structure | PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. |
norm:pmp_entry_structure | |||||||||||||||||||||||||||||||
| pmp_csr_mode | PMP CSRs are only accessible to M-mode. |
norm:pmp_csr_mode | |||||||||||||||||||||||||||||||
| PMP_ENTRY_COUNT | PMP supports up to 64 entries with allowed implementation counts and ordering rules | Rule's "summary" property | |||||||||||||||||||||||||||||||
| extension | Rule's "kind" property | ||||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| Up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first. |
norm:pmp_entry_count | ||||||||||||||||||||||||||||||||
| PMP_CSRS_WARL_ACCESS | PMP CSRs are WARL, may read as zero, and are accessible only in M-mode | Rule's "summary" property | |||||||||||||||||||||||||||||||
| extension | Rule's "kind" property | ||||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| All PMP CSR fields are WARL and may be read-only zero. |
norm:pmp_csrs_warl_access | ||||||||||||||||||||||||||||||||
| pmp_cfg_rv32_layout | RV32 PMP configuration CSRs layout and mapping | Rule's "summary" property | |||||||||||||||||||||||||||||||
| For RV32, sixteen CSRs, pmpcfg0–pmpcfg15, hold the configurations pmp0cfg–pmp63cfg for the 64 PMP entries, as shown in pmpcfg-rv32. |
norm:pmp_cfg_rv32_layout | ||||||||||||||||||||||||||||||||
| pmp_cfg_rv64_layout | RV64 PMP configuration CSRs layout using even-numbered CSRs | Rule's "summary" property | |||||||||||||||||||||||||||||||
| For RV64, eight even-numbered CSRs, pmpcfg0, pmpcfg2, …, pmpcfg14, hold the configurations for the 64 PMP entries, as shown in pmpcfg-rv64. |
norm:pmp_cfg_rv64_layout | ||||||||||||||||||||||||||||||||
| pmp_cfg_rv64_illegal | Odd-numbered PMP configuration CSRs are illegal in RV64 | Rule's "summary" property | |||||||||||||||||||||||||||||||
| For RV64, the odd-numbered configuration registers, pmpcfg1, pmpcfg3, …, pmpcfg15, are illegal. |
norm:pmp_cfg_rv64_illegal | ||||||||||||||||||||||||||||||||
| pmp_addr_registers | PMP address registers are named pmpaddr0 through pmpaddr63 | Rule's "summary" property | |||||||||||||||||||||||||||||||
| The PMP address registers are CSRs named pmpaddr0-pmpaddr63. | norm:pmp_addr_registers | ||||||||||||||||||||||||||||||||
| pmp_addr_encoding | PMP address registers encode physical address bits depending on XLEN | Rule's "summary" property | |||||||||||||||||||||||||||||||
| Each PMP address register encodes bits 33-2 of a 34-bit physical address for RV32, as shown in pmpaddr-rv32. For RV64, each PMP address register encodes bits 55-2 of a 56-bit physical address, as shown in pmpaddr-rv64. |
norm:pmp_addr_encoding | ||||||||||||||||||||||||||||||||
| PMP_ADDR_WARL | PMP address registers are WARL due to optional physical address bits | Rule's "summary" property | |||||||||||||||||||||||||||||||
| extension | Rule's "kind" property | ||||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| Not all physical address bits may be implemented, and so the pmpaddr registers are WARL. |
norm:pmp_addr_warl | ||||||||||||||||||||||||||||||||
| pmp_cfg_permissions | PMP R, W, and X bits control read, write, and execute permissions | Rule's "summary" property | |||||||||||||||||||||||||||||||
| pmpcfg shows the layout of a PMP configuration register. The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively. When one of these bits is clear, the corresponding access type is denied. |
norm:pmp_cfg_permissions | ||||||||||||||||||||||||||||||||
| PMP_RWX_WARL | extension | Rule's "kind" property | |||||||||||||||||||||||||||||||
| Sm | Rule's "instance" property | ||||||||||||||||||||||||||||||||
| Implementation-defined behavior | Rule's property | ||||||||||||||||||||||||||||||||
| WARL | Implementation-defined behavior category | ||||||||||||||||||||||||||||||||
| The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved. |
norm:pmp_rwx_warl | ||||||||||||||||||||||||||||||||
| pmp_exec_fault | Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception. |
norm:pmp_exec_fault | |||||||||||||||||||||||||||||||
| pmp_load_fault | Attempting to execute a load, load-reserved, or cache-block management instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception. |
norm:pmp_load_fault | |||||||||||||||||||||||||||||||
| pmp_store_fault | Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception. |
norm:pmp_store_fault | |||||||||||||||||||||||||||||||
| pmp_a_field_encoding | The A field in a PMP entry's configuration register encodes the address-matching mode of the associated PMP address register. The encoding of this field is shown in pmpcfg-a. |
norm:pmp_a_field_encoding | |||||||||||||||||||||||||||||||
| pmp_a_field_off | When A=0, this PMP entry is disabled and matches no addresses. | norm:pmp_a_field_off | |||||||||||||||||||||||||||||||
| pmp_a_field_napot_na4 | naturally aligned power-of-2 regions (NAPOT), including the special case of naturally aligned four-byte regions (NA4); |
norm:pmp_a_field_napot_na4 | |||||||||||||||||||||||||||||||
| pmp_a_field_tor | If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range. If PMP entry i's A field is set to TOR, the entry matches any address y such that pmpaddri-1{le}y<pmpaddri (irrespective of the value of pmpcfgi-1). If PMP entry 0's A field is set to TOR, zero is used for the lower bound, and so it matches any address y<pmpaddr0. |
norm:pmp_a_field_tor | |||||||||||||||||||||||||||||||
| pmp_napot_encoding_low_bits | NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range, as shown in pmpcfg-napot. |
norm:pmp_napot_encoding_low_bits | |||||||||||||||||||||||||||||||
| pmp_region_granularity_g | Although the PMP mechanism supports regions as small as four bytes, platforms may specify coarser PMP regions. In general, the PMP grain is 2G+2 bytes and must be the same across all PMP regions. |
norm:pmp_region_granularity_g | |||||||||||||||||||||||||||||||
| pmp_na4_select_restriction | When G {ge} 1, the NA4 mode is not selectable. | norm:pmp_na4_select_restriction | |||||||||||||||||||||||||||||||
| pmp_napot_addr_read_mask | When G {ge} 2 and pmpcfgi.A[1] is set, i.e. the mode is NAPOT, then bits pmpaddri[G-2:0] read as all ones. |
norm:pmp_napot_addr_read_mask | |||||||||||||||||||||||||||||||
| pmp_tor_off_addr_read_mask | When G {ge} 1 and pmpcfgi.A[1] is clear, i.e. the mode is OFF or TOR, then bits pmpaddri[G-1:0] read as all zeros. Bits pmpaddri[G-1:0] do not affect the TOR address-matching logic. |
norm:pmp_tor_off_addr_read_mask | |||||||||||||||||||||||||||||||
| pmp_addr_retention_on_mode_change | Although changing pmpcfgi.A[1] affects the value read from pmpaddri, it does not affect the underlying value stored in that register—in particular, pmpaddri[G-1] retains its original value when pmpcfgi.A is changed from NAPOT to TOR/OFF then back to NAPOT. |
norm:pmp_addr_retention_on_mode_change | |||||||||||||||||||||||||||||||
| pmp_l_bit_function | The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored. |
norm:pmp_l_bit_function | |||||||||||||||||||||||||||||||
| pmp_l_bit_write_protection | If PMP entry i is locked, writes to pmpicfg and pmpaddri are ignored. Additionally, if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored. |
norm:pmp_l_bit_write_protection | |||||||||||||||||||||||||||||||
| pmp_l_bit_m_mode_enforcement | In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are additionally enforced on M-mode accesses. When the L bit is set, these permissions are enforced for all privilege modes. When the L bit is clear, any M-mode access matching the PMP entry will succeed; the R/W/X permissions apply only to S and U modes. |
norm:pmp_l_bit_m_mode_enforcement | |||||||||||||||||||||||||||||||
| pmp_misaligned_access_behavior | On some implementations, misaligned loads, stores, and instruction fetches may be decomposed into multiple memory operations, some of which may succeed before an access-fault exception occurs, as described in the RVWMO specification. PMP checking is performed on each memory operation independently. |
norm:pmp_misaligned_access_behavior | |||||||||||||||||||||||||||||||
| pmp_entry_priority | PMP entries are statically prioritized. The lowest-numbered PMP entry that matches any byte of a memory operation determines whether that operation succeeds or fails. |
norm:pmp_entry_priority | |||||||||||||||||||||||||||||||
| pmp_full_match_required | The matching PMP entry must match all bytes of a memory operation, or the operation fails, irrespective of the L, R, W, and X bits. |
norm:pmp_full_match_required | |||||||||||||||||||||||||||||||
| pmp_rwx_check | If a PMP entry matches all bytes of a memory operation, then the L, R, W, and X bits determine whether the operation succeeds or fails. If the L bit is clear and the privilege mode of the access is M, the operation succeeds. Otherwise, if the L bit is set or the privilege mode of the access is S or U, then the operation succeeds only if the R, W, or X bit corresponding to the access type is set. |
norm:pmp_rwx_check | |||||||||||||||||||||||||||||||
| pmp_no_entry_match | If no PMP entry matches an M-mode memory operation, the operation succeeds. If no PMP entry matches an S-mode or U-mode memory operation, but at least one PMP entry is implemented, the operation fails. |
norm:pmp_no_entry_match | |||||||||||||||||||||||||||||||
| pmp_access_fault_exception | Failed memory operations generate an instruction, load, or store access-fault exception. |
norm:pmp_access_fault_exception | |||||||||||||||||||||||||||||||
| pmp_with_paging | When paging is enabled, instructions that access virtual memory may result in multiple physical-memory accesses, including implicit references to the page tables. The PMP checks apply to all of these accesses. |
norm:pmp_with_paging | |||||||||||||||||||||||||||||||
| pmp_speculative_translations | Implementations with virtual memory are permitted to perform address translations speculatively and earlier than required by an explicit memory access, and are permitted to cache them in address translation cache structures—including possibly caching the identity mappings from effective address to physical address used in Bare translation modes and M-mode. The PMP settings for the resulting physical address may be checked (and possibly cached) at any point between the address translation and the explicit memory access. |
norm:pmp_speculative_translations | |||||||||||||||||||||||||||||||
| pmp_sfence_required | when the PMP settings are modified, M-mode software must synchronize the PMP settings with the virtual memory system and any PMP or address-translation caches. This is accomplished by executing an SFENCE.VMA instruction with rs1=x0 and rs2=x0, after the PMP CSRs are written. |
norm:pmp_sfence_required |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| pm_ignore_upper_bits | RISC-V Pointer Masking (PM) is a feature that, when enabled, causes the CPU to ignore the upper bits of the effective address | norm:pm_ignore_upper_bits |
| pm_all_priv_modes | Such tools can be applied in all privilege modes (U, S, and M). | norm:pm_all_priv_modes |
| pm_tag_check_impl | The tag checks themselves can be implemented in software or hardware. | norm:pm_tag_check_impl |
| pm_ignore_va | The ignore transformation differs depending on whether it applies to a virtual or physical address. For virtual addresses, it replaces the upper PMLEN bits with the sign extension of the PMLEN+1st bit. | norm:pm_ignore_va |
| pm_ignore_pa | When applied to a physical address, including guest-physical addresses (i.e., all cases except when the active satp register's MODE field != Bare), the ignore transformation replaces the upper PMLEN bits with 0. This includes both the case of running in M-mode and running in other privilege modes with Bare address translation mode. | norm:pm_ignore_pa |
| pm_apply_explicit | When pointer masking is enabled, the ignore transformation will be applied to every explicit memory access (e.g., loads/stores, atomics operations, and floating point loads/stores). | norm:pm_apply_explicit |
| pm_not_apply_implicit | The transformation does not apply to implicit accesses such as page-table walks or instruction fetches. | norm:pm_not_apply_implicit |
| pm_deterministic_effect | Pointer masking with the same value of PMLEN always has the same effect for the same type of address (virtual or physical). | norm:pm_deterministic_effect |
| pmlen_supported_values | The current standard only supports PMLEN=XLEN-48 (i.e., PMLEN=16 in RV64) and PMLEN=XLEN-57 (i.e., PMLEN=7 in RV64). | norm:pmlen_supported_values |
| pmlen_future_reserved | A setting has been reserved to potentially support other values of PMLEN in future standards. | norm:pmlen_future_reserved |
| pm_per_mode_control | Pointer masking is controlled separately for different privilege modes. | norm:pm_per_mode_control |
| pm_auto_apply_active_mode | Different privilege modes may have different pointer masking settings active simultaneously and the hardware will automatically apply the pointer masking settings of the currently active privilege mode. | norm:pm_auto_apply_active_mode |
| pm_config_next_higher | A privilege mode's pointer masking setting is configured by bits in configuration registers of the next-higher privilege mode. | norm:pm_config_next_higher |
| pm_mode_only_dependency | the pointer masking setting that is applied only depends on the active privilege mode, not on the address that is being masked. | norm:pm_mode_only_dependency |
| pm_mprv_spvp | MPRV and SPVP affect pointer masking as well, causing the pointer masking settings of the effective privilege mode to be applied. | norm:pm_mprv_spvp |
| pm_mxr_exception | When MXR is in effect at the effective privilege mode where explicit memory access is performed, pointer masking does not apply. | norm:pm_mxr_exception |
| pm_cpu_only | Pointer masking only applies to accesses generated by instructions on the CPU (including CPU extensions such as an FPU). E.g., it does not apply to accesses generated by page-table walks, the IOMMU, or devices. | norm:pm_cpu_only |
| pm_misaligned_equivalence | Misaligned accesses are supported, subject to the same limitations as in the absence of pointer masking. The behavior is identical to applying the pointer masking transformation to every constituent aligned memory access. | norm:pm_misaligned_equivalence |
| pm_no_csr_sw | No pointer masking operations are applied when software reads/writes to CSRs, including those meant to hold addresses. | norm:pm_no_csr_sw |
| pm_warl_unaffected | The implemented WARL width of CSRs is unaffected by pointer masking | norm:pm_warl_unaffected |
| pm_csr_hw_apply | pointer masking, when applicable, is applied for hardware writes to a CSR (e.g., when the hardware writes the transformed address to stval when taking an exception). | norm:pm_csr_hw_apply |
| pm_debug_trigger | Pointer masking is also applied, when applicable, to the memory access address when matching address triggers in debug. | norm:pm_debug_trigger |
| pm_no_trap_vector_mask | on trap delivery (e.g., due to an exception or interrupt), pointer masking will not be applied to the address of the trap handler. | norm:pm_no_trap_vector_mask |
| pm_family_extensions | Pointer masking refers to a number of separate extensions, all of which are privileged. | norm:pm_family_extensions |
| ssnpm_definition | A supervisor-level extension that provides pointer masking for the next lower privilege mode (U-mode), and for VS- and VU-modes if the H extension is present. | norm:ssnpm_definition |
| smnpm_definition | A machine-level extension that provides pointer masking for the next lower privilege mode (S/HS if S-mode is implemented, or U-mode otherwise). | norm:smnpm_definition |
| smmpm_definition | A machine-level extension that provides pointer masking for M-mode. | norm:smmpm_definition |
| sspm_definition | An extension that indicates that there is pointer-masking support available in supervisor mode, with some facility provided in the supervisor execution environment to control pointer masking. | norm:sspm_definition |
| supm_definition | An extension that indicates that there is pointer-masking support available in user mode, with some facility provided in the application execution environment to control pointer masking. | norm:supm_definition |
| pm_rv64_only | Pointer masking only applies to RV64. | norm:pm_rv64_only |
| pm_rv32_illegal | In RV32, trying to enable pointer masking will result in an illegal WARL write and not update the pointer masking configuration bits | norm:pm_rv32_illegal |
| pm_uxl_clear | Setting UXL/SXL/MXL to 1 will clear the corresponding pointer masking configuration bits. | norm:pm_uxl_clear |
| pmlen_mode_depend | the supported values of PMLEN may depend on the effective privilege mode. The current standard only defines PMLEN=XLEN-48 and PMLEN=XLEN-57, | norm:pmlen_mode_depend |
| pmlen_illegal_warl | Trying to enable pointer masking in an unsupported scenario represents an illegal write to the corresponding pointer masking enable bit and follows WARL semantics. | norm:pmlen_illegal_warl |
| Rule Name | Rule Description | Origin of Description | |||||||
|---|---|---|---|---|---|---|---|---|---|
| always_priv_level | At any time, a RISC-V hardware thread (hart) is running at some privilege level encoded as a mode in one or more CSRs (control and status registers). |
norm:always_priv_level | |||||||
| priv_levels | Three RISC-V privilege levels are currently defined | norm:priv_levels-txt | |||||||
|
norm:priv_levels_tbl | ||||||||
| non_priv_exc | attempts to perform operations not permitted by the current privilege mode will cause an exception to be raised. |
norm:non_priv_exc | |||||||
| m_level_highest_priv | The machine level has the highest privileges and is the only mandatory privilege level for a RISC-V hardware platform. |
norm:m-level-high-priv-only-mandatory | |||||||
| m_level_only_mandatory | The machine level has the highest privileges and is the only mandatory privilege level for a RISC-V hardware platform. |
norm:m-level-high-priv-only-mandatory | |||||||
| m_mode_mandatory | All hardware implementations must provide M-mode | norm:m_mode_mandatory | |||||||
| priv_combs | Implementations might provide anywhere from 1 to 3 privilege modes | norm:priv_combs_txt | |||||||
|
norm:priv_combs_tbl |
| Rule Name | Rule Description | Origin of Description | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Q_fpr_regs | The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide |
norm:flen | ||||||||||||||||||||||||||
| The floating-point registers are now extended to hold either a single, double, or quad-precision floating-point value (FLEN=128). |
norm:Q_flen_128 | |||||||||||||||||||||||||||
| fsq_op | New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field. | norm:fsq_flq_op | ||||||||||||||||||||||||||
| flq_op | New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field. | norm:fsq_flq_op | ||||||||||||||||||||||||||
| fsq_atomic_align | FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128. | norm:fsq_flq_atomic_align | ||||||||||||||||||||||||||
| flq_atomic_align | FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128. | norm:fsq_flq_atomic_align | ||||||||||||||||||||||||||
| fsq_bits_maintained | FLQ and FSQ do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fsq_flq_bits_maintained | ||||||||||||||||||||||||||
| flq_bits_maintained | FLQ and FSQ do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fsq_flq_bits_maintained | ||||||||||||||||||||||||||
| fadd-q_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmul-q_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsub-q_op | FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 |
norm:fsub-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fdiv-q_op | FDIV.S performs the single-precision floating-point division of rs1 by rs2 | norm:fdiv-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsqrt-q_op | FSQRT.S computes the square root of rs1 | norm:fsqrt-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmadd-q_op | FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. | norm:fmadd-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmsub-q_op | FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. | norm:fmsub-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmsub-q_op | FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. | norm:fnmsub-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmadd-q_op | FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. | norm:fnmadd-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. | norm:Q_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-w-q_op | FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively |
norm:fcvt-w-q_fcvt-l-q_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-l-q_op | FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively |
norm:fcvt-w-q_fcvt-l-q_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions |
norm:fcvt_long_quad_rv64_only | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-q-w_op | FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number |
norm:fcvt-q-w_fcvt-q-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-q-l_op | FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number |
norm:fcvt-q-w_fcvt-q-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions |
norm:fcvt_long_quad_rv64_only | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-wu-q_op | FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-q_fcvt-lu-q_fcvt-q-wu_fcvt-q-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-lu-q_op | FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-q_fcvt-lu-q_fcvt-q-wu_fcvt-q-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions |
norm:fcvt_long_quad_rv64_only | |||||||||||||||||||||||||||
| The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S |
norm:fcvt_int_double_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-q-wu_op | FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-q_fcvt-lu-q_fcvt-q-wu_fcvt-q-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-q-lu_op | FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-q_fcvt-lu-q_fcvt-q-wu_fcvt-q-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions |
norm:fcvt_long_quad_rv64_only | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-s-q_op | FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively |
norm:fcvt-s-q_fcvt-q-s_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-q-s_op | FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively |
norm:fcvt-s-q_fcvt-q-s_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-d-q_op | FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively |
norm:fcvt-d-q_fcvt-q-d_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-q-d_op | FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively |
norm:fcvt-d-q_fcvt-q-d_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fsgnj-q_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction. | norm:fsgnj-q_fsgnjn-q_fsgnjx-q_op | |||||||||||||||||||||||||||
| fsgnjn-q_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction. | norm:fsgnj-q_fsgnjn-q_fsgnjx-q_op | |||||||||||||||||||||||||||
| fsgnjx-q_op | Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs |
norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction. | norm:fsgnj-q_fsgnjn-q_fsgnjx-q_op | |||||||||||||||||||||||||||
| feq-q_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands. | norm:Q_compare_instrs | |||||||||||||||||||||||||||
| flt-q_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands. | norm:Q_compare_instrs | |||||||||||||||||||||||||||
| fle-q_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands. | norm:Q_compare_instrs | |||||||||||||||||||||||||||
| feq-q_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN |
norm:feq-s_quiet | |||||||||||||||||||||||||||
| The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands. | norm:Q_compare_instrs | |||||||||||||||||||||||||||
| flt-q_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands. | norm:Q_compare_instrs | |||||||||||||||||||||||||||
| fle-q_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands. | norm:Q_compare_instrs | |||||||||||||||||||||||||||
| fclass-q_op | The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags. | norm:fclass-s_op | ||||||||||||||||||||||||||
| The quad-precision floating-point classify instruction, FCLASS.Q, is defined analogously to its double-precision counterpart, but operates on quad-precision operands. | norm:fclass-q_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| lui_enc | LUI | norm:lui_enc |
| auipc_enc | AUIPC | norm:auipc_enc |
| jal_enc | JAL | norm:jal_enc |
| jalr_enc | JALR | norm:jalr_enc |
| beq_enc | BEQ | norm:beq_enc |
| bne_enc | BNE | norm:bne_enc |
| blt_enc | BLT | norm:blt_enc |
| bge_enc | BGE | norm:bge_enc |
| bltu_enc | BLTU | norm:bltu_enc |
| bgeu_enc | BGEU | norm:bgeu_enc |
| lb_enc | LB | norm:lb_enc |
| lh_enc | LH | norm:lh_enc |
| lw_enc | LW | norm:lw_enc |
| lbu_enc | LBU | norm:lbu_enc |
| lhu_enc | LHU | norm:lhu_enc |
| sb_enc | SB | norm:sb_enc |
| sh_enc | SH | norm:sh_enc |
| sw_enc | SW | norm:sw_enc |
| addi_enc | ADDI | norm:addi_enc |
| slti_enc | SLTI | norm:slti_enc |
| sltiu_enc | SLTIU | norm:sltiu_enc |
| xori_enc | XORI | norm:xori_enc |
| ori_enc | ORI | norm:ori_enc |
| andi_enc | ANDI | norm:andi_enc |
| slli_enc | SLLI | norm:slli_enc |
| srli_enc | SRLI | norm:srli_enc |
| srai_enc | SRAI | norm:srai_enc |
| add_enc | ADD | norm:add_enc |
| sub_enc | SUB | norm:sub_enc |
| sll_enc | SLL | norm:sll_enc |
| slt_enc | SLT | norm:slt_enc |
| sltu_enc | SLTU | norm:sltu_enc |
| xor_enc | XOR | norm:xor_enc |
| srl_enc | SRL | norm:srl_enc |
| sra_enc | SRA | norm:sra_enc |
| or_enc | OR | norm:or_enc |
| and_enc | AND | norm:and_enc |
| fence_enc | FENCE | norm:fence_enc |
| fence-tso_enc | FENCE.TSO | norm:fence-tso_enc |
| pause_enc | PAUSE | norm:pause_enc |
| ecall_enc | ECALL | norm:ecall_enc |
| ebreak_enc | EBREAK | norm:ebreak_enc |
| lwu_enc | LWU | norm:lwu_enc |
| ld_enc | LD | norm:ld_enc |
| sd_enc | SD | norm:sd_enc |
| addiw_enc | ADDIW | norm:addiw_enc |
| slliw_enc | SLLIW | norm:slliw_enc |
| srliw_enc | SRLIW | norm:srliw_enc |
| sraiw_enc | SRAIW | norm:sraiw_enc |
| addw_enc | ADDW | norm:addw_enc |
| subw_enc | SUBW | norm:subw_enc |
| sllw_enc | SLLW | norm:sllw_enc |
| srlw_enc | SRLW | norm:srlw_enc |
| sraw_enc | SRAW | norm:sraw_enc |
| mul_enc | MUL | norm:mul_enc |
| mulh_enc | MULH | norm:mulh_enc |
| mulhsu_enc | MULHSU | norm:mulhsu_enc |
| mulhu_enc | MULHU | norm:mulhu_enc |
| div_enc | DIV | norm:div_enc |
| divu_enc | DIVU | norm:divu_enc |
| rem_enc | REM | norm:rem_enc |
| remu_enc | REMU | norm:remu_enc |
| mulw_enc | MULW | norm:mulw_enc |
| divw_enc | DIVW | norm:divw_enc |
| divuw_enc | DIVUW | norm:divuw_enc |
| remw_enc | REMW | norm:remw_enc |
| remuw_enc | REMUW | norm:remuw_enc |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| diff_rv32e_rv32i | RV32E and RV64E use the same instruction-set encoding as RV32I and RV64I respectively, except that only registers x0-x15 are provided. All encodings specifying the other registers x16-x31 are reserved. | norm:diff_rv32e_rv32i |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| rv32i_xreg_sz | RV32I XLEN | Rule's "summary" property |
| For RV32I, the 32 x registers are each 32 bits wide, i.e., XLEN=32. |
norm:rv32i_xreg_sz | |
| rv32i_other_xregs | Registers x1 to x31 | Rule's "summary" property |
| General purpose registers x1-x31 hold values that various instructions interpret as a collection of Boolean values, or as two's complement signed binary integers or unsigned binary integers. |
norm:rv32i_rv64i_other_xregs | |
| pcreg_op | The pc contains a byte address so is incremented by 4 for 32-bit instructions and2 for 16-bit instructions. |
Rule's "description" property |
| There is one additional unprivileged register: the program counter pc holds the address of the current instruction. | norm:pcreg_op | |
| slti_op | SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). |
norm:slti_sltiu_op |
| sltiu_op | SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number). |
norm:slti_sltiu_op |
| x0eq0 | Register x0 always zero | Rule's "summary" property |
| Register x0 is hardwired with all bits equal to 0. | norm:x0eq0 | |
| taken_cti_misaligned_exc | CTI misaligned execution | Rule's "summary" property |
| An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not IALIGN-bit aligned. This exception is reported on the branch or jump instruction, not on the target instruction. |
norm:taken_cti_misaligned_exc | |
| cond_br_no_ia_misaligned_exc_not_taken | No IA misaligned exc on not taken | Rule's "summary" property |
| No instruction-address-misaligned exception is generated for a conditional branch that is not taken. |
norm:cond_br_no_ia_misaligned_exc_not_taken | |
| imm_always_sex | Immediates always sign-extended | Rule's "summary" property |
| Except for the 5-bit immediates used in CSR instructions (csrinsts), immediates are always sign-extended |
norm:imm_always_sex | |
| addi_op | ADDI adds the sign-extended 12-bit immediate to register rs1. | norm:addi_op |
| addi_overflow | Treatment of overflow | Rule's "summary" property |
| Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. | norm:addi_overflow | |
| andi_op | ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. |
norm:andi_ori_xori_op |
| ori_op | ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. |
norm:andi_ori_xori_op |
| xori_op | ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. |
norm:andi_ori_xori_op |
| slli_op | SLLI is a logical left shift (zeros are shifted into the lower bits); | norm:slli_op |
| srli_op | SRLI is a logical right shift (zeros are shifted into the upper bits); | norm:srli_op |
| srai_op | SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits). | norm:srai_op |
| lui_op | LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros. |
norm:lui_op |
| auipc_op | AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd. |
norm:auipc_op |
| R-type_operands | All operations read the rs1 and rs2 registers as source operands and write the result into register rd. |
norm:R-type_operands |
| add_op | ADD performs the addition of rs1 and rs2. | norm:add_op |
| sub_op | SUB performs the subtraction of rs2 from rs1. | norm:sub_op |
| add_overflow | Overflows are ignored and the low XLEN bits of results are written to the destination rd. | norm:add_sub_overflow |
| sub_overflow | Overflows are ignored and the low XLEN bits of results are written to the destination rd. | norm:add_sub_overflow |
| slt_op | SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. |
norm:slt_sltu_op |
| sltu_op | SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise. |
norm:slt_sltu_op |
| and_op | AND, OR, and XOR perform bitwise logical operations. | norm:and_or_xor_op |
| or_op | AND, OR, and XOR perform bitwise logical operations. | norm:and_or_xor_op |
| xor_op | AND, OR, and XOR perform bitwise logical operations. | norm:and_or_xor_op |
| sll_op | SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2. |
norm:sll_srl_sra_op |
| srl_op | SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2. |
norm:sll_srl_sra_op |
| sra_op | SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2. |
norm:sll_srl_sra_op |
| no_cti_delay_slots | Control transfer instructions in RV32I do not have architecturally visible delay slots. |
norm:no_cti_delay_slots |
| ia_fault_exc_on_target | If an instruction access-fault or instruction page-fault exception occurs on the target of a jump or taken branch, the exception is reported on the target instruction, not on the jump or branch instruction. |
norm:ia_fault_exc_on_target |
| jal_target | The offset is sign-extended and added to the address of the jump instruction to form the jump target address. |
norm:jal_target |
| jal_op | JAL stores the address of the instruction following the jump (pc+4) into register rd. |
norm:jal_op |
| jalr_target | The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero. |
norm:jalr_target |
| jalr_op | The address of the instruction following the jump (pc+4) is written to register rd. |
norm:jalr_op |
| jump_misaligned_exception | The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary. | norm:jump_misaligned_exception |
| jump_misaligned_c_no_exception | Instruction-address-misaligned exceptions are not possible on machines with IALIGN=16, e.g., those with the compressed instruction-set extension, C. | norm:jump_misaligned_c_no_exception |
| br_target | The 12-bit B-immediate encodes signed offsets in multiples of 2 bytes. The offset is sign-extended and added to the address of the branch instruction to give the target address. |
norm:br_target |
| beq_op | BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. | norm:beq_bne_op |
| bne_op | BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. | norm:beq_bne_op |
| blt_op | BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. |
norm:blt_bltu_op |
| bltu_op | BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. |
norm:blt_bltu_op |
| bge_op | BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. |
norm:bge_bgeu_op |
| bgeu_op | BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively. |
norm:bge_bgeu_op |
| branch_misaligned_taken_exception | The conditional branch instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary and the branch condition evaluates to true. |
norm:branch_misaligned_taken_exception |
| branch_misaligned_untaken_exception | If the branch condition evaluates to false, the instruction-address-misaligned exception will not be raised. |
norm:branch_misaligned_untaken_exception |
| branch_misaligned_c_no_exception | Instruction-address-misaligned exceptions are not possible on machines with IALIGN=16, e.g., those with the compressed instruction-set extension, C. | norm:branch_misaligned_c_no_exception |
| load_exc_x0 | Loads with a destination of x0 must still raise any exceptions and cause any other side effects even though the load value is discarded. |
norm:load_exc_x0 |
| ENDIANNESS | base | Rule's "kind" property |
| Any | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The EEI will define whether the memory system is little-endian or big-endian. | norm:ENDIANNESS | |
| ldst_endian_byte_invariant | In RISC-V, endianness is byte-address invariant. | norm:ldst_endian_byte_invariant |
| ldst_endian_byte_op | In a system for which endianness is byte-address invariant, the following property holds: if a byte is stored to memory at some address in some endianness, then a byte-sized load from that address in any endianness returns the stored value. | norm:ldst_endian_byte_op |
| ldst_little_endian_op | In a little-endian configuration, multibyte stores write the least-significant register byte at the lowest memory byte address, followed by the other register bytes in ascending order of their significance. Loads similarly transfer the contents of the lesser memory byte addresses to the less-significant register bytes. | norm:ldst_little_endian_op |
| ldst_big_endian_op | In a big-endian configuration, multibyte stores write the most-significant register byte at the lowest memory byte address, followed by the other register bytes in descending order of their significance. Loads similarly transfer the contents of the greater memory byte addresses to the less-significant register bytes. | norm:ldst_big_endian_op |
| ldst_ea | The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. |
norm:ldst_ea |
| ldst_no_exc_aligned | loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception. |
norm:ldst_no_exc_aligned |
| load_op | Loads copy a value from memory to register rd. | norm:load_op |
| store_op | Stores copy the value in register rs2 to memory. | norm:store_op |
| lw_op | The LW instruction loads a 32-bit value from memory into rd. | norm:lw_op |
| lh_op | LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. |
norm:lh_op |
| lhu_op | LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. |
norm:lhu_op |
| lb_op | LB and LBU are defined analogously for 8-bit values. | norm:lb_lbu_op |
| LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. |
norm:lh_op | |
| lbu_op | LB and LBU are defined analogously for 8-bit values. | norm:lb_lbu_op |
| LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. |
norm:lhu_op | |
| sw_op | The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory. |
norm:sw_sh_sb_op |
| sh_op | The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory. |
norm:sw_sh_sb_op |
| sb_op | The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory. |
norm:sw_sh_sb_op |
| MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Loads and stores whose effective address is not naturally aligned to the referenced datatype (i.e., the effective address is not divisible by the size of the access in bytes) have behavior dependent on the EEI. |
norm:misaligned_ldst_eei_dependent_behavior | |
| MISALIGNED_LDST_HW_SUPPORT | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| misaligned loads and stores can be handled in hardware, or via an invisible trap into the execution environment implementation, or possibly a combination of hardware and invisible trap depending on address. |
norm:misaligned_ldst_hw_support | |
| MISALIGNED_LDST_EXC_TYPE | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| loads and stores that are not naturally aligned may either complete execution successfully or raise an exception. The exception raised can be either an address-misaligned exception or an access-fault exception. For a memory access that would otherwise be able to complete except for the misalignment, an access-fault exception can be raised instead of an address-misaligned exception if the misaligned access should not be emulated, e.g., if accesses to the memory region have side effects. |
norm:misaligned_ldst_exc_type | |
| MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| When an EEI does not guarantee misaligned loads and stores are handled invisibly, the EEI must define if exceptions caused by address misalignment result in a contained trap (allowing software running inside the execution environment to handle the trap) or a fatal trap (terminating execution). |
norm:misaligned_ldst_contained_or_fatal_trap | |
| ldst_atomicity_for_aligned | naturally aligned loads and stores are guaranteed to execute atomically |
norm:ldst_atomicity_for_aligned |
| fence_op | A FENCE (with fm=0000) orders all memory operations in its predecessor set before all memory operations in its successor set. |
norm:fence_op |
| fence-tso_op | FENCE.TSO orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set. This leaves non-AMO store operations in the FENCE.TSO's predecessor set unordered with non-AMO loads in its successor set. |
norm:fence-tso_op |
| fence-tso_ordering_rw_rw_ok | Because FENCE RW,RW imposes a superset of the orderings that FENCE.TSO imposes, it is correct to ignore the fm field and implement FENCE.TSO as FENCE RW,RW. | norm:fence-tso_ordering_rw_rw_ok |
| fence_unused_flds_rsv | The unused fields in the FENCE instructions--rs1 and rd--are reserved for finer-grain fences in future extensions. For forward compatibility, base implementations shall ignore these fields |
norm:fence_unused_flds_rsv |
| fence_cons_ok | We chose a relaxed memory model to allow high performance from simple machine implementations and from likely future coprocessor or accelerator extensions. We separate out I/O ordering from memory R/W ordering to avoid unnecessary serialization within a device-driver hart and also to support alternative non-memory paths to control added coprocessors or I/O devices. Simple implementations may additionally ignore the predecessor and successor fields and always execute a conservative FENCE on all operations. | norm:fence_cons_ok |
| ecall_op | The ECALL instruction is used to make a service request to the execution environment. | norm:ecall_op1 |
| The ECALL instruction is used to make a request to the supporting execution environment. When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation. | norm:ecall_op2 | |
| ebreak_op | The EBREAK instruction is used to return control to a debugging environment. | norm:ebreak_op1 |
| The EBREAK instruction is used by debuggers to cause control to be transferred back to a debugging environment. Unless overridden by an external debug environment, EBREAK raises a breakpoint exception and performs no other operation. | norm:ebreak_op2 | |
| hints_op | HINTs do not change any architecturally visible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints. |
norm:hints_op |
| hints_enc | Most RV32I HINTs are encoded as integer computational instructions with rd=x0. The other RV32I HINTs are encoded as FENCE instructions with a null predecessor or successor set and with fm=0. |
norm:hints_enc |
| nop_op | The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters. |
norm:nop_op |
| nop_enc | NOP is encoded as ADDI x0, x0, 0. | norm:nop_enc |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| rv64i_xreg_sz | RV64I XLEN | Rule's "summary" property |
| RV64I widens the integer registers and supported user address space to 64 bits (XLEN=64 in gprs). |
norm:rv64i_xreg_sz | |
| rv64_w_sex | These "*W" instructions ignore the upper 32 bits of their inputs and always produce 32-bit signed values, sign-extending them to 64 bits, i.e. bits XLEN-1 through 31 are equal. |
norm:rv64_w_sex |
| rv64i_other_xregs | Registers x1 to x31 | Rule's "summary" property |
| General purpose registers x1-x31 hold values that various instructions interpret as a collection of Boolean values, or as two's complement signed binary integers or unsigned binary integers. |
norm:rv32i_rv64i_other_xregs | |
| addiw_op | ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign extension of a 32-bit result in rd. |
norm:addiw_op |
| slliw_op | SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. |
norm:slliw_srliw_sraiw_op |
| srliw_op | SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. |
norm:slliw_srliw_sraiw_op |
| sraiw_op | SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. |
norm:slliw_srliw_sraiw_op |
| slliw_imm5_rsv | Bit 5 of imm reserved | Rule's "summary" property |
| SLLIW, SRLIW, and SRAIW encodings with imm[5] {ne} 0 are reserved. |
norm:slliw_srliw_sraiw_imm5_rsv | |
| srliw_imm5_rsv | Bit 5 of imm reserved | Rule's "summary" property |
| SLLIW, SRLIW, and SRAIW encodings with imm[5] {ne} 0 are reserved. |
norm:slliw_srliw_sraiw_imm5_rsv | |
| sraiw_imm5_rsv | Bit 5 of imm reserved | Rule's "summary" property |
| SLLIW, SRLIW, and SRAIW encodings with imm[5] {ne} 0 are reserved. |
norm:slliw_srliw_sraiw_imm5_rsv | |
| lui_op_rv64i | LUI places the 32-bit U-immediate into register rd, filling in the lowest 12 bits with zeros. The 32-bit result is sign-extended to 64 bits. |
norm:lui_op_rv64i |
| auipc_op_rv64i | AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, sign-extends the result to 64 bits, adds it to the address of the AUIPC instruction, then places the result in register rd. |
norm:auipc_op_rv64i |
| addw_op | ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results. |
norm:addw_subw_op |
| subw_op | ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results. |
norm:addw_subw_op |
| addw_overflow | Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register. |
norm:addw_subw_overflow |
| subw_overflow | Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register. |
norm:addw_subw_overflow |
| addiw_overflow | Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. |
norm:addiw_overflow |
| sll_sh_amt_rv64i | In RV64I, only the low 6 bits of rs2 are considered for the shift amount. |
norm:sll_srl_sra_sh_amt_rv64i |
| srl_sh_amt_rv64i | In RV64I, only the low 6 bits of rs2 are considered for the shift amount. |
norm:sll_srl_sra_sh_amt_rv64i |
| sra_sh_amt_rv64i | In RV64I, only the low 6 bits of rs2 are considered for the shift amount. |
norm:sll_srl_sra_sh_amt_rv64i |
| sllw_op | SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0]. |
norm:sllw_srlw_sraw_op |
| srlw_op | SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0]. |
norm:sllw_srlw_sraw_op |
| sraw_op | SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0]. |
norm:sllw_srlw_sraw_op |
| ld_op_rv64i | The LD instruction loads a 64-bit value from memory into register rd for RV64I. |
norm:ld_op_rv64i |
| lw_op_rv64i | The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. |
norm:lw_op_rv64i |
| lwu_op | The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. |
norm:lwu_op |
| lh_op_rv64i | lh RV64I operation | Rule's "summary" property |
| The LD instruction loads a 64-bit value from memory into register rd for RV64I. |
norm:ld_op_rv64i | |
| The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. |
norm:lw_op_rv64i | |
| LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values. |
norm:lh_lhu_lb_lbu_op_rv64i | |
| lhu_rv64i_op | lhu RV64I operation | Rule's "summary" property |
| The LD instruction loads a 64-bit value from memory into register rd for RV64I. |
norm:ld_op_rv64i | |
| The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. |
norm:lw_op_rv64i | |
| LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values. |
norm:lh_lhu_lb_lbu_op_rv64i | |
| lb_rv64i_op | lb RV64I operation | Rule's "summary" property |
| The LD instruction loads a 64-bit value from memory into register rd for RV64I. |
norm:ld_op_rv64i | |
| The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. |
norm:lw_op_rv64i | |
| LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values. |
norm:lh_lhu_lb_lbu_op_rv64i | |
| lbu_rv64i_op | lbu RV64I operation | Rule's "summary" property |
| The LD instruction loads a 64-bit value from memory into register rd for RV64I. |
norm:ld_op_rv64i | |
| The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. |
norm:lw_op_rv64i | |
| LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values. |
norm:lh_lhu_lb_lbu_op_rv64i | |
| sd_op_rv64i | The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively. |
norm:sd_sw_sh_sb_op_rv64i |
| sw_op_rv64i | The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively. |
norm:sd_sw_sh_sb_op_rv64i |
| sh_op_rv64i | The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively. |
norm:sd_sw_sh_sb_op_rv64i |
| sb_op_rv64i | The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively. |
norm:sd_sw_sh_sb_op_rv64i |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| rvwmo_single_hart_op | Under RVWMO, code running on a single hart appears to execute in order from the perspective of other memory instructions in the same hart, but memory instructions from another hart may observe the memory instructions from the first hart being executed in a different order. |
norm:rvwmo_single_hart_op |
| rvwmo_only_mainmem | This chapter defines the memory model for regular main memory operations. The interaction of the memory model with I/O memory, instruction fetches, FENCE.I, page-table walks, and SFENCE.VMA is not (yet) formalized. |
norm:rvwmo_only_mainmem |
| rvwmo_excludes_overlap_widths | Memory consistency models supporting overlapping memory accesses of different widths simultaneously remain an active area of academic research and are not yet fully understood. The specifics of how memory accesses of different sizes interact under RVWMO are specified to the best of our current abilities |
norm:rvwmo_excludes_overlap_widths |
| rvwmo_single_copy_atomic | All memory operations are single-copy atomic: they can never be observed in a partially complete state. |
norm:rvwmo_single_copy_atomic |
| rvwmo_aligned_memop | Each aligned memory instruction that accesses XLEN or fewer bits gives rise to exactly one memory operation, unless specified otherwise. |
norm:rvwmo_aligned_memop |
| rvwmo_aligned_amo_memop | An aligned AMO gives rise to a single memory operation that is both a load operation and a store operation simultaneously. |
norm:rvwmo_aligned_amo_memop |
| rvwmo_sc_fail_no_memop | An unsuccessful SC instruction does not give rise to any memory operations. | norm:rvwmo_sc_fail_no_memop |
| rvwmo_v_multi_memops | ISA extensions such as V (Vector) and the upcoming P (SIMD) may give rise to multiple memory operations. |
norm:rvwmo_v_p_multi_memops |
| The memory operations generated by such instructions are not ordered with respect to each other in program order, but they are ordered normally with respect to the memory operations generated by preceding and subsequent instructions in program order. |
norm:rvwmo_order_multi_memops | |
| rvwmo_p_multi_memops | ISA extensions such as V (Vector) and the upcoming P (SIMD) may give rise to multiple memory operations. |
norm:rvwmo_v_p_multi_memops |
| The memory operations generated by such instructions are not ordered with respect to each other in program order, but they are ordered normally with respect to the memory operations generated by preceding and subsequent instructions in program order. |
norm:rvwmo_order_multi_memops | |
| rvwmo_misaligned_ldst_memops | A misaligned load or store instruction may be decomposed into a set of component memory operations of any granularity. |
norm:rvwmo_misaligned_ldst_memops |
| The memory operations generated by such instructions are not ordered with respect to each other in program order, but they are ordered normally with respect to the memory operations generated by preceding and subsequent instructions in program order. |
norm:rvwmo_order_multi_memops | |
| rvwmo_fp_gt_xlen_memops | A floating-point load or store of more than XLEN bits may also be decomposed into a set of component memory operations of any granularity. |
norm:rvwmo_fp_gt_xlen_memops |
| The memory operations generated by such instructions are not ordered with respect to each other in program order, but they are ordered normally with respect to the memory operations generated by preceding and subsequent instructions in program order. |
norm:rvwmo_order_multi_memops | |
| rvwmo_misaligned_in_atomic_pma | if misaligned atomics are supported via the misaligned atomicity granule PMA, then AMOs within an atomicity granule are not decomposed, nor are loads and stores defined in the base ISAs, nor are loads and stores of no more than XLEN bits defined in the F, D, and Q extensions. |
norm:rvwmo_misaligned_in_atomic_pma |
| rvwmo_obeyed | An execution of a RISC-V program obeys the RVWMO memory consistency model only if there exists a global memory order conforming to preserved program order and satisfying the load value axiom, the atomicity axiom, and the progress axiom. | norm:rvwmo_obeyed |
| rvwmo_ppo | The complete definition of preserved program order is as follows (and note that AMOs are simultaneously both loads and stores): memory operation a precedes memory operation b in preserved program order (and hence also in the global memory order) if a precedes b in program order, a and b both access regular main memory (rather than I/O regions), and any of the following hold: | norm:rvwmo_ppo_lead-in |
| Overlapping-Address Orderings | norm:rvwmo_ppo_overlap | |
| b is a store, and a and b access overlapping memory addresses | norm:rvwmo_ppo_overlap1 | |
| a and b are loads, x is a byte read by both a and b, there is no store to x between a and b in program order, and a and b return values for x written by different memory operations |
norm:rvwmo_ppo_overlap2 | |
| a is generated by an AMO or SC instruction, b is a load, and b returns a value written by a |
norm:rvwmo_ppo_overlap3 | |
| Explicit Synchronization | norm:rvwmo_ppo_sync | |
| There is a FENCE instruction that orders a before b | norm:rvwmo_ppo_sync1 | |
| a has an acquire annotation annotation | norm:rvwmo_ppo_sync2 | |
| b has a release annotation | norm:rvwmo_ppo_sync3 | |
| a and b both have RCsc annotations | norm:rvwmo_ppo_sync4 | |
| a is paired with b | norm:rvwmo_ppo_sync5 | |
| Syntactic Dependencies | norm:rvwmo_ppo_dep | |
| b has a syntactic address dependency on a | norm:rvwmo_ppo_dep1 | |
| b has a syntactic data dependency on a | norm:rvwmo_ppo_dep2 | |
| b is a store, and b has a syntactic control dependency on a | norm:rvwmo_ppo_dep3 | |
| Pipeline Dependencies | norm:rvwmo_ppo_pipe | |
| b is a load, and there exists some store m between a and b in program order such that m has an address or data dependency on a, and b returns a value written by m |
norm:rvwmo_ppo_pipe1 | |
| b is a store, and there exists some instruction m between a and b in program order such that m has an address dependency on a |
norm:rvwmo_ppo_pipe2 | |
| rvwmo_ld_val_axiom | Each byte of each load i returns the value written to that byte by the store that is the latest in global memory order among the following stores: | norm:rvwmo_ld_val_axiom_lead-in |
| Stores that write that byte and that precede i in the global memory order Stores that write that byte and that precede i in program order |
norm:rvwmo_ld_val_axiom_list | |
| rvwmo_atomicity_axiom | If r and w are paired load and store operations generated by aligned LR and SC instructions in a hart h, s is a store to byte x, and r returns a value written by s, then s must precede w in the global memory order, and there can be no store from a hart other than h to byte x following s and preceding w in the global memory order. | norm:rvwmo_atomicity_axiom |
| rvwmo_progress_axiom | No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations. | norm:rvwmo_progress_axiom |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| zkr_seed_addr | The entropy source extension defines the seed CSR at address 0x015. This CSR provides up to 16 physical entropy bits that can be used to seed cryptographic random bit generators. | norm:zkr_seed_addr |
| zkn_impl_all | A core which implements Zkn must implement all of the above extensions. | norm:zkn_impl_all |
| zks_impl_all | A core which implements Zks must implement all of the above extensions. | norm:zks_impl_all |
| zk_impl_all | A core which implements Zk must implement all of the above extensions. | norm:zk_impl_all |
| zk_scalar_xreg_op | All instructions described herein use the general-purpose X registers, and obey the 2-read-1-write register access constraint. |
norm:zk_scalar_xreg_op |
| zknd_shared_instr | NOTE: The insns-aes64ks1i and insns-aes64ks2 instructions are present in both the zknd and zkne extensions. |
norm:zknd_shared_instr |
| zkne_shared_instr | NOTE: The aes64ks1i and aes64ks2 instructions are present in both the zknd and zkne extensions. |
norm:zkne_shared_instr |
| aes32dsi_enc | Encoding | norm:aes32dsi_enc |
| aes32dsi_op | Operation | norm:aes32dsi_op |
| aes32dsmi_enc | Encoding | norm:aes32dsmi_enc |
| aes32dsmi_op | Operation | norm:aes32dsmi_op |
| aes32esi_enc | Encoding | norm:aes32esi_enc |
| aes32esi_op | Operation | norm:aes32esi_op |
| aes32esmi_enc | Encoding | norm:aes32esmi_enc |
| aes32esmi_op | Operation | norm:aes32esmi_op |
| aes64ds_enc | Encoding | norm:aes64ds_enc |
| aes64ds_op | Operation | norm:aes64ds_op |
| aes64dsm_enc | Encoding | norm:aes64dsm_enc |
| aes64dsm_op | Operation | norm:aes64dsm_op |
| aes64es_enc | Encoding | norm:aes64es_enc |
| aes64es_op | Operation | norm:aes64es_op |
| aes64esm_enc | Encoding | norm:aes64esm_enc |
| aes64esm_op | Operation | norm:aes64esm_op |
| aes64im_enc | Encoding | norm:aes64im_enc |
| aes64im_op | Operation | norm:aes64im_op |
| aes64ks1i_enc | Encoding | norm:aes64ks1i_enc |
| aes64ks1i_op | Operation | norm:aes64ks1i_op |
| aes64ks2_enc | Encoding | norm:aes64ks2_enc |
| aes64ks2_op | Operation | norm:aes64ks2_op |
| sha256sig0_enc | Encoding | norm:sha256sig0_enc |
| sha256sig0_op | Operation | norm:sha256sig0_op |
| sha256sig1_enc | Encoding | norm:sha256sig1_enc |
| sha256sig1_op | Operation | norm:sha256sig1_op |
| sha256sum0_enc | Encoding | norm:sha256sum0_enc |
| sha256sum0_op | Operation | norm:sha256sum0_op |
| sha256sum1_enc | Encoding | norm:sha256sum1_enc |
| sha256sum1_op | Operation | norm:sha256sum1_op |
| sha512sig0h_enc | Encoding | norm:sha512sig0h_enc |
| sha512sig0h_op | Operation | norm:sha512sig0h_op |
| sha512sig0l_enc | Encoding | norm:sha512sig0l_enc |
| sha512sig0l_op | Operation | norm:sha512sig0l_op |
| sha512sig1h_enc | Encoding | norm:sha512sig1h_enc |
| sha512sig1h_op | Operation | norm:sha512sig1h_op |
| sha512sig1l_enc | Encoding | norm:sha512sig1l_enc |
| sha512sig1l_op | Operation | norm:sha512sig1l_op |
| sha512sum0r_enc | Encoding | norm:sha512sum0r_enc |
| sha512sum0r_op | Operation | norm:sha512sum0r_op |
| sha512sum1r_enc | Encoding | norm:sha512sum1r_enc |
| sha512sum1r_op | Operation | norm:sha512sum1r_op |
| sha512sig0_enc | Encoding | norm:sha512sig0_enc |
| sha512sig0_op | Operation | norm:sha512sig0_op |
| sha512sig1_enc | Encoding | norm:sha512sig1_enc |
| sha512sig1_op | Operation | norm:sha512sig1_op |
| sha512sum0_enc | Encoding | norm:sha512sum0_enc |
| sha512sum0_op | Operation | norm:sha512sum0_op |
| sha512sum1_enc | Encoding | norm:sha512sum1_enc |
| sha512sum1_op | Operation | norm:sha512sum1_op |
| sm3p0_enc | Encoding | norm:sm3p0_enc |
| sm3p0_op | Operation | norm:sm3p0_op |
| sm3p1_enc | Encoding | norm:sm3p1_enc |
| sm3p1_op | Operation | norm:sm3p1_op |
| sm4ed_enc | Encoding | norm:sm4ed_enc |
| sm4ed_op | Operation | norm:sm4ed_op |
| sm4ks_enc | Encoding | norm:sm4ks_enc |
| sm4ks_op | Operation | norm:sm4ks_op |
| seed_ro_illegal | Attempts to access the seed CSR using a read-only CSR-access instruction (CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0) raise an illegal-instruction exception; any other CSR-access instruction may be used to access seed. |
norm:seed_ro_illegal |
| seed_write_ignore | The write value (in rs1 or uimm) must be ignored by implementations. | norm:seed_write_ignore |
| seed_csr_unpriv | seed is an unprivileged CSR located at address 0x015. | norm:seed_csr_unpriv |
| seed_exec_mode_control | The seed CSR is also access controlled by execution mode, and attempted read or write access will raise an illegal-instruction exception outside M mode unless access is explicitly granted. See crypto_scalar_es_access for more details. |
norm:seed_exec_mode_control |
| seed_entropy_unique | Each returned seed[15:0] = entropy value represents unique randomness when OPST=ES16 (seed[31:30] = 10), even if its numerical value is the same as that of a previously polled entropy value. |
norm:seed_entropy_unique |
| seed_entropy_zero_non_es16 | When OPST is not ES16, entropy must be set to 0. | norm:seed_entropy_zero_non_es16 |
| seed_wipe_on_read | For security reasons, the interface guarantees that secret entropy words are not made available multiple times. Hence polling (reading) must also have the side effect of clearing (wipe-on-read) the entropy contents and changing the state to WAIT (unless there is entropy immediately available for ES16). Other states (BIST, WAIT, and DEAD) may be unaffected by polling. |
norm:seed_wipe_on_read |
| seed_bist_latch | Such a BIST alarm must be latched until polled at least once to enable software to record its occurrence. |
norm:seed_bist_latch |
| seed_min_security_256 | Any implementation of the seed CSR that limits the security strength shall not reduce it to less than 256 bits. |
norm:seed_min_security_256 |
| seed_disable_if_weak | If the security level is under 256 bits, then the interface must not be available. |
norm:seed_disable_if_weak |
| zkt_optional_instr | Vendors do not have to implement all of the list's instructions to be Zkt compliant; |
norm:zkt_optional_instr |
| zkt_impl_must_constant_latency | if they claim to have Zkt and implement any of the listed instructions, it must have data-independent latency. | norm:zkt_impl_must_constant_latency |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| cfi_call_term | The term call is used to refer to a JAL or JALR instruction with a link register as destination, i.e., rd≠x0. Conventionally, the link register is x1 or x5. A call using JAL or C.JAL is termed a direct call. A C.JALR expands to JALR x1, 0(rs1) and is a call. A call using JALR or C.JALR is termed an indirect-call. | norm:cfi_call_term |
| cfi_return_term | The term return is used to refer to a JALR instruction with rd=x0 and with rs1=x1 or rs1=x5. A C.JR instruction expands to JALR x0, 0(rs1) and is a return if rs1=x1 or rs1=x5. | norm:cfi_return_term |
| cfi_indirect-jump_term | The term indirect-jump is used to refer to a JALR instruction with rd=x0 and where the rs1 is not x1 or x5 (i.e., not a return). A C.JR instruction where rs1 is not x1 or x5 (i.e., not a return) is an indirect-jump. | norm:cfi_indirect-jump_term |
| Zicflip_lpad_enc | The LPAD instruction (See LP_INST) is encoded using the AUIPC major opcode with rd=x0. |
norm:zicflip_lpad_enc |
| The LPAD instruction is encoded with a 20-bit immediate value called the landing-pad-label (LPL) that is matched to the expected landing pad label. When LPL is encoded as zero, the LPAD instruction does not perform the label check and in programs built with this single label mode of operation the indirect call/jump sites do not need to establish an expected landing pad label value in x7. |
norm:zicflip_lpad_imm_enc | |
| Zicflip_lpad_expected | The Zicfilp extension, when enabled, determines if an indirect call or an indirect jump must land on a landing pad, as specified in . If is_lp_expected is 1, then the hart updates the ELP to LP_EXPECTED. | norm:zicflip_lpad_expected |
| Zicflip_indirect_branch_lpad | An indirect branch using JALR, C.JALR, or C.JR with rs1 as x7 is termed a software guarded branch. Such branches do not need to land on a LPAD instruction and thus do not set ELP to LP_EXPECTED. | norm:zicflip_indirect_branch_lpad |
| Zicflip_lpad_label | To support labeled landing pads, the indirect call/jump sites establish an expected landing pad label (e.g., using the LUI instruction) in the bits 31:12 of the x7 register. |
norm:zicflip_lpad_label |
| Zicflip_elp_lpad_expected | When ELP is set to LP_EXPECTED, if the next instruction in the instruction stream is not 4-byte aligned, or is not LPAD, or if the landing pad label encoded in LPAD is not zero and does not match the expected landing pad label in bits 31:12 of the x7 register, then a software-check exception (cause=18) with xtval set to "landing pad fault (code=2)" is raised else the ELP is updated to NO_LP_EXPECTED. | norm:zicflip_elp_lpad_expected |
| Zicflip_lpad_enabled_instr_allowed | When Zicfilp is enabled, LPAD is the only instruction allowed to execute when the ELP state is LP_EXPECTED. If Zicfilp is not enabled then the instruction is a no-op. |
norm:zicflip_lpad_enabled_instr_allowed |
| Zicflip_lpad_exception | If Zicfilp is enabled, the LPAD instruction causes a software-check exception with xtval set to "landing pad fault (code=2)" |
norm:zicflip_lpad_enabled_exception |
| The pc is not 4-byte aligned and ELP is LP_EXPECTED. | norm:zicflip_lpad_alignment_exception | |
| The ELP is LP_EXPECTED and the LPL is not zero and the LPL does not match the expected landing pad label in bits 31:12 of the x7 register. | norm:zicflip_lpad_label_exception | |
| If a software-check exception is not caused then the ELP is updated to NO_LP_EXPECTED. | norm:zicflip_lpad_no_sw_exception | |
| Zicfiss_link_reg_func | When Zicfiss is enabled, each function that needs to spill the link register, typically non-leaf functions, store the link register value to the regular stack and a shadow copy of the link register value to the shadow stack when the function is entered (the prologue). |
norm:zicfiss_link_reg_func_enter |
| When such a function returns (the epilogue), the function loads the link register from the regular stack and the shadow copy of the link register from the shadow stack. |
norm:zicfiss_link_reg_func_return | |
| Then, the link register value from the regular stack and the shadow link register value from the shadow stack are compared. A mismatch of the two values is indicative of a subversion of the return address control variable and causes a software-check exception. |
norm:zicfiss_stack_compare | |
| Zicfiss_enc | The Zicfiss instructions, except SSAMOSWAP.W/D, are encoded using a subset of May-Be-Operation instructions defined by the Zimop and Zcmop extensions. |
norm:zicfiss_enc |
| Zicfiss_sspush_enc | SSPUSH x1 and SSPUSH x5 - encoded using MOP.RR.7 | norm:zicfiss_sspush_enc |
| C.SSPUSH x1 - encoded using C.MOP.1 | norm:zicfiss_c-sspush_enc | |
| Zicfiss_sspopchk_enc | SSPOPCHK x1 and SSPOPCHK x5 - encoded using MOP.R.28 | norm:zicfiss_sspopchk_enc |
| C.SSPOPCHK x5 - encoded using C.MOP.5 | norm:zicfiss_c-sspopchk_enc | |
| Zicfiss_ssrdp_enc | SSRDP - encoded using MOP.R.28 | norm:zicfiss_ssrdp_enc |
| Zicfiss_atomic_swap | Perform an atomic swap from a shadow stack location (See SSAMOSWAP) | norm:zicfiss_atomic_swap |
| csr_ssp | The ssp CSR is an unprivileged read-write (URW) CSR that reads and writes XLEN low order bits of the shadow stack pointer (ssp). |
norm:ssp_op |
| The CSR address is 0x011. |
norm:ssp_addr | |
| There is no high CSR defined as the ssp is always as wide as the XLEN of the current privilege mode. |
norm:ssp_sz | |
| The bits 1:0 of ssp are read-only zero. If the UXLEN or SXLEN may never be 32, then the bit 2 is also read-only zero. |
norm:ssp-field_1_0 | |
| ss_push_c-push_op | A shadow stack push operation is defined as decrement of the ssp by XLEN/8 followed by a store of the value in the link register to memory at the new top of the shadow stack. | norm:ss_push |
| The SSPUSH instruction and its compressed form C.SSPUSH can be used to push a link register on the shadow stack. The SSPUSH and C.SSPUSH instructions perform a store identically to the existing store instructions, with the difference that the base is implicitly ssp and the width is implicitly XLEN. | norm:sspush_c-sspush_instr | |
| The ssp is decremented by SSPUSH and C.SSPUSH only if the store to the shadow stack completes successfully. | norm:sspush_c-sspush_decrement | |
| sspopchk_op | A shadow stack pop operation is defined as an XLEN wide read from the current top of the shadow stack followed by an increment of the ssp by XLEN/8. | norm:ss_pop |
| The SSPOPCHK instruction, and its compressed form C.SSPOPCHK, can be used to pop the shadow return address value from the shadow stack and check that the value matches the contents of the link register, and if not cause a software-check exception with xtval set to "shadow stack fault (code=3)". | norm:sspopchk_shadow_return_pop | |
| The C.SSPOPCHK, and SSPOPCHK instructions perform a load identically to the existing load instructions, with the difference that the base is implicitly ssp and the width is implicitly XLEN. | norm:sspopchk-c_load_op | |
| If the value loaded from the address in ssp does not match the value in rs1, a software-check exception (cause=18) is raised with xtval set to "shadow stack fault (code=3)". The software-check exception caused by SSPOPCHK/ C.SSPOPCHK is lower in priority than a load/store/AMO access-fault exception. | norm:sspop_exception | |
| The ssp is incremented by SSPOPCHK and C.SSPOPCHK only if the load from the shadow stack completes successfully and no software-check exception is raised. | norm:sspop_increment | |
| ssrdp_read | The SSRDP instruction is provided to move the contents of ssp to a destination register. | norm:ssrdp_read |
| rv32_ssamoswap | For RV32, SSAMOSWAP.W atomically loads a 32-bit data value from address of a shadow stack location in rs1, puts the loaded value into register rd, and stores the 32-bit value held in rs2 to the original address in rs1. SSAMOSWAP.D (RV64 only) is similar to SSAMOSWAP.W but operates on 64-bit data values. | norm:rv32_ssamoswap-w_op |
| Just as for AMOs in the A extension, SSAMOSWAP.W/D requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords, and four-byte aligned for words). The same exception options apply if the address is not naturally aligned. | norm:ssamoswap_address | |
| rv64_ssamoswap | For RV64, SSAMOSWAP.W atomically loads a 32-bit data value from address of a shadow stack location in rs1, sign-extends the loaded value and puts it in rd, and stores the lower 32 bits of the value held in rs2 to the original address in rs1. | norm:rv64_ssamoswap-w_op |
| Just as for AMOs in the A extension, SSAMOSWAP.W/D requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords, and four-byte aligned for words). The same exception options apply if the address is not naturally aligned. | norm:ssamoswap_address |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Smctr_Ssctr_dependencies | Smctr and Ssctr depend on both the implementation of S-mode and the Sscsrind extension. | Rule's "summary" property |
| Smctr and Ssctr depend on both the implementation of S-mode and the Sscsrind extension. | norm:Smctr_Ssctr_depend | |
| CTR_DEPTH | CTR buffer depth depends on implementation maximum and software-selected configuration. | Rule's "summary" property |
| The number of records that can be held in the buffer depends upon both the implementation (the maximum supported depth) and the CTR configuration (the software selected depth). | norm:ctr_depth | |
| It is implementation-specific which DEPTH value(s) are supported. | norm:sctrdepth_depth | |
| Smctr_recording_criteria | Only transfers meeting filtering criteria (privilege mode, transfer type) are recorded. | Rule's "summary" property |
| Only qualified transfers are recorded. Qualified transfers are those that meet the filtering criteria, which include the privilege mode and the transfer type. | norm:Smctr_recording_criteria | |
| Smctr_transfer_steps | Recorded transfers are inserted at write pointer; overwrites on full buffer; optional RAS mode. | Rule's "summary" property |
| Recorded transfers are inserted at the write pointer, which is then incremented, while older recorded transfers may be overwritten once the buffer is full. Or the user can enable RAS (Return Address Stack) emulation mode, where only function calls are recorded, and function returns pop the last call record. The source PC, target PC, and some optional metadata (transfer type, elapsed cycles) are stored for each recorded transfer. | norm:Smctr_transfer_steps | |
| Smctr_CTR_CSR_interface | CTR buffer accessed via indirect CSR; logical entry 0 = youngest transfer. | Rule's "summary" property |
| The CTR buffer is accessible through an indirect CSR interface, such that software can specify which logical entry in the buffer it wishes to read or write. Logical entry 0 always corresponds to the youngest recorded transfer, followed by entry 1 as the next youngest, and so on. | norm:Smctr_CTR_CSR_interface | |
| Smctr_scope | Smctr covers machine-level CSRs, instructions, and behavior; Ssctr excludes machine-level only. | Rule's "summary" property |
| The machine-level extension, Smctr, encompasses all newly added Control Status Registers (CSRs), instructions, and behavior modifications for a hart across all privilege levels. | norm:Smctr_scope | |
| The corresponding supervisor-level extension, Ssctr, is essentially identical to Smctr, except that it excludes machine-level CSRs and behaviors not intended to be directly accessible at the supervisor level. | norm:Ssctr_transfer_steps | |
| mctrctl | 64-bit R/W register to enable and configure CTR. | Rule's "summary" property |
| The mctrctl register is a 64-bit read/write register that enables and configures the CTR capability. | norm:Ssctr_mctrctl_sz_acc_op | |
| mctrctl_mode_en | Enable transfer recording in selected privilege mode(s). | Rule's "summary" property |
| Enable transfer recording in the selected privileged mode(s). | norm:mctrctl_mode_op | |
| mctrctl_rasemu | Enables RAS (Return Address Stack) emulation mode. | Rule's "summary" property |
| Enables RAS (Return Address Stack) Emulation Mode. | norm:mctrctl_rasemu_op | |
| mctrctl_mte | Enables recording of traps to M-mode when M=0. | Rule's "summary" property |
| Enables recording of traps to M-mode when M=0. | norm:mctrctl_mte_op | |
| mctrctl_ste | Enables recording of traps to S-mode when S=0. | Rule's "summary" property |
| Enables recording of traps to S-mode when S=0. | norm:mctrctl_ste_op | |
| mctrctl_bpfrz | Sets sctrstatus.FROZEN on breakpoint trap to M or S mode. | Rule's "summary" property |
| Set sctrstatus.FROZEN on a breakpoint exception that traps to M-mode or S-mode. | norm:mctrctl_bpfrz_op | |
| mctrctl_lcofifrz | Sets sctrstatus.FROZEN on local-counter-overflow trap to M or S. | Rule's "summary" property |
| Set sctrstatus.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to M-mode or S-mode. | norm:mctrctl_lcofifrz_op | |
| mctrctl_excinh | Inhibit recording of exceptions. | Rule's "summary" property |
| Inhibit recording of exceptions. | norm:mctrctl_excinh_op | |
| mctrctl_intrinh | Inhibit recording of interrupts. | Rule's "summary" property |
| Inhibit recording of interrupts. | norm:mctrctl_intrinh_op | |
| mctrctl_tretinh | Inhibit recording of trap returns. | Rule's "summary" property |
| Inhibit recording of trap returns. | norm:mctrctl_tretinh_op | |
| mctrctl_ntbren | Enable recording of not-taken branches. | Rule's "summary" property |
| Enable recording of not-taken branches. | norm:mctrctl_ntbren_op | |
| mctrctl_tkbrinh | Inhibit recording of taken branches. | Rule's "summary" property |
| Inhibit recording of taken branches. | norm:mctrctl_tkbrinh_op | |
| mctrctl_indcallinh | Inhibit recording of indirect calls. | Rule's "summary" property |
| Inhibit recording of indirect calls. | norm:mctrctl_indcallinh_op | |
| mctrctl_dircallinh | Inhibit recording of direct calls. | Rule's "summary" property |
| Inhibit recording of direct calls. | norm:mctrctl_dircallinh_op | |
| mctrctl_indjmpinh | Inhibit recording of indirect jumps (no linkage). | Rule's "summary" property |
| Inhibit recording of indirect jumps (without linkage). | norm:mctrctl_indjmpinh_op | |
| mctrctl_dirjmpinh | Inhibit recording of direct jumps (no linkage). | Rule's "summary" property |
| Inhibit recording of direct jumps (without linkage). | norm:mctrctl_dirjmpinh_op | |
| mctrctl_corswapinh | Inhibit recording of co-routine swaps. | Rule's "summary" property |
| Inhibit recording of co-routine swaps. | norm:mctrctl_corswapinh_op | |
| mctrctl_retinh | Inhibit recording of function returns. | Rule's "summary" property |
| Inhibit recording of function returns. | norm:mctrctl_retinh_op | |
| mctrctl_indljmpinh | Inhibit recording of other indirect jumps (with linkage). | Rule's "summary" property |
| Inhibit recording of other indirect jumps (with linkage). | norm:mctrctl_indljmpinh_op | |
| mctrctl_dirljmpinh | Inhibit recording of other direct jumps (with linkage). | Rule's "summary" property |
| Inhibit recording of other direct jumps (with linkage). | norm:mctrctl_dirljmpinh_op | |
| mctrctl_custom | WARL custom bits; value 0 = standard behavior. | Rule's "summary" property |
| WARL bits designated for custom use. | norm:mctrctl_custom_op | |
| mctrctl_impl | All fields optional except M, S, U, BPFRZ; unimplemented = read-only 0. | Rule's "summary" property |
| All fields are optional except for M, S, U, and BPFRZ. All unimplemented fields are read-only 0, while all implemented fields are writable. If the Sscofpmf extension is implemented, LCOFIFRZ must be writable. | norm:mctrctl_impl | |
| sctrctl | Supervisor access subset of mctrctl; M and MTE excluded. | Rule's "summary" property |
| The sctrctl register provides supervisor mode access to a subset of mctrctl. | norm:Ssctr_sctrctl_op | |
| Bits 2 and 9 in sctrctl are read-only 0. As a result, the M and MTE fields in mctrctl are not accessible through sctrctl. All other mctrctl fields are accessible through sctrctl. | norm:Ssctr_sctrctl_acc | |
| vsctrctl | VS-mode’s version of sctrctl; used when V=1. | Rule's "summary" property |
| If the H extension is implemented, the vsctrctl register is a 64-bit read/write register that is VS-mode's version of supervisor register sctrctl. When V=1, vsctrctl substitutes for the usual sctrctl, so instructions that normally read or modify sctrctl actually access vsctrctl instead. | norm:Ssctr_vsctrctl_sz_acc_op | |
| vsctr-s | Enable transfer recording in VS-mode. | Rule's "summary" property |
| Enable transfer recording in VS-mode. | norm:vsctr-s_op | |
| vsctrctl-u | Enable transfer recording in VU-mode. | Rule's "summary" property |
| Enable transfer recording in VU-mode. | norm:vsctrctl-u_op | |
| vsctrctl-ste | Enables recording of traps to VS-mode when S=0. | Rule's "summary" property |
| Enables recording of traps to VS-mode when S=0. | norm:vsctrctl-ste_op | |
| vsctrctl-bpfrz | Sets FROZEN on breakpoint trap to VS-mode. | Rule's "summary" property |
| Set sctrstatus.FROZEN on a breakpoint exception that traps to VS-mode. | norm:vsctrctl-bpfrz_op | |
| vsctrctl-lcofifrz | Sets FROZEN on local-counter-overflow trap to VS-mode. | Rule's "summary" property |
| Set sctrstatus.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to VS-mode. | norm:vsctrctl-lcofifrz_op | |
| sctrdepth | 32-bit register selecting CTR buffer depth. | Rule's "summary" property |
| The 32-bit sctrdepth register specifies the depth of the CTR buffer. | norm:sctrdepth | |
| It is implementation-specific which DEPTH value(s) are supported. | norm:sctrdepth_depth | |
| SCTRDEPTH_DEPTH | WARL field encoding CTR buffer depth (16–256, reserved encodings). | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| WARL field that selects the depth of the CTR buffer. | norm:sctrdepth_depth_op0 | |
| The depth of the CTR buffer dictates the number of entries to which the hardware records transfers. For a depth of N, the hardware records transfers to entries 0..N-1. All Entry Registers read as '0' and are read-only when the selected entry is in the range N to 255. When the depth is increased, the newly accessible entries contain unspecified but legal values. | norm:sctrdepth_depth_op1 | |
| It is implementation-specific which DEPTH value(s) are supported. | norm:sctrdepth_depth | |
| SCTRDEPTH_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| WARL field that selects the depth of the CTR buffer. | norm:sctrdepth_depth_op0 | |
| sctrdepth_mode | VS/VU-mode access to sctrdepth raises virtual-instruction exception unless enabled. | Rule's "summary" property |
| Attempts to access sctrdepth from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply. | norm:sctrdepth_mode | |
| sctrstatus | 32-bit register with CTR status; active when privilege mode enabled and not frozen. | Rule's "summary" property |
| The 32-bit sctrstatus register grants access to CTR status information and is updated by the hardware whenever CTR is active. CTR is active when the current privilege mode is enabled for recording and CTR is not frozen. | norm:sctrstatus | |
| sctrstatus_wrptr | WARL field pointing to next CTR buffer entry; wraps on depth. | Rule's "summary" property |
| WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see Behavior), though there are exceptions when xctrctl.RASEMU=1, see RAS (Return Address Stack) Emulation Mode. For a given CTR depth (where depth = 2(DEPTH+4)), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value. | norm:sctrstatus_wrptr | |
| SCTRSTATUS_WRPTR_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see Behavior), though there are exceptions when xctrctl.RASEMU=1, see RAS (Return Address Stack) Emulation Mode. For a given CTR depth (where depth = 2(DEPTH+4)), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value. | norm:sctrstatus_wrptr | |
| sctrstatus_frozen_op | FROZEN bit inhibits transfer recording. | Rule's "summary" property |
| Inhibit transfer recording. | norm:sctrstatus_frozen_op | |
| sctrstatus_acc | Undefined bits WPRI, read-only 0 unless custom extension. | Rule's "summary" property |
| Undefined bits in sctrstatus are WPRI. Status fields may be added by future extensions, and software should ignore but preserve any fields that it does not recognize. Undefined bits must be implemented as read-only 0, unless a custom extension is implemented and enabled |
norm:Ssctr_sctrstatus_acc | |
| siselect_acc_op | Indirect CSR index range 0x200..0x2FF reserved for CTR entries. | Rule's "summary" property |
| The siselect index range 0x200 through 0x2FF is reserved for CTR logical entries 0 through 255. When siselect holds a value in this range, sireg provides access to ctrsource, sireg2 provides access to ctrtarget, and sireg3 provides access to ctrdata. sireg4, sireg5, and sireg6 are read-only 0. | norm:siselect_acc_op | |
| vsiselect_op | VS-mode indirect entry registers mirror S-mode. | Rule's "summary" property |
| When vsiselect holds a value in 0x200..0x2FF, the vsireg* registers provide access to the same CTR entry register state as the analogous sireg* registers. There is not a separate set of entry registers for V=1. | norm:vsiselect_op | |
| ctrsource_op | ctrsource holds source PC or epc of trap. | Rule's "summary" property |
| The ctrsource register contains the source program counter, which is the pc of the recorded control transfer instruction, or the epc of the recorded trap. | norm:ctrsource_op | |
| ctrsource_validbit | V bit indicates valid data in ctrsource/ctrtarget/ctrdata. | Rule's "summary" property |
| The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in ctrsource, ctrtarget, and ctrdata is valid for this entry. | norm:ctrsource_ctrtartget_ctrdata_Vbit | |
| ctrsource_sz_acc | MXLEN WARL register; must hold valid PC addresses; zero-extended if XLEN| Rule's "summary" property |
|
| ctrsource is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended. | norm:Ssctr_ctrsource_sz_acc_op | |
| CTRSOURCE_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| ctrsource is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended. | norm:Ssctr_ctrsource_sz_acc_op | |
| ctrtarget_op | ctrtarget holds destination PC of recorded transfer. | Rule's "summary" property |
| The ctrtarget register contains the target (destination) program counter of the recorded transfer. |
norm:ctrtarget_op | |
| ctrtarget_pc_next_br | For a not-taken branch, ctrtarget holds the PC of the next sequential instruction following the branch. | norm:ctrtarget_pc_next_br |
| ctrtarget_misp | Optional MISP bit shows branch misprediction; read-only 0 if unimplemented. | Rule's "summary" property |
| The optional MISP bit is set by the hardware when the recorded transfer is an instruction whose target or taken/not-taken direction was mispredicted by the branch predictor. MISP is read-only 0 when not implemented. |
norm:ctrtarget_misp | |
| ctrtarget_sz_acc | MXLEN WARL register; holds valid PC addresses; zero-extended if XLEN| Rule's "summary" property |
|
| ctrtarget is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended. | norm:ctrtarget_sz_acc | |
| CTRTARGET_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| ctrtarget is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended. | norm:ctrtarget_sz_acc | |
| ctrdata_sz_acc | ctrdata holds metadata; mandatory register, fields optional, 64-bit. | Rule's "summary" property |
| The ctrdata register contains metadata for the recorded transfer. This register must be implemented, though all fields within it are optional. Unimplemented fields are read-only 0. ctrdata is a 64-bit register. |
norm:ctrdata_sz_acc | |
| CTRDATA_CC_SUPPORTED | ctrdata register may optionally include a count of CPU cycles | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The ctrdata register may optionally include a count of CPU cycles elapsed since the prior CTR record. The elapsed cycle count value is represented by the CC field, which has a 12-bit mantissa component (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE). | norm:ctrdata_cc_supported | |
| ctrdata_type | TYPE encodes control transfer type; 0 if not supported. | Rule's "summary" property |
| Identifies the type of the control flow transfer recorded in the entry, using the encodings listed in xref:transfer-type-defs[xrefstyle=short]. Implementations that do not support this field will report 0. | norm:ctrdata_type | |
| ctrdata_ccv | Cycle Count Valid bit. | Rule's "summary" property |
| Cycle Count Valid. | norm:ctrdata_ccv | |
| ctrdata_cc | Cycle Count value (mantissa + exponent). | Rule's "summary" property |
| Cycle Count, composed of the Cycle Count Exponent (CCE, in CC[15:12]) and Cycle Count Mantissa (CCM, in CC[11:0]). |
norm:ctrdata_cc | |
| ctrdata_undef | Undefined ctrdata bits WPRI, read-only 0 unless custom extension. | Rule's "summary" property |
| Undefined bits in ctrdata are WPRI. Undefined bits must be implemented as read-only 0, unless a custom extension is implemented and enabled. | norm:ctrdata_undef | |
| sctrclr | Instruction clears entry registers and cycle counter. | Rule's "summary" property |
| Zeroes all CTR Entry Registers, for all DEPTH values | norm:sctrclr_op1 | |
| Zeroes the CTR cycle counter and CCV | norm:sctrclr_op2 | |
| Any read of ctrsource, ctrtarget, or ctrdata that follows SCTRCLR, such that it precedes the next qualified control transfer, will return the value 0. Further, the first recorded transfer following SCTRCLR will have ctrdata.CCV=0. | norm:sctrclr_acc | |
| SCTRCLR raises an illegal-instruction exception in U-mode, and a virtual-instruction exception in VU-mode, unless CTR state enable access restrictions apply. | norm:sctrclr_exceptions | |
| mstateen_ctr | mstateen0.CTR controls CTR access for lower modes. | Rule's "summary" property |
| When mstateen0.CTR=1, accesses to CTR register state behave as described in CSRs and Entry Registers above, while SCTRCLR behaves as described in Supervisor CTR Clear Instruction. | norm:mstateen_ctr1 | |
| When mstateen0.CTR=0 and the privilege mode is less privileged than M-mode, the following operations raise an illegal-instruction exception: | norm:mstateen_ctr0 | |
| Attempts to access sctrctl, vsctrctl, sctrdepth, or sctrstatus | norm:mstateen_ctr0_execpt1 | |
| Attempts to access sireg* when siselect is in 0x200..0x2FF, or vsireg* when vsiselect is in 0x200..0x2FF | norm:mstateen_ctr0_execpt2 | |
| Execution of the SCTRCLR instruction | norm:mstateen_ctr0_execpt3 | |
| When mstateen0.CTR=0, qualified control transfers executed in privilege modes less privileged than M-mode will continue to implicitly update entry registers and sctrstatus. | norm:mstateen_ctr0_qualified_transfer | |
| hstateen_ctr | hstateen0.CTR controls VS-mode access to CTR; read-only 0 if mstateen0.CTR=0. | Rule's "summary" property |
| If the H extension is implemented and mstateen0.CTR=1, the hstateen0.CTR bit controls access to supervisor CTR state when V=1. This state includes sctrctl (really vsctrctl), sctrstatus, and sireg* (really vsireg*) when siselect (really vsiselect) is in 0x200..0x2FF. hstateen0.CTR is read-only 0 when mstateen0.CTR=0. | norm:hstateen_ctr | |
| When mstateen0.CTR=1 and hstateen0.CTR=1, VS-mode accesses to supervisor CTR state behave as described in CSRs and Entry Registers above, while SCTRCLR behaves as described in Supervisor CTR Clear Instruction. When mstateen0.CTR=1 and hstateen0.CTR=0, both VS-mode accesses to supervisor CTR state and VS-mode execution of SCTRCLR raise a virtual-instruction exception. | norm:hstateen_vs | |
| hstateen0_CTR0-V1_update_sctrstatus | hstateen0.CTR=0 and V=1 updates sctrstatus implicitly | Rule's "summary" property |
| When hstateen0.CTR=0, qualified control transfers executed while V=1 will continue to implicitly update entry registers and sctrstatus. | norm:hstateen0_CTR0-V1_op | |
| ctr_behavior | CTR records transfers if mode enabled, type not inhibited, not frozen, and retired. | Rule's "summary" property |
| CTR records qualified control transfers. Control transfers are qualified if they meet the following criteria: | norm:ctr_behavior | |
| The current privilege mode is enabled | norm:ctr_behavior_criteria0 | |
| The transfer type is not inhibited | norm:ctr_behavior_criteri1 | |
| sctrstatus.FROZEN is not set | norm:ctr_behavior_criteria2 | |
| The transfer completes/retires | norm:ctr_behavior_criteria3 | |
| ctr_stack | CTR buffer operates as circular stack; overwrites oldest entries when full. | Rule's "summary" property |
| Such qualified transfers update the Entry Registers at logical entry 0. As a result, older entries are pushed down the stack; the record previously in logical entry 0 moves to logical entry 1, the record in logical entry 1 moves to logical entry 2, and so on. If the CTR buffer is full, the oldest recorded entry (previously at entry depth-1) is lost. | norm:ctr_stack | |
| ctr_validbit | Recorded transfers set ctrsource.V=1 and update fields. | Rule's "summary" property |
| Recorded transfers will set the ctrsource.V bit to 1, and will update all implemented record fields. | norm:ctr_validbit | |
| ctr_trap_rules | Defines when traps/trap returns are recorded depending on enabled/disabled modes. | Rule's "summary" property |
| Traps between enabled privilege modes are recorded as normal. | norm:ctr_trap_enabled | |
| Traps from a disabled privilege mode to an enabled privilege mode are partially recorded, such that the ctrsource.PC is 0. | norm:ctr_trap_disabled_src | |
| Traps from an enabled mode to a disabled mode, known as external traps, are not recorded by default. | norm:ctr_trap_disabled_tgt | |
| Trap returns between enabled privilege modes are recorded as normal. | norm:ctr_trapret_enabled | |
| Trap returns from an enabled mode back to a disabled mode are partially recorded, such that ctrtarget.PC is 0. | norm:ctr_trapret_to_disabled | |
| Trap returns from a disabled mode to an enabled mode are not recorded. | norm:ctr_trapret_from_disabled | |
| Recorded | norm:ctr_trap_ee | |
| External trap. Not recorded by default, | norm:ctr_trap_ed | |
| Recorded, ctrsource.PC is 0. | norm:ctr_trap_de | |
| Not recorded. | norm:ctr_trap_dd | |
| Recorded. | norm:ctr_trapret_ee | |
| Recorded, ctrtarget.PC is 0. | norm:ctr_trapret_ed | |
| Not recorded. | norm:ctr_trapret_de | |
| Not recorded. | norm:ctr_trapret_dd | |
| ctr_debug_recording_inhibited | Debug mode inhibits recording | Rule's "summary" property |
| Recording in Debug Mode is always inhibited. Transfers into and out of Debug Mode are never recorded. | norm:debug_recording_inhibited | |
| ctr_exttrap | External traps not recorded by default; can opt-in with TE bits. | Rule's "summary" property |
| External traps are traps from a privilege mode enabled for CTR recording to a privilege mode that is not enabled for CTR recording. By default external traps are not recorded, but privileged software running in the target mode of the trap can opt-in to allowing CTR to record external traps into that mode. The xctrctl.xTE bits allow M-mode, S-mode, and VS-mode to opt-in separately. | norm:exttrap_def | |
| External trap recording depends not only on the target mode, but on any intervening modes, which are modes that are more privileged than the source mode but less privileged than the target mode. Not only must the external trap enable bit for the target mode be set, but the external trap enable bit(s) for any intervening modes must also be set. | norm:exttrap_requirements | |
| sctrctl.STE | norm:exttrap_us | |
| mctrctl.MTE, sctrctl.STE | norm:exttrap_um | |
| mctrctl.MTE | norm:exttrap_sm | |
| vsctrctl.STE | norm:exttrap_vuvs | |
| sctrctl.STE, vsctrctl.STE | norm:exttrap_vuhs | |
| mctrctl.MTE, sctrctl.STE, vsctrctl.STE | norm:exttrap_vum | |
| sctrctl.STE | norm:exttrap_vshs | |
| mctrctl.MTE, sctrctl.STE | norm:exttrap_vsm | |
| In records for external traps, the ctrtarget.PC is 0. | norm:exttrap_ctrtarget0 | |
| If external trap recording is implemented, mctrctl.MTE and sctrctl.STE must be implemented, while vsctrctl.STE must be implemented if the H extension is implemented. | norm:exttrap_implreq | |
| ctr_ttf_default | Default is to record all transfers unless filtered by type bits. | Rule's "summary" property |
| Default CTR behavior, when all transfer type filter bits (xctrctl[47:32]) are unimplemented or 0, is to record all control transfers within enabled privileged modes. By setting transfer type filter bits, software can opt out of recording select transfer types, or opt into recording non-default operations. All transfer type filter bits are optional. | norm:ctr_ttf_default | |
| ctr_ttype | Transfer type encodings 0–15 with specific meanings. | Rule's "summary" property |
| Not used by CTR | norm:ctr_ttype0 | |
| Exception | norm:ctr_ttype1 | |
| Interrupt | norm:ctr_ttype2 | |
| Trap return | norm:ctr_ttype3 | |
| Not-taken branch | norm:ctr_ttype4 | |
| Taken branch | norm:ctr_ttype5 | |
| Indirect call | norm:ctr_ttype8 | |
| Direct call | norm:ctr_ttype9 | |
| Indirect jump (without linkage) | norm:ctr_ttype10 | |
| Direct jump (without linkage) | norm:ctr_ttype11 | |
| Co-routine swap | norm:ctr_ttype12 | |
| Function return | norm:ctr_ttype13 | |
| Other indirect jump (with linkage) | norm:ctr_ttype14 | |
| Other direct jump (with linkage) | norm:ctr_ttype15 | |
| ctr_various_jump_enc | encodings for various indirect jumps with linkage. | Rule's "summary" property |
| Encodings 8 through 15 refer to various encodings of jump instructions. The types are distinguished as described below. | norm:ctr_various_jump_enc | |
| ctr_ccounter | Cycle counter increments with mcycle; reset on ctrctl writes and SCTRCLR; CCV/CC fields define elapsed cycles. | Rule's "summary" property |
| The elapsed cycle counter (CtrCycleCounter) increments at the same rate as the mcycle counter. Only cycles while CTR is active are counted, where active implies that the current privilege mode is enabled for recording and CTR is not frozen. The CC field is encoded such that CCE holds 0 if the CtrCycleCounter value is less than 4096, otherwise it holds the index of the most significant one bit in the CtrCycleCounter value, minus 11. CCM holds CtrCycleCounter bits CCE+10:CCE-1. | norm:ctr_ccounter_inc | |
| The CtrCycleCounter is reset on writes to xctrctl, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch. | norm:ctr_ccounter_reset | |
| 4095 | norm:ccsize0 | |
| 8191 | norm:ccsize1 | |
| 32764 | norm:ccsize2 | |
| 524224 | norm:ccsize3 | |
| 134201344 | norm:ccsize4 | |
| The CC value saturates when all implemented bits in CCM and CCE are 1. | norm:ctr_ccounter_sat | |
| The CC value is valid only when the Cycle Count Valid (CCV) bit is set. If CCV=0, the CC value might not hold the correct count of elapsed active cycles since the last recorded transfer. The next record will have CCV=0 after a write to xctrctl, or execution of SCTRCLR, since CtrCycleCounter is reset. CCV should additionally be cleared after any other implementation-specific scenarios where active cycles might not be counted in CtrCycleCounter. | norm:ctr_ccounter_ccv | |
| CTR_CCOUNTER_IMPL | Implementation can support 0 to 4 exponent bits | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| An implementation that supports cycle counting must implement CCV and all CCM bits, but may implement 0..4 exponent bits in CCE. Unimplemented CCE bits are read-only 0. For implementations that support transfer type filtering, it is recommended to implement at least 3 exponent bits. This allows capturing the full latency of most functions, when recording only calls and returns. |
norm:ctr_ccounter_impl | |
| ctrctl_rasemu | RASEMU bit enables RAS emulation mode with altered recording behavior. | Rule's "summary" property |
| When the optional xctrctl.RASEMU bit is implemented and set to 1, transfer recording behavior is altered to emulate the behavior of a return-address stack (RAS). | norm:ctrctl_rasemu_op | |
| ctr_freeze | FROZEN bit inhibits CTR recording; set on LCOFI or breakpoint traps. | Rule's "summary" property |
| When sctrctl.LCOFIFRZ=1 and a local-counter-overflow interrupt (LCOFI) traps (as a result of an HPM counter overflow) to M-mode or to S-mode, sctrstatus.FROZEN is set by hardware. This inhibits CTR recording until software clears FROZEN. The LCOFI trap itself is not recorded. |
norm:sctrstatus_frozen_set | |
| Similarly, on a breakpoint exception that traps to M-mode or S-mode with sctrctl.BPFRZ=1, FROZEN is set by hardware. The breakpoint exception itself is not recorded. | norm:ctr_freeze_bp | |
| If the H extension is implemented, freeze behavior for LCOFIs and breakpoint exceptions that trap to VS-mode is determined by the LCOFIFRZ and BPFRZ values, respectively, in vsctrctl. This includes virtual LCOFIs pended by a hypervisor. | norm:ctr_freeze_vs | |
| ctr_custom_bits | Non-zero custom bits in ctrctl enable custom extensions; must revert to standard when zero. | Rule's "summary" property |
| Any custom CTR extension must be associated with a non-zero value within the designated custom bits in xctrctl. When the custom bits hold a non-zero value that enables a custom extension, the extension may alter standard CTR behavior, and may define new custom status fields within sctrstatus or the CTR Entry Registers. All custom status fields, and standard status fields whose behavior is altered by the custom extension, must revert to standard behavior when the custom bits hold zero. This includes read-only 0 behavior for any bits undefined by any implemented standard extensions. | norm:ctr_custom_bits |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| mcyclecfg_sz | mcyclecfg and minstretcfg are 64-bit registers | norm:mcyclecfg_sz |
| mcyclecfg_op | configure privilege mode filtering for the cycle and instret counters, respectively. | norm:mcyclecfg_op |
| all_xinh_zero | When all xINH bits are zero, event counting is enabled in all modes. | norm:all_xinh_zero |
| unimplemented_mode_bits | For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero. | norm:unimplemented_mode_bits |
| rv32_high_access | For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR. | norm:rv32_high_access |
| csr_supervisor_access | The content of these registers may be accessible from Supervisor level if the Smcdeleg/Ssccfg extensions are implemented. | norm:csr_supervisor_access |
| counter_inhibited_behavior | The fundamental behavior of cycle and instret is modified in that counting does not occur while executing in an inhibited privilege mode. | norm:counter_inhibited_behavior |
| transition_counting_defined | Further, the following defines how transitions between a non-inhibited privilege mode and an inhibited privilege mode are counted. | norm:transition_counting_defined |
| cycle_counting | The cycle counter will simply count CPU cycles while the CPU is in a non-inhibited privilege mode. | norm:cycle_counting |
| instret_non_inhibited | instructions that retire in a non-inhibited mode increment instret, and instructions that retire in an inhibited mode do not. | norm:instret_non_inhibited |
| instret_exception | The former are not considered to retire, and hence do not increment instret. | norm:instret_exception |
| instret_xret | The latter do retire, and should increment instret only if the originating privilege mode is not inhibited. | norm:instret_xret |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Smdbltrp_with_Smrnmi_op | When Smrnmi is implemented, a double trap in M-mode invokes the RNMI handler to handle the critical error | Rule's "summary" property |
| When the Smrnmi extension (rnmi) is implemented, it enables invocation of the RNMI handler on a double trap in M-mode to handle the critical error. |
norm:Smdbltrp_with_Smrnmi_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| smepmp_no_mml_limit | Without the Smepmp extension, it is not possible for a PMP rule to be enforced only on non-Machine modes and denied on Machine mode, in order to allow access to a memory region solely by less-privileged modes. | norm:smepmp_no_mml_limit |
| smepmp_no_mml_behavior | It is only possible to have a locked rule that will be enforced on all modes, or a rule that will be enforced on non-Machine modes and be ignored by Machine mode. | norm:smepmp_no_mml_behavior |
| smepmp_machine_unlimited | So for any physical memory region which is not protected with a Locked rule, Machine mode has unlimited access, including the ability to execute it. | norm:smepmp_machine_unlimited |
| smepmp_attack_surface | Without being able to protect less-privileged modes from Machine mode, it is not possible to prevent the mentioned attack vector. | norm:smepmp_attack_surface |
| mseccfg_fields_exist | this extension introduces the RLB, MMWP, and MML fields in the mseccfg CSR and their associated rules. |
norm:mseccfg_fields_exist |
| mml_truth_table | The physical memory protection rules when mseccfg.MML is set to 1 are summarized in the truth table below. | norm:mml_truth_table |
| mseccfg_locking | Since all fields defined in mseccfg as part of this extension are locked when set (MMWP/MML) or locked when cleared (RLB), software can't poll them for determining the presence of Smepmp. | norm:mseccfg_locking |
| bootrom_discovery | It is expected that BootROM will set mseccfg.MMWP and/or mseccfg.MML during early boot, before jumping to the firmware, so that the firmware will be able to determine the presence of Smepmp by reading mseccfg and checking the state of mseccfg.MMWP and mseccfg.MML. | norm:bootrom_discovery |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Smrnmi_csrs | The extension adds four new CSRs (mnepc, mncause, mnstatus, and mnscratch) to hold the interrupted state |
norm:Smrnmi_csrs |
| mnret_exist | one new instruction, MNRET, to resume from the RNMI handler. |
norm:mnret_exist |
| rnmi_priority | These interrupts have higher priority than any other interrupt or exception on the hart |
norm:rnmi_priority |
| rnmi_not_disabled | cannot be disabled by software. Specifically, they are not disabled by clearing the mstatus.MIE register. |
norm:rnmi_not_disabled |
| rnmi_trap_addr | The RNMI interrupt trap handler address is implementation-defined. | norm:rnmi_trap_addr |
| rnmi_exc_trap_addr | RNMI also has an associated exception trap handler address, which is implementation defined. |
norm:rnmi_exc_trap_addr |
| mnscratch_sz | The mnscratch CSR holds an MXLEN-bit | norm:mnscratch_sz |
| mnscratch_acc | read-write register | norm:mnscratch_acc |
| mnscratch_op | enables the RNMI trap handler to save and restore the context that was interrupted. |
norm:mnscratch_op |
| mnepc_sz | The mnepc CSR is an MXLEN-bit | norm:mnepc_sz |
| mnepc_acc | read-write register | norm:mnepc_acc |
| mnepc_op | RNMI trap handler holds the PC of the instruction that took the interrupt. |
norm:mnepc_op |
| mnepc_bit0 | The low bit of mnepc (mnepc[0]) is always zero. | norm:mnepc_bit0 |
| mnepc_ialign32 | On implementations that support only IALIGN=32, the two low bits (mnepc[1:0]) are always zero. |
norm:mnepc_ialign32 |
| mnepc_ialign_mask | If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), then, whenever IALIGN=32, bit mnepc[1] is masked on reads so that it appears to be 0. |
norm:mnepc_ialign_mask |
| mnepc_bit1_writable | Though masked, mnepc[1] remains writable when IALIGN=32. |
norm:mnepc_bit1_writable |
| MNEPC_WARL | extension | Rule's "kind" property |
| Smrnmi | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| mnepc is a WARL register that must be able to hold all valid virtual addresses. |
norm:mnepc_warl | |
| MNCAUSE_WARL | extension | Rule's "kind" property |
| Smrnmi | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:mncause_img | |
| mnepc_invalid_convert | Prior to writing mnepc, implementations may convert an invalid address into some other invalid address that mnepc is capable of holding. |
norm:mnepc_invalid_convert |
| mncause_op | The mncause CSR holds the reason for the RNMI. | norm:mncause_op |
| mncause_interrupt | If the reason is an interrupt, bit MXLEN-1 is set to 1, | norm:mncause_interrupt |
| mncause_interrupt_code | the RNMI cause is encoded in the least-significant bits. |
norm:mncause_interrupt_code |
| mncause_interrupt_zero | If the reason is an interrupt and RNMI causes are not supported, bit MXLEN-1 is set to 1, and zero is written to the least-significant bits. |
norm:mncause_interrupt_zero |
| mncause_doubletrap | If the reason is an exception within M-mode that results in a double trap as specified in the Smdbltrp extension, bit MXLEN-1 is set to 0 and the least-significant bits are set to the cause code corresponding to the exception that precipitated the double trap. |
norm:mncause_doubletrap |
| MNSTATUS_WARL | extension | Rule's "kind" property |
| Smrnmi | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:mnstatus_img | |
| mnstatus_mnpp_op | The mnstatus CSR holds a two-bit field, MNPP, which on entry to the RNMI trap handler holds the privilege mode of the interrupted context, encoded in the same manner as mstatus.MPP. |
norm:mnstatus_mnpp_op |
| mnstatus_mnpv_op | It also holds a one-bit field, MNPV, which on entry to the RNMI trap handler holds the virtualization mode of the interrupted context, encoded in the same manner as mstatus.MPV. |
norm:mnstatus_mnpv_op |
| mnstatus_mnpelp_op | If the Zicfilp extension is implemented, mnstatus also holds the MNPELP field, which on entry to the RNMI trap handler holds the previous ELP state. |
norm:mnstatus_mnpelp_op |
| mnstatus_mnpelp_update | When an RNMI trap is taken, MNPELP is set to ELP and ELP is set to 0. | norm:mnstatus_mnpelp_update |
| mnstatus_nmie_enable | When NMIE=1, non-maskable interrupts are enabled. |
norm:mnstatus_nmie_enable |
| mnstatus_nmie_disable | When NMIE=0, all interrupts are disabled. | norm:mnstatus_nmie_disable |
| mnstatus_mprv_clear | When NMIE=0, the hart behaves as though mstatus.MPRV were clear, regardless of the current setting of mstatus.MPRV. |
norm:mnstatus_mprv_clear |
| mnstatus_nmie_reset | Upon reset, NMIE contains the value 0. | norm:mnstatus_nmie_reset |
| mnstatus_nmie_set_clear | Software can set NMIE to 1, but attempts to clear NMIE have no effect. | norm:mnstatus_nmie_set_clear |
| mnstatus_wfi | For the purposes of the WFI instruction, NMIE is a global interrupt enable, meaning that the setting of NMIE does not affect the operation of the WFI instruction. |
norm:mnstatus_wfi |
| mnstatus_reserved | The other bits in mnstatus are reserved; software should write zeros and hardware implementations should return zeros. |
norm:mnstatus_reserved |
| mnret_mode | MNRET is an M-mode-only instruction | norm:mnret_mode |
| mnret_restore | This instruction also sets mnstatus.NMIE. |
norm:mnret_restore |
| mnret_mprv | If MNRET changes the privilege mode to a mode less privileged than M, it also sets mstatus.MPRV to 0. | norm:mnret_mprv |
| mnret_zicfilp | If the Zicfilp extension is implemented, then if the new privileged mode is y, MNRET sets ELP to the logical AND of yLPE (see FCFIACT) and mnstatus.MNPELP. |
norm:mnret_zicfilp |
| rnmi_entry | When an RNMI interrupt is detected, the interrupted PC is written to the mnepc CSR, |
norm:rnmi_entry |
| rnmi_entry_cause | the type of RNMI to the mncause CSR, | norm:rnmi_entry_cause |
| rnmi_entry_priv | the privilege mode of the interrupted context to the mnstatus CSR. |
norm:rnmi_entry_priv |
| rnmi_entry_nmie_clear | The mnstatus.NMIE bit is cleared, masking all interrupts. |
norm:rnmi_entry_nmie_clear |
| rnmi_enter_mmode | The hart then enters machine-mode and jumps to the RNMI trap handler address. |
norm:rnmi_enter_mmode |
| rnmi_resume | The RNMI handler can resume original execution using the new MNRET instruction, which restores the PC from mnepc, the privilege mode from mnstatus, and also sets mnstatus.NMIE, which re-enables interrupts. |
norm:rnmi_resume |
| rnmi_exception_nmie0 | If the hart encounters an exception while executing in M-mode with the mnstatus.NMIE bit clear, the actions taken are the same as if the exception had occurred while mnstatus.NMIE were set, except that the program counter is set to the RNMI exception trap handler address. | norm:rnmi_exception_nmie0 |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| mhpmevent_inh_op | Each of the five xINH bits, when set, inhibit counting of events while in privilege mode x. All-zeroes for these bits results in counting of events in all modes. | norm:mhpmevent_inh_op |
| mhpmevent_of_op | The OF bit is set when the corresponding hpmcounter overflows, and remains set until written by software. |
norm:mhpmevent_of_op |
| hpmcounter_overflow | Since hpmcounter values are unsigned values, overflow is defined as unsigned overflow of the implemented counter bits. |
norm:hpmcounter_overflow |
| count_overflow_interrupt | If an hpmcounter overflows while the associated OF bit is zero, then a "count overflow interrupt request" is generated. If the OF bit is one, then no interrupt request is generated. Consequently the OF bit also functions as a count overflow interrupt disable for the associated hpmcounter. | norm:count_overflow_interrupt |
| count_overflow_trigger | Count overflow never results from writes to the mhpmcountern or mhpmeventn registers, only from hardware increments of counter registers. | norm:count_overflow_trigger |
| mhpmevent_of_bit_set | Generation of a count-overflow-interrupt request by an hpmcounter sets the associated OF bit. |
norm:mhpmevent_of_bit_set |
| sip_lcofip_op | When an OF bit is set, it eventually, but not necessarily immediately, sets the LCOFIP bit in the mip/sip registers. |
norm:LCOFIP_op |
| scountovf_op | This extension adds the scountovf CSR, a 32-bit read-only register that contains shadow copies of the OF bits in the 29 mhpmevent CSRs (mhpmevent3 - mhpmevent31) - where scountovf bit X corresponds to mhpmeventX. | norm:scountovf_op |
| scountovf_smode_read_access_control | Read access to bit X is subject to the same mcounteren (or mcounteren and hcounteren) CSRs that mediate access to the hpmcounter CSRs by S-mode (or VS-mode). |
norm:scountovf_smode_read_access_control |
| scountovf_mmode_read_access | In M-mode, scountovf bit X is always readable. | norm:scountovf_mmode_read_access |
| scountovf_smode_read_access | In S/HS-mode, scountovf bit X is readable when mcounteren bit X is set, and otherwise reads as zero. |
norm:scountovf_smode_read_access |
| scountovf_vsmode_read_access | Similarly, in VS mode, scountovf bit X is readable when mcounteren bit X and hcounteren bit X are both set, and otherwise reads as zero. |
norm:scountovf_vsmode_read_access |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| HS_mode_invoke_error | HS-mode must invoke a critical error handler in a virtual machine on a double trap in VS-mode | Rule's "summary" property |
| It enables HS-mode to invoke a critical error handler in a virtual machine on a double trap in VS-mode. |
norm:HS_mode_invoke_error | |
| M_mode_invoke_error | M-mode must invoke a critical error handler in the OS/Hypervisor on a double trap in S/HS-mode | Rule's "summary" property |
| It also allows M-mode to invoke a critical error handler in the OS/Hypervisor on a double trap in S/HS-mode. |
norm:M_mode_invoke_error | |
| menvcfg_DTE | The Ssdbltrp extension adds the menvcfg.DTE field | Rule's "summary" property |
| The Ssdbltrp extension adds the menvcfg.DTE (See sec:menvcfg) | norm:menvcfg_DTE | |
| sstatus_SDT | The Ssdbltrp extension adds the sstatus.SDT field | Rule's "summary" property |
| and the sstatus.SDT fields (See sstatus). |
norm:sstatus_SDT | |
| henvcfg_DTE | If the hypervisor extension is implemented, Ssdbltrp adds the henvcfg.DTE field | Rule's "summary" property |
| If the hypervisor extension is additionally implemented, then the extension adds the henvcfg.DTE (See sec:henvcfg) |
norm:henvcfg_DTE | |
| vsstatus_SDT | If the hypervisor extension is implemented, Ssdbltrp adds the vsstatus.SDT field | Rule's "summary" property |
| and the vsstatus.SDT fields (See vsstatus). | norm:vsstatus_SDT |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| sstc_purpose | This extension serves to provide supervisor mode with its own CSR-based timer interrupt facility that it can directly manage to provide its own timer service (in the form of having its own stimecmp register) - thus eliminating the large overheads for emulating S/HS-mode timers and timer interrupt generation up in M-mode. |
norm:sstc_purpose |
| sstc_vs_facility | Further, this extension adds a similar facility to the Hypervisor extension for VS-mode. |
norm:sstc_vs_facility |
| stimecmp_exist | This extension adds the S-level stimecmp CSR (stimecmp) |
norm:stimecmp_exist |
| vstimecmp_exist | and the VS-level vstimecmp CSR (vstimecmp). | norm:vstimecmp_exist |
| menvcfg_stce_exist | This extension adds the STCE bit to the menvcfg (sec:menvcfg) and henvcfg (sec:henvcfg) CSRs. |
norm:stce_bit_exist |
| henvcfg_stce_exist | This extension adds the STCE bit to the menvcfg (sec:menvcfg) and henvcfg (sec:henvcfg) CSRs. |
norm:stce_bit_exist |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| smstateen_mmode_rv64_csrs | For RV64 harts, this extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. | norm:smstateen_mmode_rv64_csrs |
| smstateen_smode_rv64_csrs | If supervisor mode is implemented, another four CSRs are defined at supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. | norm:smstateen_smode_rv64_csrs |
| smstateen_hypervisor_rv64_csrs | And if the hypervisor extension is implemented, another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. | norm:smstateen_hypervisor_rv64_csrs |
| smstateen_rv32_upper_bits_csrs | For RV32, there are CSR addresses for accessing the upper 32 bits of corresponding machine-level and hypervisor CSRs: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, hstateen1h, hstateen2h, and hstateen3h. | norm:smstateen_rv32_upper_bits_csrs |
| stateen_op | The stateen registers at each level control access to state at all less-privileged levels, but not at its own level. |
norm:stateen_op |
| smstateen_illegal_state_access | Just as with the counteren CSRs, when a stateen CSR prevents access to state by less-privileged levels, an attempt in one of those privilege modes to execute an instruction that would read or write the protected state raises an illegal-instruction exception, or, if executing in VS or VU mode and the circumstances for a virtual-instruction exception apply, raises a virtual-instruction exception instead of an illegal-instruction exception. |
norm:smstateen_illegal_state_access |
| smstateen_implicit_state_update | When a stateen CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal-instruction or virtual-instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. | norm:smstateen_implicit_state_update |
| sstateen_user_access_control | Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) to an extension's state. |
norm:sstateen_user_access_control |
| sstateen_bit_allocation | The intention is to allocate the bits of sstateen CSRs starting at the least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered sstateen CSR. |
norm:sstateen_bit_allocation |
| sstateen_bit_correspondence | For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the matching mstateen CSR to control access below machine level to the same state. |
norm:sstateen_bit_correspondence |
| mstateen_bit_allocation | The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, through to bit 32, and then on to the next-higher mstateen CSR. |
norm:mstateen_bit_allocation |
| mstateen_bit_encroachment | If the rate that bits are being allocated from the least-significant end for sstateen CSRs is sufficiently low, allocation from the most-significant end of mstateen CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher mstateen CSR. |
norm:mstateen_bit_encroachment |
| sstateen_encroachment_bits_roz | In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in the matching sstateen CSRs. |
norm:sstateen_encroachment_bits_roz |
| hstateen_encoding | With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen CSRs, except controlling accesses for a virtual machine (from VS and VU modes). | norm:hstateen_encoding |
| STATEEN_WARL_ACCESS | extension | Rule's "kind" property |
| Smstateen | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| Each standard-defined bit of a stateen CSR is WARL and may be read-only zero or one, subject to the following conditions. | norm:stateen_warl_access | |
| stateen_unimplemented_state_roz | Bits in any stateen CSR that are defined to control state that a hart doesn't implement are read-only zeros for that hart. |
norm:stateen_unimplemented_state_roz |
| stateen_reserved_roz | Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. |
norm:stateen_reserved_roz |
| sstateen_vsmode_access_roz | For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in sstateen when accessed in VS-mode. |
norm:sstateen_vsmode_access_roz |
| sstateen_ro1_bits | A bit in a supervisor-level sstateen CSR cannot be read-only one unless the same bit is read-only one in the matching mstateen CSR and, if it exists, in the matching hstateen CSR. |
norm:sstateen_ro1_bits |
| hstateen_ro1_bits | A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one in the matching mstateen CSR. |
norm:hstateen_ro1_bits |
| mstateen_zero_initialization | On reset, all writable mstateen bits are initialized by the hardware to zeros. | norm:mstateen_zero_initialization |
| hstateen_sstateen_zero_initialization | If machine-level software changes these values, it is responsible for initializing the corresponding writable bits of the hstateen and sstateen CSRs to zeros too. |
norm:hstateen_sstateen_zero_initialization |
| mstateen_bit_63_op | For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen CSRs. |
norm:mstateen_bit_63_op |
| hstateen_bit_63_op | Likewise, bit 63 of each hstateen correspondingly controls access to the matching sstateen CSR. |
norm:hstateen_bit_63_op |
| mstateen_bit_63_roz | Bit 63 of each mstateen CSR may be read-only zero only if the hypervisor extension is not implemented and the matching supervisor-level sstateen CSR is all read-only zeros. |
norm:mstateen_bit_63_roz |
| hstateen_bit_63_writable | Bit 63 of each hstateen CSR is always writable (not read-only). |
norm:hstateen_bit_63_writable |
| stateen0_c_op | The C bit controls access to any and all custom state. | norm:stateen0_c_op |
| stateen0_fcsr_op | The FCSR bit controls access to fcsr for the case when floating-point instructions operate on x registers instead of f registers as specified by the Zfinx and related extensions (Zdinx, etc.). |
norm:stateen0_fcsr_op |
| stateen0_fcsr0_misa_f0_illegal_fpu_instr | For convenience, when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a controlling stateen0 CSR is zero, all floating-point instructions cause an illegal-instruction exception (or virtual-instruction exception, if relevant), as though they all access fcsr, regardless of whether they really do. |
norm:stateen0_fcsr0_misa_f0_illegal_fpu_instr |
| stateen0_jvt_op | The JVT bit controls access to the jvt CSR provided by the Zcmt extension. | norm:stateen0_jvt_op |
| mstateen0_se0_op | The SE0 bit in mstateen0 controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs. |
norm:mstateen0_se0_op |
| hstateen0_se0_op | The SE0 bit in hstateen0 controls access to the sstateen0 CSR. |
norm:hstateen0_SE0_op |
| mstateen0_envcfg_op | The ENVCFG bit in mstateen0 controls access to the henvcfg, henvcfgh, and the senvcfg CSRs. |
norm:mstateen0_envcfg_op |
| hstateen0_envcfg_op | The ENVCFG bit in hstateen0 controls access to the senvcfg CSRs. |
norm:hstateen0_envcfg_op |
| mstateen0_csrind_op | The CSRIND bit in mstateen0 controls access to the siselect, sireg*, vsiselect, and the vsireg* CSRs provided by the Sscsrind extensions. |
norm:mstateen0_csrind_op |
| hstateen0_csrind_op | The CSRIND bit in hstateen0 controls access to the siselect and the sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind extensions. |
norm:hstateen0_csrind_op |
| mstateen0_imsic_op | The IMSIC bit in mstateen0 controls access to the IMSIC state, including CSRs stopei and vstopei, provided by the Ssaia extension. |
norm:mstateen0_imsic_op |
| hstateen0_imsic_op | The IMSIC bit in hstateen0 controls access to the guest IMSIC state, including CSRs stopei (really vstopei), provided by the Ssaia extension. |
norm:hstateen0_imsic_op |
| mstateen0_aia_op | The AIA bit in mstateen0 controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits. |
norm:mstateen0_aia_op |
| hstateen0_aia_op | The AIA bit in hstateen0 controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits of hstateen0. |
norm:hstateen0_aia_op |
| mstateen0_context_op | The CONTEXT bit in mstateen0 controls access to the scontext and hcontext CSRs provided by the Sdtrig extension. |
norm:mstateen0_context_op |
| hstateen0_context_op | The CONTEXT bit in hstateen0 controls access to the scontext CSR provided by the Sdtrig extension. |
norm:hstateen0_context_op |
| mstateen0_p1p13_op | The P1P13 bit in mstateen0 controls access to the hedelegh introduced by Privileged Specification Version 1.13. | norm:mstateen0_p1p13_op |
| mstateen0_srmcfg_op | The SRMCFG bit in mstateen0 controls access to the srmcfg CSR introduced by the Ssqosid extension. | norm:mstateen0_srmcfg_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| sstatus_sz | The sstatus register is an SXLEN-bit read/write register formatted as shown in when SXLEN=32 and when SXLEN=64. The sstatus register keeps track of the processor’s current operating state. | norm:sstatus |
| sstatus_mode | The sstatus register is an SXLEN-bit read/write register formatted as shown in when SXLEN=32 and when SXLEN=64. The sstatus register keeps track of the processor’s current operating state. | norm:sstatus |
| sstatus_acc | The sstatus register is an SXLEN-bit read/write register formatted as shown in when SXLEN=32 and when SXLEN=64. The sstatus register keeps track of the processor’s current operating state. | norm:sstatus |
| sstatus_spp_sz | The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise. When an SRET instruction (see ) is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0. | norm:sstatus_spp |
| sstatus_spp_acc | The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise. When an SRET instruction (see ) is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0. | norm:sstatus_spp |
| sstatus_spp_op | The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise. When an SRET instruction (see ) is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0. | norm:sstatus_spp |
| sstatus_sie_sz | The SIE bit enables or disables all interrupts in supervisor mode. When SIE is clear, interrupts are not taken while in supervisor mode. When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled. The supervisor can disable individual interrupt sources using the sie CSR. | norm:sstatus_sie |
| sstatus_sie_acc | The SIE bit enables or disables all interrupts in supervisor mode. When SIE is clear, interrupts are not taken while in supervisor mode. When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled. The supervisor can disable individual interrupt sources using the sie CSR. | norm:sstatus_sie |
| sstatus_sie_op | The SIE bit enables or disables all interrupts in supervisor mode. When SIE is clear, interrupts are not taken while in supervisor mode. When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled. The supervisor can disable individual interrupt sources using the sie CSR. | norm:sstatus_sie |
| sstatus_spie_sz | The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1. | norm:sstatus_spie |
| sstatus_spie_acc | The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1. | norm:sstatus_spie |
| sstatus_spie_op | The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1. | norm:sstatus_spie |
| sstatus_uxl_acc | The UXL field controls the value of XLEN for U-mode, termed UXLEN, which may differ from the value of XLEN for S-mode, termed SXLEN. The encoding of UXL is the same as that of the MXL field of misa, shown in . | norm:sstatus_uxl |
| sstatus_uxl_op | The UXL field controls the value of XLEN for U-mode, termed UXLEN, which may differ from the value of XLEN for S-mode, termed SXLEN. The encoding of UXL is the same as that of the MXL field of misa, shown in . | norm:sstatus_uxl |
| sstatus_uxl_sz | When SXLEN=32, the UXL field does not exist, and UXLEN=32. When SXLEN=64, it is a WARL field that encodes the current value of UXLEN. In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN. | norm:sstatus_uxl_sz |
| SSTATUS_UXL_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| When SXLEN=32, the UXL field does not exist, and UXLEN=32. When SXLEN=64, it is a WARL field that encodes the current value of UXLEN. In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN. | norm:sstatus_uxl_sz | |
| sstatus_uxl_behavior | If UXLEN≠SXLEN, instructions executed in the narrower mode must ignore source register operand bits above the configured XLEN, and must sign-extend results to fill the widest supported XLEN in the destination register. | norm:sstatus_uxl_behavior |
| HINT_SXLEN | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., c.addi x8, 0. When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits SXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1. | norm:hint_sxlen | |
| sstatus_mxr_sz | The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable (R=1 in ) will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. | norm:sstatus_mxr |
| sstatus_mxr_acc | The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable (R=1 in ) will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. | norm:sstatus_mxr |
| sstatus_mxr_op | The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable (R=1 in ) will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. | norm:sstatus_mxr |
| sstatus_sum_sz | The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode. Note that S-mode can never execute instructions from user pages, regardless of the state of SUM. | norm:sstatus_sum |
| sstatus_sum_acc | The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode. Note that S-mode can never execute instructions from user pages, regardless of the state of SUM. | norm:sstatus_sum |
| sstatus_sum_op | The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode. Note that S-mode can never execute instructions from user pages, regardless of the state of SUM. | norm:sstatus_sum |
| sstatus_sum_satp_mode | SUM is read-only 0 if satp.MODE is read-only 0. | norm:sstatus_sum_satp_mode |
| SSTATUS_UBE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| The UBE bit is a WARL field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode. An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode. | norm:sstatus_ube | |
| sstatus_ube_sz | The UBE bit is a WARL field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode. An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode. | norm:sstatus_ube |
| sstatus_ube_acc | The UBE bit is a WARL field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode. An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode. | norm:sstatus_ube |
| sstatus_ube_op | The UBE bit is a WARL field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode. An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode. | norm:sstatus_ube |
| sstatus_ube_implicit | UBE has no effect on instruction fetches, which are implicit memory accesses that are always little-endian. | norm:sstatus_ube_implicit |
| sstatus_spelp_sz | Access to the SPELP field, added by Zicfilp, accesses the homonymous fields of mstatus when V=0, and the homonymous fields of vsstatus when V=1. | norm:sstatus_spelp |
| sstatus_spelp_acc | Access to the SPELP field, added by Zicfilp, accesses the homonymous fields of mstatus when V=0, and the homonymous fields of vsstatus when V=1. | norm:sstatus_spelp |
| sstatus_spelp_op | Access to the SPELP field, added by Zicfilp, accesses the homonymous fields of mstatus when V=0, and the homonymous fields of vsstatus when V=1. | norm:sstatus_spelp |
| sstatus_spelp_Zicfilp | Access to the SPELP field, added by Zicfilp, accesses the homonymous fields of mstatus when V=0, and the homonymous fields of vsstatus when V=1. | norm:sstatus_spelp |
| sstatus_sdt_sz | The S-mode-disable-trap (SDT) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M. | norm:sstatus_sdt |
| sstatus_sdt_acc | The S-mode-disable-trap (SDT) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M. | norm:sstatus_sdt |
| sstatus_sdt_op | The S-mode-disable-trap (SDT) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M. | norm:sstatus_sdt |
| sstatus_sdt_Ssdbltrp | The S-mode-disable-trap (SDT) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M. | norm:sstatus_sdt |
| SSTATUS_SDT_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| The S-mode-disable-trap (SDT) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M. | norm:sstatus_sdt | |
| sstatus_sdt_sstatus_sie_overwrite | When the SDT bit is set to 1 by an explicit CSR write, the SIE (Supervisor Interrupt Enable) bit is cleared to 0. This clearing occurs regardless of the value written, if any, to the SIE bit by the same write. The SIE bit can only be set to 1 by an explicit CSR write if the SDT bit is being set to 0 by the same write or is already 0. | norm:sstatus_sdt_sstatus_sie_overwrite |
| sstatus_sdt_trap | When a trap is to be taken into S-mode, if the SDT bit is currently 0, it is then set to 1, and the trap is delivered as expected. However, if SDT is already set to 1, then this is an unexpected trap. In the event of an unexpected trap, a double-trap exception trap is delivered into M-mode. To deliver this trap, the hart writes registers, except mcause and mtval2, with the same information that the unexpected trap would have written if it was taken into M-mode. The mtval2 register is then set to what would be otherwise written into the mcause register by the unexpected trap. The mcause register is set to 16, the double-trap exception code. | norm:sstatus_sdt_trap |
| sstatus_sdt_sret | An SRET instruction sets the SDT bit to 0. | norm:sstatus_sdt_sret |
| stvec_sz | The stvec register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). | norm:stvec |
| stvec_acc | The stvec register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). | norm:stvec |
| stvec_mode | The stvec register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). | norm:stvec |
| STVEC_MODE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:stvec_img | |
| STVEC_BASE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:stvec_img | |
| stvec_op | The BASE field in stvec is a field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field. | norm:stvec_op |
| stvec_sz_base | Note that the CSR contains only bits XLEN-1 through 2 of the address BASE. When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary. | norm:stvec_sz_base |
| sip_sz | The sip register is an SXLEN-bit read/write register containing information on pending interrupts, while sie is the corresponding SXLEN-bit read/write register containing interrupt enable bits. Interrupt cause number i (as reported in CSR scause, ) corresponds with bit i in both sip and sie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. | norm:sip_sie |
| sie_sz | The sip register is an SXLEN-bit read/write register containing information on pending interrupts, while sie is the corresponding SXLEN-bit read/write register containing interrupt enable bits. Interrupt cause number i (as reported in CSR scause, ) corresponds with bit i in both sip and sie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. | norm:sip_sie |
| sip_mode | The sip register is an SXLEN-bit read/write register containing information on pending interrupts, while sie is the corresponding SXLEN-bit read/write register containing interrupt enable bits. Interrupt cause number i (as reported in CSR scause, ) corresponds with bit i in both sip and sie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. | norm:sip_sie |
| sie_mode | The sip register is an SXLEN-bit read/write register containing information on pending interrupts, while sie is the corresponding SXLEN-bit read/write register containing interrupt enable bits. Interrupt cause number i (as reported in CSR scause, ) corresponds with bit i in both sip and sie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. | norm:sip_sie |
| sie_sip_supervisor_strap | An interrupt i will trap to S-mode if both of the following are true: (a) either the current privilege mode is S and the SIE bit in the sstatus register is set, or the current privilege mode has less privilege than S-mode; and (b) bit i is set in both sip and sie. | norm:sie_sip_supervisor_strap |
| sie_sip_strap_time_constraint | These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in sip, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including sip, sie and sstatus). | norm:sie_sip_strap_time_constraint |
| s_interrupt_priority | Interrupts to S-mode take priority over any interrupts to lower privilege modes. | norm:s_interrupt_priority |
| sip_acc | Each individual bit in register sip may be writable or may be read-only. |
norm:sip_acc |
| sip_op | When bit i in sip is writable, a pending interrupt i can be cleared by writing 0 to this bit. If interrupt i can become pending but bit i in sip is read-only, the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment). |
norm:sip_op |
| sie_acc | A bit in sie must be writable if the corresponding interrupt can ever become pending. Bits of sie that are not writable are read-only zero. |
norm:sie_acc |
| sip_sie_bits_sz | The standard portions (bits 15:0) of registers sip and sie are formatted as shown in Figures and respectively. | norm:sip_sie_bits_sz |
| sip_seip_acc | Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller. | norm:sip_seip_sie_seie |
| sip_seip_op | Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller. | norm:sip_seip_sie_seie |
| sie_seie_acc | Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller. | norm:sip_seip_sie_seie |
| sie_seie_op | Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller. | norm:sip_seip_sie_seie |
| sip_stip_acc | Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip. When the Sstc extension is not implemented, STIP is set and cleared by the execution environment. When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from stimecmp. The sip.STIP bit, in response to timer interrupts generated by stimecmp, is set by writing stimecmp with a value that is less than or equal to time, and is cleared by writing stimecmp with a value greater than time. | norm:sip_stip_sie_stie |
| A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the mip and sip registers whenever time contains a value greater than or equal to stimecmp, treating the values as unsigned integers. If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, but not necessarily immediately. The interrupt remains posted until stimecmp becomes greater than time, typically as a result of writing stimecmp. The interrupt will be taken based on the standard interrupt enable and delegation rules. | norm:mip_sip_stip_op | |
| sip_stip_op | Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip. When the Sstc extension is not implemented, STIP is set and cleared by the execution environment. When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from stimecmp. The sip.STIP bit, in response to timer interrupts generated by stimecmp, is set by writing stimecmp with a value that is less than or equal to time, and is cleared by writing stimecmp with a value greater than time. | norm:sip_stip_sie_stie |
| A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the mip and sip registers whenever time contains a value greater than or equal to stimecmp, treating the values as unsigned integers. If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, but not necessarily immediately. The interrupt remains posted until stimecmp becomes greater than time, typically as a result of writing stimecmp. The interrupt will be taken based on the standard interrupt enable and delegation rules. | norm:mip_sip_stip_op | |
| sie_stie_acc | Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip. When the Sstc extension is not implemented, STIP is set and cleared by the execution environment. When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from stimecmp. The sip.STIP bit, in response to timer interrupts generated by stimecmp, is set by writing stimecmp with a value that is less than or equal to time, and is cleared by writing stimecmp with a value greater than time. | norm:sip_stip_sie_stie |
| sie_stie_op | Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip. When the Sstc extension is not implemented, STIP is set and cleared by the execution environment. When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from stimecmp. The sip.STIP bit, in response to timer interrupts generated by stimecmp, is set by writing stimecmp with a value that is less than or equal to time, and is cleared by writing stimecmp with a value greater than time. | norm:sip_stip_sie_stie |
| sip_ssip_acc | Bits sip.SSIP and sie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller. | norm:sip_ssip_sie_ssie |
| sip_ssip_op | Bits sip.SSIP and sie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller. | norm:sip_ssip_sie_ssie |
| sie_ssie_acc | Bits sip.SSIP and sie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller. | norm:sip_ssip_sie_ssie |
| sie_ssie_op | Bits sip.SSIP and sie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller. | norm:sip_ssip_sie_ssie |
| sip_lcofip_Sscofpmf_acc | If the Sscofpmf extension is implemented, bits sip.LCOFIP and sie.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in sip and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the mhpmeventn.OF bits being set. If the Sscofpmf extension is not implemented, sip.LCOFIP and sie.LCOFIE are read-only zeros. | norm:sip_sie_Sscofpmf |
| sip_lcofip_Sscofpmf_op | If the Sscofpmf extension is implemented, bits sip.LCOFIP and sie.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in sip and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the mhpmeventn.OF bits being set. If the Sscofpmf extension is not implemented, sip.LCOFIP and sie.LCOFIE are read-only zeros. | norm:sip_sie_Sscofpmf |
| sie_lcofip_Sscofpmf_acc | If the Sscofpmf extension is implemented, bits sip.LCOFIP and sie.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in sip and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the mhpmeventn.OF bits being set. If the Sscofpmf extension is not implemented, sip.LCOFIP and sie.LCOFIE are read-only zeros. | norm:sip_sie_Sscofpmf |
| sie_lcofip_Sscofpmf_op | If the Sscofpmf extension is implemented, bits sip.LCOFIP and sie.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in sip and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the mhpmeventn.OF bits being set. If the Sscofpmf extension is not implemented, sip.LCOFIP and sie.LCOFIE are read-only zeros. | norm:sip_sie_Sscofpmf |
| SEI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| STI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| SSI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| LCOFI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| SIP_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| All bits in sip and sie are WARL fields. The implemented interrupts may be found by writing one to every bit location in sie, then reading back to see which bit positions hold a one. |
norm:sip_sie_warl | |
| SIE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| All bits in sip and sie are WARL fields. The implemented interrupts may be found by writing one to every bit location in sie, then reading back to see which bit positions hold a one. |
norm:sip_sie_warl | |
| sip_priority_bit_order | Multiple simultaneous interrupts destined for supervisor mode are handled in the following decreasing priority order: SEI, SSI, STI, LCOFI. | norm:sip_sie_priority_bit_order |
| sie_priority_bit_order | Multiple simultaneous interrupts destined for supervisor mode are handled in the following decreasing priority order: SEI, SSI, STI, LCOFI. | norm:sip_sie_priority_bit_order |
| supervisor_timer_scheduling | The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, time. | norm:supervisor_timer_scheduling |
| scounteren_sz | The counter-enable (scounteren) CSR is a 32-bit register that controls the availability of the hardware performance monitoring counters to U-mode. | norm:scounteren |
| scounteren_mode | The counter-enable (scounteren) CSR is a 32-bit register that controls the availability of the hardware performance monitoring counters to U-mode. | norm:scounteren |
| scounteren_acc | scounteren must be implemented. However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when executing in U-mode. Hence, they are effectively WARL fields. | norm:scounteren_acc |
| SCOUNTEREN_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| scounteren must be implemented. However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when executing in U-mode. Hence, they are effectively WARL fields. | norm:scounteren_acc | |
| scounteren_op | When the CY, TM, IR, or HPMn bit in the scounteren register is clear, attempts to read the cycle, time, instret, or hpmcountern register while executing in U-mode will cause an illegal-instruction exception. When one of these bits is set, access to the corresponding register is permitted. | norm:scounteren_op |
| sscratch_sz | The sscratch CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, sscratch is used to hold a pointer to the hart-local supervisor context while the hart is executing user code. At the beginning of a trap handler, software normally uses a CSRRW instruction to swap sscratch with an integer register to obtain an initial working register. | norm:sscratch |
| sscratch_acc | The sscratch CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, sscratch is used to hold a pointer to the hart-local supervisor context while the hart is executing user code. At the beginning of a trap handler, software normally uses a CSRRW instruction to swap sscratch with an integer register to obtain an initial working register. | norm:sscratch |
| sscratch_mode | The sscratch CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, sscratch is used to hold a pointer to the hart-local supervisor context while the hart is executing user code. At the beginning of a trap handler, software normally uses a CSRRW instruction to swap sscratch with an integer register to obtain an initial working register. | norm:sscratch |
| sepc_sz | sepc is an SXLEN-bit read/write CSR formatted as shown in . The low bit of sepc (sepc[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (sepc[1:0]) are always zero. | norm:sepc |
| sepc_acc | sepc is an SXLEN-bit read/write CSR formatted as shown in . The low bit of sepc (sepc[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (sepc[1:0]) are always zero. | norm:sepc |
| sepc_op | sepc is an SXLEN-bit read/write CSR formatted as shown in . The low bit of sepc (sepc[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (sepc[1:0]) are always zero. | norm:sepc |
| sepc_mode | sepc is an SXLEN-bit read/write CSR formatted as shown in . The low bit of sepc (sepc[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (sepc[1:0]) are always zero. | norm:sepc |
| sepc_op_mask_ialign32 | If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), then, whenever IALIGN=32, bit sepc[1] is masked on reads so that it appears to be 0. This masking occurs also for the implicit read by the SRET instruction. Though masked, sepc[1] remains writable when IALIGN=32. | norm:sepc_op_mask_ialign32 |
| sepc_acc_invalid_addr | sepc is a WARL register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid addresses. Prior to writing sepc, implementations may convert an invalid address into some other invalid address that sepc is capable of holding. | norm:sepc_acc_invalid_addr |
| SEPC_ACC_INVALID_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| sepc is a WARL register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid addresses. Prior to writing sepc, implementations may convert an invalid address into some other invalid address that sepc is capable of holding. | norm:sepc_acc_invalid_addr | |
| sepc_op_trap_write | When a trap is taken into S-mode, sepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, sepc is never written by the implementation, though it may be explicitly written by software. | norm:sepc_op_trap_write |
| scause_sz | The scause CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, scause is written with a code indicating the event that caused the trap. Otherwise, scause is never written by the implementation, though it may be explicitly written by software. | norm:scause |
| scause_acc | The scause CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, scause is written with a code indicating the event that caused the trap. Otherwise, scause is never written by the implementation, though it may be explicitly written by software. | norm:scause |
| scause_op | The scause CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, scause is written with a code indicating the event that caused the trap. Otherwise, scause is never written by the implementation, though it may be explicitly written by software. | norm:scause |
| scause_interrupt_sz | The Interrupt bit in the scause register is set if the trap was caused by an interrupt. The Exception Code field contains a code identifying the last exception or interrupt. lists the possible exception codes for the current supervisor ISAs. The Exception Code is a WLRL field. It is required to hold the values 0–31 (i.e., bits 4–0 must be implemented), but otherwise it is only guaranteed to hold supported exception codes. | norm:scause_interrupt |
| scause_interrupt_op | The Interrupt bit in the scause register is set if the trap was caused by an interrupt. The Exception Code field contains a code identifying the last exception or interrupt. lists the possible exception codes for the current supervisor ISAs. The Exception Code is a WLRL field. It is required to hold the values 0–31 (i.e., bits 4–0 must be implemented), but otherwise it is only guaranteed to hold supported exception codes. | norm:scause_interrupt |
| SCAUSE_EXCEPTION_CODE_ACC | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WLRL | Implementation-defined behavior category | |
| The Exception Code is a WLRL field. |
norm:scause_exception_code_acc | |
| scause_exception_code_sz | It is required to hold the values 0–31 (i.e., bits 4–0 must be implemented), but otherwise it is only guaranteed to hold supported exception codes. |
norm:scause_exception_code_sz |
| stval_sz | The stval CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. Otherwise, stval is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set stval informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception. | norm:stval |
| stval_op | The stval CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. Otherwise, stval is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set stval informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception. | norm:stval |
| stval_mode | The stval CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. Otherwise, stval is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set stval informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception. | norm:stval |
| stval_op_faulting_addr | If stval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then stval will contain the faulting virtual address. | norm:stval_op_faulting_addr |
| stval_op_breakpoint | On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, stval is written with either zero or the virtual address of the instruction. | norm:stval_op_breakpoint |
| stval_op_load_store_fault | If stval is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then stval will contain the virtual address of the portion of the access that caused the fault. | norm:stval_op_load_store_fault |
| stval_faulting_address_variable_instr | If stval is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then stval will contain the virtual address of the portion of the instruction that caused the fault, while sepc will point to the beginning of the instruction. | norm:stval_faulting_address_variable_instr |
| stval_op_illegal_instr | The stval register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (sepc points to the faulting instruction in memory). If stval is written with a nonzero value when an illegal-instruction exception occurs, then stval will contain the shortest of: | norm:stval_op_illegal_instr |
| stval_op_illegal_instr_format | The value loaded into stval on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero. | norm:stval_op_illegal_instr_format |
| stval_exception_info | On a trap caused by a software-check exception, the stval register holds the cause for the exception. The following encodings are defined: | norm:stval_exception_info |
| stval_op_other_traps | For other traps, stval is set to zero, but a future standard may redefine stval’s setting for other traps. | norm:stval_op_other_traps |
| stval_acc | stval is a WARL register that must be able to hold all valid virtual addresses and the value 0. It need not be capable of holding all possible invalid addresses. Prior to writing stval, implementations may convert an invalid address into some other invalid address that stval is capable of holding. If the feature to return the faulting instruction bits is implemented, stval must also be able to hold all values less than 2N, where N is the smaller of SXLEN and ILEN. | norm:stval_acc |
| STVAL_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| stval is a WARL register that must be able to hold all valid virtual addresses and the value 0. It need not be capable of holding all possible invalid addresses. Prior to writing stval, implementations may convert an invalid address into some other invalid address that stval is capable of holding. If the feature to return the faulting instruction bits is implemented, stval must also be able to hold all values less than 2N, where N is the smaller of SXLEN and ILEN. | norm:stval_acc | |
| senvcfg_sz | The senvcfg CSR is an SXLEN-bit read/write register, formatted as shown in , that controls certain characteristics of the U-mode execution environment. | norm:senvcfg |
| senvcfg_acc | The senvcfg CSR is an SXLEN-bit read/write register, formatted as shown in , that controls certain characteristics of the U-mode execution environment. | norm:senvcfg |
| senvcfg_mode | The senvcfg CSR is an SXLEN-bit read/write register, formatted as shown in , that controls certain characteristics of the U-mode execution environment. | norm:senvcfg |
| senvcfg_fiom_sz | If bit FIOM (Fence of I/O implies Memory) is set to one in senvcfg, FENCE instructions executed in U-mode are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1. | norm:senvcfg_fiom |
| senvcfg_fiom_op | If bit FIOM (Fence of I/O implies Memory) is set to one in senvcfg, FENCE instructions executed in U-mode are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1. | norm:senvcfg_fiom |
| senvcfg_fiom_op_atomic | Similarly, for U-mode when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory. | norm:senvcfg_fiom_op_atomic |
| senvcfg_fiom_acc | If satp.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero. | norm:senvcfg_fiom_acc |
| senvcfg_pmm_Ssnpm | If the Ssnpm extension is implemented, the PMM field enables or disables pointer masking (see ) for the next-lower privilege mode (U/VU), according to the values in . If Ssnpm is not implemented, PMM is read-only zero. The PMM field is read-only zero for RV32. | norm:senvcfg_pmm_Ssnpm |
| senvcfg_lpe_Zicfilp_acc | The Zicfilp extension adds the LPE field in senvcfg. When the LPE field is set to 1, the Zicfilp extension is enabled in VU/U-mode. When the LPE field is 0, the Zicfilp extension is not enabled in VU/U-mode and the following rules apply to VU/U-mode: | norm:senvcfg_lpe_Zicfilp |
| senvcfg_lpe_Zicfilp_op | The Zicfilp extension adds the LPE field in senvcfg. When the LPE field is set to 1, the Zicfilp extension is enabled in VU/U-mode. When the LPE field is 0, the Zicfilp extension is not enabled in VU/U-mode and the following rules apply to VU/U-mode: | norm:senvcfg_lpe_Zicfilp |
| senvcfg_sse_Zicfilp_sz | The Zicfiss extension adds the SSE field in senvcfg. When the SSE field is set to 1, the Zicfiss extension is activated in VU/U-mode. When the SSE field is 0, the Zicfiss extension remains inactive in VU/U-mode, and the following rules apply: | norm:senvcfg_sse_Zicfilp |
| senvcfg_sse_Zicfilp_op | The Zicfiss extension adds the SSE field in senvcfg. When the SSE field is set to 1, the Zicfiss extension is activated in VU/U-mode. When the SSE field is 0, the Zicfiss extension remains inactive in VU/U-mode, and the following rules apply: | norm:senvcfg_sse_Zicfilp |
| satp_sz | The satp CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection. This register holds the physical page number (PPN) of the root page table, i.e., its supervisor physical address divided by 4 KiB; an address space identifier (ASID), which facilitates address-translation fences on a per-address-space basis; and the MODE field, which selects the current address-translation scheme. Further details on the access to this register are described in . | norm:satp |
| satp_acc | The satp CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection. This register holds the physical page number (PPN) of the root page table, i.e., its supervisor physical address divided by 4 KiB; an address space identifier (ASID), which facilitates address-translation fences on a per-address-space basis; and the MODE field, which selects the current address-translation scheme. Further details on the access to this register are described in . | norm:satp |
| satp_op | The satp CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection. This register holds the physical page number (PPN) of the root page table, i.e., its supervisor physical address divided by 4 KiB; an address space identifier (ASID), which facilitates address-translation fences on a per-address-space basis; and the MODE field, which selects the current address-translation scheme. Further details on the access to this register are described in . | norm:satp |
| satp_mode | The satp CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection. This register holds the physical page number (PPN) of the root page table, i.e., its supervisor physical address divided by 4 KiB; an address space identifier (ASID), which facilitates address-translation fences on a per-address-space basis; and the MODE field, which selects the current address-translation scheme. Further details on the access to this register are described in . | norm:satp |
| satp_mode_sz | shows the encodings of the MODE field when SXLEN=32 and SXLEN=64. When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme described in . To select MODE=Bare, software must write zero to the remaining fields of satp (bits 30–0 when SXLEN=32, or bits 59–0 when SXLEN=64). Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on address translation and protection behavior. | norm:satp_mode |
| satp_mode_acc | shows the encodings of the MODE field when SXLEN=32 and SXLEN=64. When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme described in . To select MODE=Bare, software must write zero to the remaining fields of satp (bits 30–0 when SXLEN=32, or bits 59–0 when SXLEN=64). Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on address translation and protection behavior. | norm:satp_mode |
| satp_mode_op | shows the encodings of the MODE field when SXLEN=32 and SXLEN=64. When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme described in . To select MODE=Bare, software must write zero to the remaining fields of satp (bits 30–0 when SXLEN=32, or bits 59–0 when SXLEN=64). Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on address translation and protection behavior. | norm:satp_mode |
| satp_mode_sxlen32 | When SXLEN=32, the only other valid setting for MODE is Sv32, a paged virtual-memory scheme described in . | norm:satp_mode_sxlen32 |
| satp_mode_sxlen64 | When SXLEN=64, three paged virtual-memory schemes are defined: Sv39, Sv48, and Sv57, described in , , and , respectively. One additional scheme, Sv64, will be defined in a later version of this specification. The remaining MODE settings are reserved for future use and may define different interpretations of the other fields in satp. | norm:satp_mode_sxlen64 |
| satp_mode_op_unsupported | Implementations are not required to support all MODE settings, and if satp is written with an unsupported MODE, the entire write has no effect; no fields in satp are modified. | norm:satp_mode_op_unsupported |
| ASIDLEN | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The number of ASID bits is UNSPECIFIED and may be zero. The number of implemented ASID bits, termed ASIDLEN, may be determined by writing one to every bit position in the ASID field, then reading back the value in satp to see which bit positions in the ASID field hold a one. The least-significant bits of ASID are implemented first: that is, if ASIDLEN > 0, ASID[ASIDLEN-1:0] is writable. The maximal value of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57. | norm:asidlen | |
| satp_op_active | The satp CSR is considered active when the effective privilege mode is S-mode or U-mode. Executions of the address-translation algorithm may only begin using a given value of satp when satp is active. | norm:satp_op_active |
| satp_op_sfence_vma | Note that writing satp does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches. If the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to execute an SFENCE.VMA instruction (see ) after, or in some cases before, writing satp. | norm:satp_op_sfence_vma |
| sfence_vma_op | The supervisor memory-management fence instruction SFENCE.VMA is used to synchronize updates to in-memory memory-management data structures with current execution. Instruction execution causes implicit reads and writes to these data structures; however, these implicit references are ordinarily not ordered with respect to explicit loads and stores. Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory-management data structures. The specific set of operations ordered by SFENCE.VMA is determined by rs1 and rs2, as described below. SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see ). Further details on the behavior of this instruction are described in and . | norm:sfence_vma_op |
| sfence_vma_ordering | Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory-management data structures. The specific set of operations ordered by SFENCE.VMA is determined by rs1 and rs2, as described below. |
norm:sfence_vma_ordering |
| sfence_vma_invalidation | SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see sv32algorithm). |
norm:sfence_vma_invalidation |
| sfence_vma_all_asid_va | If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. The fence also invalidates all address-translation cache entries, for all address spaces. |
norm:sfence_vma_all_asid_va |
| sfence_vma_asid_only | If rs1=x0 and rs2{ne}x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see translation) are not ordered. The fence also invalidates all address-translation cache entries matching the address space identified by integer register rs2, except for entries containing global mappings. |
norm:sfence_vma_asid_only |
| sfence_vma_va_all_asid | If rs1{ne}x0 and rs2=x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for all address spaces. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1, for all address spaces. |
norm:sfence_vma_va_all_asid |
| sfence_vma_va_asid | If rs1{ne}x0 and rs2{ne}x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1 and that match the address space identified by integer register rs2, except for entries containing global mappings. |
norm:sfence_vma_va_asid |
| sfence_vma_invalid_va | If the value held in rs1 is not a valid virtual address, then the SFENCE.VMA instruction has no effect. No exception is raised in this case. | norm:sfence_vma_invalid_va |
| sfence_vma_rs2_bits | When rs2≠x0, bits SXLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use. Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations. Furthermore, if ASIDLEN<ASIDMAX, the implementation shall ignore bits ASIDMAX-1:ASIDLEN of the value held in rs2. | norm:sfence_vma_rs2_bits |
| sfence_vma_ordering_semantics | An implicit read of the memory-management data structures may return any translation for an address that was valid at any time since the most recent SFENCE.VMA that subsumes that address. The ordering implied by SFENCE.VMA does not place implicit reads and writes to the memory-management data structures into the global memory order in a way that interacts cleanly with the standard RVWMO ordering rules. In particular, even though an SFENCE.VMA orders prior explicit accesses before subsequent implicit accesses, and those implicit accesses are ordered before their associated explicit accesses, SFENCE.VMA does not necessarily place prior explicit accesses before subsequent explicit accesses in the global memory order. These implicit loads also need not otherwise obey normal program order semantics with respect to prior loads or stores to the same address. | norm:sfence_vma_ordering_semantics |
| sfence_vma_implicit_access | Implementations must only perform implicit reads of the translation data structures pointed to by the current contents of the satp register or a subsequent valid (V=1) translation data structure entry, and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively. | norm:sfence_vma_implicit_access |
| sfence_vma_sum_mxr_effect | Changes to the sstatus fields SUM and MXR take effect immediately, without the need to execute an SFENCE.VMA instruction. |
norm:sfence_vma_sum_mxr_effect |
| sfence_vma_mode_effect | Changing satp.MODE from Bare to other modes and vice versa also takes effect immediately, without the need to execute an SFENCE.VMA instruction. |
norm:sfence_vma_mode_effect |
| sfence_vma_asid_effect | Likewise, changes to satp.ASID take effect immediately. | norm:sfence_vma_asid_effect |
| asid_hart_private | If a hart employs an address-translation cache, that cache must appear to be private to that hart. In particular, the meaning of an ASID is local to a hart; software may choose to use the same ASID to refer to different address spaces on different harts. | norm:asid_hart_private |
| SATP_MODE_ROZ_SFENCE_ILLEGAL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| For implementations that make satp.MODE read-only zero (always Bare), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception. | norm:satp_mode_roz_sfence_illegal | |
| fetch_page_fault_no_x | Attempting to fetch an instruction from a page that does not have execute permissions raises a fetch page-fault exception. |
norm:fetch_page_fault_no_x |
| load_page_fault_no_r | Attempting to execute a load, load-reserved, or cache-block management instruction whose effective address lies within a page without read permissions raises a load page-fault exception. |
norm:load_page_fault_no_r |
| store_page_fault_no_w | Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction instruction whose effective address lies within a page without write permissions raises a store page-fault exception. |
norm:store_page_fault_no_w |
| Sv39_sxlen | simple paged virtual-memory system for SXLEN=64 |
norm:Sv39_sxlen |
| Sv39_va_sz | supports 39-bit virtual address spaces | norm:Sv39_va_sz |
| Sv39_va_signext | must have bits 63–39 all equal to bit 38, or else a page-fault exception will occur |
norm:Sv39_va_signext |
| Sv39_vpn_sz | 27-bit VPN | norm:Sv39_vpn_sz |
| satp_ppn_sv39_sz | 44-bit PPN | norm:satp_ppn_sv39_sz |
| Sv39_levels | three-level page table | norm:Sv39_levels |
| Sv39_page_offset_sz | 12-bit page offset is untranslated | norm:Sv39_page_offset_sz |
| Sv39_pte_count | 29 page table entries (PTEs) |
norm:Sv39_pte_count |
| Sv39_pte_sz | eight bytes each | norm:Sv39_pte_sz |
| Sv39_pt_sz | exactly the size of a page | norm:Sv39_pt_sz |
| Sv39_pt_align | must always be aligned to a page boundary | norm:Sv39_pt_align |
| Sv39_pte_svnapot_rsv | If Svnapot is not implemented, bit 63 remains reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised |
norm:Sv39_pte_svnapot_rsv |
| Sv39_pte_svpbmt_rsv | If Svpbmt is not implemented, bits 62-61 remain reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised |
norm:Sv39_pte_svpbmt_rsv |
| Sv39_pte_future_rsv | must be zeroed by software for forward compatibility. If any of these bits are set, a page-fault exception is raised |
norm:Sv39_pte_future_rsv |
| Sv39_leaf_any_level | Any level of PTE may be a leaf PTE | norm:Sv39_leaf_any_level |
| Sv39_page_sizes | 2 MiB megapages and 1 GiB gigapages | norm:Sv39_page_sizes |
| Sv39_superpage_align | must be virtually and physically aligned to a boundary equal to its size |
norm:Sv39_superpage_align |
| Sv39_superpage_align_fault | A page-fault exception is raised if the physical address is insufficiently aligned |
norm:Sv39_superpage_align_fault |
| Sv39_LEVELS | LEVELS equals 3 | norm:Sv39_LEVELS |
| Sv39_PTESIZE | PTESIZE equals 8 | norm:Sv39_PTESIZE |
| Sv48_sxlen | SXLEN=64 | norm:Sv48_sxlen |
| Sv48_va_sz | 48-bit virtual address spaces | norm:Sv48_va_sz |
| Sv48_requires_Sv39 | Implementations that support Sv48 must also support Sv39 |
norm:Sv48_requires_Sv39 |
| Sv48_va_signext | must have bits 63–48 all equal to bit 47, or else a page-fault exception will occur |
norm:Sv48_va_signext |
| Sv48_vpn_sz | 36-bit VPN | norm:Sv48_vpn_sz |
| satp_ppn_sv48_sz | 44-bit PPN | norm:satp_ppn_sv48_sz |
| Sv48_levels | four-level page table | norm:Sv48_levels |
| Sv48_page_offset_sz | 12-bit page offset is untranslated | norm:Sv48_page_offset_sz |
| Sv48_leaf_any_level | Any level of PTE may be a leaf PTE | norm:Sv48_leaf_any_level |
| Sv48_page_sizes | 2 MiB megapages, 1 GiB gigapages, and 512 GiB terapages |
norm:Sv48_page_sizes |
| Sv48_superpage_align | must be virtually and physically aligned to a boundary equal to its size |
norm:Sv48_superpage_align |
| Sv48_superpage_align_fault | A page-fault exception is raised if the physical address is insufficiently aligned |
norm:Sv48_superpage_align_fault |
| Sv48_LEVELS | LEVELS equals 4 | norm:Sv48_LEVELS |
| Sv48_PTESIZE | PTESIZE equals 8 | norm:Sv48_PTESIZE |
| Sv57_sxlen | RV64 systems | norm:Sv57_sxlen |
| Sv57_va_sz | 57-bit virtual address spaces | norm:Sv57_va_sz |
| Sv57_requires_Sv48 | Implementations that support Sv57 must also support Sv48 |
norm:Sv57_requires_Sv48 |
| Sv57_va_signext | must have bits 63–57 all equal to bit 56, or else a page-fault exception will occur |
norm:Sv57_va_signext |
| Sv57_vpn_sz | 45-bit VPN | norm:Sv57_vpn_sz |
| satp_ppn_sv57_sz | 44-bit PPN | norm:satp_ppn_sv57_sz |
| Sv57_levels | five-level page table | norm:Sv57_levels |
| Sv57_page_offset_sz | 12-bit page offset is untranslated | norm:Sv57_page_offset_sz |
| Sv57_leaf_any_level | Any level of PTE may be a leaf PTE | norm:Sv57_leaf_any_level |
| Sv57_page_sizes | 2 MiB megapages, 1 GiB gigapages, 512 GiB terapages, and 256 TiB petapages |
norm:Sv57_page_sizes |
| Sv57_superpage_align | must be virtually and physically aligned to a boundary equal to its size |
norm:Sv57_superpage_align |
| Sv57_superpage_align_fault | A page-fault exception is raised if the physical address is insufficiently aligned |
norm:Sv57_superpage_align_fault |
| Sv57_LEVELS | LEVELS equals 5 | norm:Sv57_LEVELS |
| Sv57_PTESIZE | PTESIZE equals 8 | norm:Sv57_PTESIZE |
| Svnapot_depends_Sv39 | The Svnapot extension depends on the Sv39 extension |
norm:Svnapot_depends_Sv39 |
| Svnapot_pte_N | N=1 | norm:Svnapot_pte_N |
| Svnapot_range_napot | Such ranges must be of a naturally aligned power-of-2 (NAPOT) granularity larger than the base page size |
norm:Svnapot_range_napot |
| Svnapot_valid_encoding | valid according to ptenapot | norm:Svnapot_valid_encoding |
| Svnapot_reserved_encoding_fault | reserved according to ptenapot, then a page-fault exception must be raised |
norm:Svnapot_reserved_encoding_fault |
| Svnapot_implicit_read_ppn_subst | implicit reads of a NAPOT PTE return a copy of pte in which pte.ppn[i][pte.napot_bits-1:0] is replaced by vpn[i][pte.napot_bits-1:0] |
norm:Svnapot_implicit_read_ppn_subst |
| Svnapot_cache_entries | Implicit reads of NAPOT page table entries may create address-translation cache entries mapping a + j×PTESIZE to a copy of pte in which pte.ppn[i][pte.napot_bits-1:0] is replaced by vpn[i][pte.napot_bits-1:0], for any or all j such that j >> napot_bits = vpn[i] >> napot_bits, all for the address space identified in satp as loaded by step 1 |
norm:Svnapot_cache_entries |
| Svnapot_hyp_gstage | Svnapot is also supported in G-stage translation |
norm:Svnapot_hyp_gstage |
| Svpbmt_depends_Sv39 | The Svpbmt extension depends on the Sv39 extension | norm:Svpbmt_depends_Sv39 |
| Svpbmt_impl_may_override_pmas | Implementations may override additional PMAs not explicitly listed in pbmt. |
norm:Svpbmt_impl_may_override_pmas |
| Svpbmt_nonleaf_pte_pbmt_must_be_zero | Until their use is defined by a standard extension, they must be cleared by software for forward compatibility, or else a page-fault exception is raised. |
norm:Svpbmt_nonleaf_pte_pbmt_must_be_zero |
| Svpbmt_leaf_pte_pbmt_reserved_3_fault | Until this value is defined by a standard extension, using this reserved value in a leaf PTE raises a page-fault exception. |
norm:Svpbmt_leaf_pte_pbmt_reserved_3_fault |
| Svpbmt_obeys_mem_ordering | memory accesses to such pages obey the memory ordering rules of the final effective attribute, |
norm:Svpbmt_obeys_mem_ordering |
| Svpbmt_io_pma_nc_pbmt_obey_rvwmo | If the underlying physical memory attribute for a page is I/O, and the page has PBMT=NC, then accesses to that page obey RVWMO. |
norm:Svpbmt_io_pma_nc_pbmt_obey_rvwmo |
| Svpbmt_io_pma_nc_pbmt_treated_as_io_and_memory | accesses to such pages are considered to be both I/O and main memory accesses for the purposes of FENCE, .aq, and .rl. |
norm:Svpbmt_io_pma_nc_pbmt_treated_as_io_and_memory |
| Svpbmt_memory_pma_io_pbmt_strong_io_ordering | accesses to that page obey strong channel 0 I/O ordering rules. |
norm:Svpbmt_memory_pma_io_pbmt_strong_io_ordering |
| Svpbmt_memory_pma_io_pbmt_treated_as_io_and_memory | accesses to such pages are considered to be both I/O and main memory accesses for the purposes of FENCE, .aq, and .rl. |
norm:Svpbmt_memory_pma_io_pbmt_treated_as_io_and_memory |
| Svpbmt_aliasing_attribute | When Svpbmt is used with non-zero PBMT encodings, it is possible for multiple virtual aliases of the same physical page to exist simultaneously with different memory attributes. It is also possible for a U-mode or S-mode mapping through a PTE with Svpbmt enabled to observe different memory attributes for a given region of physical memory than a concurrent access to the same page performed by M-mode or when MODE=Bare. In such cases, the behaviors dictated by the attributes (including coherence, which is otherwise unaffected) may be violated. |
norm:Svpbmt_aliasing_attribute |
| Svpbmt_noncacheable_aliasing_no_coherence_loss | Accessing the same location using different attributes that are both non-cacheable (e.g., NC and IO) does not cause loss of coherence, |
norm:Svpbmt_noncacheable_aliasing_no_coherence_loss |
| Svpbmt_noncacheable_aliasing_may_weaken_ordering | might result in weaker memory ordering than the stricter attribute ordinarily guarantees. |
norm:Svpbmt_noncacheable_aliasing_may_weaken_ordering |
| Svpbmt_noncacheable_aliasing_fence_prevents_ordering_loss | fence iorw, iorw instruction between such accesses suffices to prevent loss of memory ordering. |
norm:Svpbmt_noncacheable_aliasing_fence_prevents_ordering_loss |
| Svpbmt_cacheable_aliasing_may_cause_coherence_loss | may cause loss of coherence. |
norm:Svpbmt_cacheable_aliasing_may_cause_coherence_loss |
| Svpbmt_cacheable_aliasing_fence_flush_fence_required | prevents both loss of coherence and loss of memory ordering: | norm:Svpbmt_cacheable_aliasing_fence_flush_fence_required |
| Svpbmt_hgatp_stage_override_rule | if hgatp.MODE is not equal to zero, non-zero G-stage PTE PBMT bits override the attributes in the PMA to produce an intermediate set of attributes. |
norm:Svpbmt_hgatp_stage_override_rule |
| Svpbmt_vsatp_stage_override_rule | if vsatp.MODE is not equal to zero, non-zero VS-stage PTE PBMT bits override the intermediate attributes to produce the final set of attributes used by accesses to the page in question. |
norm:Svpbmt_vsatp_stage_override_rule |
| Svinval_split_fine_grained | that can be more efficiently batched or pipelined on certain classes of high-performance implementation. |
norm:Svinval_split_fine_grained |
| Svinval_sinval_vma_invalidates_same_as_sfence_vma | However, unlike SFENCE.VMA, SINVAL.VMA instructions are only ordered with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR instructions as defined below. |
norm:Svinval_sinval_vma_invalidates_same_as_sfence_vma |
| Svinval_sfence_w_inval_orders_before_sinval_vma | The SFENCE.INVAL.IR instruction guarantees that any previous SINVAL.VMA instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures. |
norm:Svinval_sfence_w_inval_orders_before_sinval_vma |
| Svinval_sequence_rs1_rs2 | the values of rs1 and rs2 for the SFENCE.VMA are the same as those used in the SINVAL.VMA, |
norm:Svinval_sequence_rs1_rs2 |
| Svinval_sequence_reads_writes_before | reads and writes prior to the SFENCE.W.INVAL are considered to be those prior to the SFENCE.VMA, |
norm:Svinval_sequence_reads_writes_before |
| Svinval_sequence_reads_writes_after | reads and writes following the SFENCE.INVAL.IR are considered to be those subsequent to the SFENCE.VMA. |
norm:Svinval_sequence_reads_writes_after |
| Svinval_hinval_vvma_gvma | These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA. |
norm:Svinval_hinval_vvma_gvma |
| Svinval_hinval_gvma_uses_vmid | HINVAL.GVMA uses VMIDs instead of ASIDs. | norm:Svinval_hinval_gvma_uses_vmid |
| Svinval_illegal_instruction_u_mode | In particular, an attempt to execute any of these instructions in U-mode always raises an illegal-instruction exception. |
norm:Svinval_illegal_instruction_u_mode |
| Svinval_illegal_instruction_tvm | An attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when mstatus.TVM=1 also raises an illegal-instruction exception. |
norm:Svinval_illegal_instruction_tvm |
| Svinval_virtual_instruction_vu_vs | An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual-instruction exception. |
norm:Svinval_virtual_instruction_vu_vs |
| Svinval_virtual_instruction_vtvms | When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual-instruction exception. |
norm:Svinval_virtual_instruction_vtvms |
| Svinval_sfence_w_inval_inval_u_mode | raises an illegal-instruction exception. | norm:Svinval_sfence_w_inval_inval_u_mode |
| Svinval_sfence_w_inval_inval_vu_mode | Doing so in VU-mode raises a virtual-instruction exception. | norm:Svinval_sfence_w_inval_inval_vu_mode |
| Svinval_sfence_w_inval_inval_s_vs_mode | SFENCE.W.INVAL and SFENCE.INVAL.IR are unaffected by the mstatus.TVM and hstatus.VTVM fields and hence are always permitted in S-mode and VS-mode. |
norm:Svinval_sfence_w_inval_inval_s_vs_mode |
| Svadu_hw_update_a_d_bits | If the Svadu extension is implemented, the menvcfg.ADUE field is writable. | norm:Svadu_hw_update_a_d_bits |
| Svadu_hypervisor_adue_writable | If the hypervisor extension is additionally implemented, the henvcfg.ADUE field is also writable. |
norm:Svadu_hypervisor_adue_writable |
| Svadu_disabled_hw_update_falls_back_to_svade | When hardware updating of A/D bits is disabled, the Svade extension, which mandates exceptions when A/D bits need be set, instead takes effect. |
norm:Svadu_disabled_hw_update_falls_back_to_svade |
| Svvptc_explicit_stores_update_valid_bit | When the Svvptc extension is implemented, explicit stores by a hart that update the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will eventually become visible within a bounded timeframe to subsequent implicit accesses by that hart to such PTEs. |
norm:Svvptc_explicit_stores_update_valid_bit |
| Svrsw60t59b_reserved_bits_60_59 | If the Svrsw60t59b extension is implemented, then bits 60-59 of the page table entries (PTEs) are reserved for use by supervisor software and are ignored by the implementation. |
norm:Svrsw60t59b_reserved_bits_60_59 |
| Svrsw60t59b_h_g_stage_reserved_bits | If the Hypervisor (H) extension is also implemented, then bits 60-59 of the G-stage PTEs are reserved for use by supervisor software and are ignored by the implementation. |
norm:Svrsw60t59b_h_g_stage_reserved_bits |
| Svrsw60t59b_depends_on_sv39 | The Svrsw60t59b extension depends on Sv39. | norm:Svrsw60t59b_depends_on_sv39 |
| Ssqosid_shared_resource_need_management | When multiple workloads execute concurrently on modern processors—equipped with large core counts, multiple cache hierarchies, and multiple memory controllers— the performance of any given workload becomes less deterministic, or even non-deterministic, due to shared resource contention. |
norm:Ssqosid_shared_resource_need_management |
| Ssqosid_hw_monitoring_required | To manage performance variability, system software needs resource allocation and monitoring capabilities. These capabilities allow for the reservation of resources like cache and bandwidth, thus meeting individual performance targets while minimizing interference. |
norm:Ssqosid_hw_monitoring_required |
| Ssqosid_srmcfg_introduced | To facilitate this, the QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. |
norm:Ssqosid_srmcfg_introduced |
| Ssqosid_metadata_used_by_controllers | Additional metadata, like the nature of the memory access and the ID of the originating supervisor domain, can accompany RCID and MCID. Resource controllers may use this metadata for differentiated service such as a different capacity allocation for code storage vs. data storage. Resource controllers can use this data for security policies such as not exposing statistics of one security domain to another. |
norm:Ssqosid_metadata_used_by_controllers |
| Ssqosid_cbqri_spec | These identifiers are crucial for the RISC-V Capacity and Bandwidth Controller QoS Register Interface (CBQRI) specification, which provides methods for setting resource usage limits and monitoring resource consumption. The RCID controls resource allocations, while the MCID is used for tracking resource usage. |
norm:Ssqosid_cbqri_spec |
| Ssqosid_srmcfg_register_size | The srmcfg register is an SXLEN-bit read/write register used to configure a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). Both RCID and MCID are WARL fields. |
norm:Ssqosid_srmcfg_register_size |
| Ssqosid_rcid_mcid_accompany_requests | The RCID and MCID accompany each request made by the hart to shared resource controllers. The RCID is used to determine the resource allocations (e.g., cache occupancy limits, memory bandwidth limits, etc.) to enforce. The MCID is used to identify a counter to monitor resource usage. |
norm:Ssqosid_rcid_mcid_accompany_requests |
| Ssqosid_srmcfg_csr_applies_to_all_modes | The RCID and MCID configured in the srmcfg CSR apply to all privilege modes of software execution on that hart by default, but this behavior may be overridden by future extensions. |
norm:Ssqosid_srmcfg_csr_applies_to_all_modes |
| Ssqosid_smstateen_srmcfg_requires_mstateen0 | If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. |
norm:Ssqosid_smstateen_srmcfg_requires_mstateen0 |
| Ssqosid_srmcfg_access_illegal_instruction | If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. |
norm:Ssqosid_srmcfg_access_illegal_instruction |
| Ssqosid_srmcfg_access_virtual_instruction | If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception. |
norm:Ssqosid_srmcfg_access_virtual_instruction |
| stimecmp_stimecmph_sz_acc | stimecmp is a 63-bit CSR with 64-bit precision; RV32 accesses split into stimecmp and stimecmph | Rule's "summary" property |
| The stimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems. In RV32 only, accesses to the stimecmp CSR access the low 32 bits, while accesses to the stimecmph CSR access the high 32 bits of stimecmp. |
norm:stimecmp_stimecmph_sz_acc | |
| mip_stip_op | Supervisor timer interrupt becomes pending in mip/sip STIP when time >= stimecmp | Rule's "summary" property |
| A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the mip and sip registers whenever time contains a value greater than or equal to stimecmp, treating the values as unsigned integers. If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, but not necessarily immediately. The interrupt remains posted until stimecmp becomes greater than time, typically as a result of writing stimecmp. The interrupt will be taken based on the standard interrupt enable and delegation rules. | norm:mip_sip_stip_op | |
| senvcfg_cbze | The Zicboz extension adds the CBZE (Cache Block Zero instruction enable) field to senvcfg. The CBZE field controls execution of the cache block zero instruction (CBO.ZERO) in U-mode. Execution of CBO.ZERO in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and CBZE is set to 1; otherwise, an illegal-instruction exception is raised. When the Zicboz extension is not implemented, CBZE is read-only zero. | norm:senvcfg_cbze |
| senvcfg_cbcfe | The Zicbom extension adds the CBCFE (Cache Block Clean and Flush instruction Enable) field to senvcfg to control execution of the CBO.CLEAN and CBO.FLUSH instructions in U-mode. Execution of these instructions in U-mode is enabled only if execution of these instructions is enabled for use in S-mode and CBCFE is set to 1; otherwise, an illegal-instruction exception is raised. When the Zicbom extension is not implemented, CBCFE is read-only zero. | norm:senvcfg_cbcfe |
| senvcfg_cbie | The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to senvcfg to control execution of the CBO.INVAL instruction in U-mode. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. Execution of CBO.INVAL in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and CBIE is set to 01b or 11b; otherwise, an illegal-instruction exception is raised. | norm:senvcfg_cbie |
| SENVCFG_CBIE_WARL | extension | Rule's "kind" property |
| Zicboz | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to senvcfg to control execution of the CBO.INVAL instruction in U-mode. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. Execution of CBO.INVAL in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and CBIE is set to 01b or 11b; otherwise, an illegal-instruction exception is raised. | norm:senvcfg_cbie | |
| cbo-inval_s-mode_op | If CBO.INVAL is enabled in S-mode to perform a flush operation, then when the instruction is enabled in U-mode it performs a flush operation, even if CBIE is set to 11b. Otherwise, the instruction behaves as follows, depending on the CBIE encoding: |
norm:cbo-inval_s-mode_op0 |
| (No text available) | norm:cbo-inval_s-mode_op1 | |
| (No text available) | norm:cbo-inval_s-mode_op2 |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| ELEN | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The maximum size in bits of a vector element that any operation can produce or consume, ELEN {ge} 8, which must be a power of 2. |
norm:elen | |
| VLEN | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| The number of bits in a single vector register, VLEN {ge} ELEN, which must be a power of 2, and must be no greater than 216. | norm:vlen | |
| HW_MSTATUS_VS_DIRTY_UPDATE | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Implementations may also change mstatus.VS or vsstatus.VS from Initial or Clean to Dirty at any time, even when there is no change in vector state. |
norm:hw_mstatus_vs_dirty_update | |
| RESERVED_VILL_SET | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| [CONTEXT] Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if vill was 1 beforehand. | norm:vtype_vset_rsv | |
| Implementations may set vill in either case. | norm:reserved_vill_set | |
| vreg_count | The vector extension adds 32 architectural vector registers, v0-v31 to the base scalar RISC-V ISA. | norm:vreg_count |
| mstatus_vs_op_initial_clean | When mstatus.VS is set to Initial or Clean, executing any instruction that changes vector state, including the vector CSRs, will change mstatus.VS to Dirty. Implementations may also change mstatus.VS from Initial or Clean to Dirty at any time, even when there is no change in vector state. | norm:mstatus_vs_op_initial_clean |
| vsstatus_vs_mstatus_vs_op_off | When V=1, both vsstatus.VS and mstatus.VS are in effect: attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when either field is set to Off. | norm:vsstatus_vs_mstatus_vs_op_off |
| vsstatus_vs_sz | When the hypervisor extension is present, a vector context status field, VS, is added to vsstatus[10:9]. It is defined analogously to the floating-point context status field, FS. | norm:vsstatus_vs_sz_acc |
| vsstatus_vs_acc | When the hypervisor extension is present, a vector context status field, VS, is added to vsstatus[10:9]. It is defined analogously to the floating-point context status field, FS. | norm:vsstatus_vs_sz_acc |
| mstatus_vs_op_off | Attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when mstatus.VS is set to Off. | norm:mstatus_vs_op_off |
| mstatus_vs_op_active | When V=1 and neither vsstatus.VS nor mstatus.VS is set to Off, executing any instruction that changes vector state, including the vector CSRs, will change both mstatus.VS and vsstatus.VS to Dirty. |
norm:vsstatus_vs_mstatus_vs_op_active |
| sstatus_vs_op | A vector context status field, VS, is added to mstatus[10:9] and shadowed in sstatus[10:9]. It is defined analogously to the floating-point context status field, FS. | norm:mstatus_vs_sstatus_vs_op |
| vsstatus_vs_op2 | Similarly, when V=1, both vsstatus.VS and the HS-level sstatus.VS are in effect. Attempts to execute a vector instruction when either field is 0 (Off) raise an illegal-instruction exception. Modifying the vector state when V=1 causes both fields to be set to 3 (Dirty). | norm:vsstatus_vs_op |
| vsstatus_vs_op_off | When V=1, both vsstatus.VS and mstatus.VS are in effect: attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when either field is set to Off. | norm:vsstatus_vs_mstatus_vs_op_off |
| vsstatus_vs_op_active | When V=1 and neither vsstatus.VS nor mstatus.VS is set to Off, executing any instruction that changes vector state, including the vector CSRs, will change both mstatus.VS and vsstatus.VS to Dirty. |
norm:vsstatus_vs_mstatus_vs_op_active |
| vsstatus_sd_op_vs | If vsstatus.VS is Dirty, vsstatus.SD is 1; otherwise, vsstatus.SD is set in accordance with existing specifications. | norm:vsstatus_sd_op_vs |
| mstatus_sd_op_vs | If mstatus.VS is Dirty, mstatus.SD is 1; otherwise, mstatus.SD is set in accordance with existing specifications. | norm:mstatus_sd_op_vs |
| MUTABLE_MISA_V | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Implementations may have a writable misa.V field. | norm:mutable_misa_v | |
| MSTATUS_VS_EXISTS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Analogous to the way in which the floating-point unit is handled, the mstatus.VS field may exist even if misa.V is clear. |
norm:mstatus_vs_exists | |
| VSSTATUS_VS_EXISTS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| For implementations with a writable misa.V field, the vsstatus.VS field may exist even if misa.V is clear. | norm:vsstatus_vs_exists | |
| vtype_sz | The read-only XLEN-wide vector type CSR, vtype provides the default type used to interpret the contents of the vector register file, and can only be updated by vset{i}vl{i} instructions. |
norm:vtype_sz_acc_op |
| vtype_op | The read-only XLEN-wide vector type CSR, vtype provides the default type used to interpret the contents of the vector register file, and can only be updated by vset{i}vl{i} instructions. |
norm:vtype_sz_acc_op |
| vtype_vill_sz | The vtype register has five fields, vill, vma, vta, vsew[2:0], and vlmul[2:0]. Bits vtype[XLEN-2:8] should be written with zero, and non-zero values in this field are reserved. | norm:vtype_fields_sz |
| vtype_vma_sz | The vtype register has five fields, vill, vma, vta, vsew[2:0], and vlmul[2:0]. Bits vtype[XLEN-2:8] should be written with zero, and non-zero values in this field are reserved. | norm:vtype_fields_sz |
| vtype_vta_sz | The vtype register has five fields, vill, vma, vta, vsew[2:0], and vlmul[2:0]. Bits vtype[XLEN-2:8] should be written with zero, and non-zero values in this field are reserved. | norm:vtype_fields_sz |
| vtype_vsew_sz | The vtype register has five fields, vill, vma, vta, vsew[2:0], and vlmul[2:0]. Bits vtype[XLEN-2:8] should be written with zero, and non-zero values in this field are reserved. | norm:vtype_fields_sz |
| vtype_vlmul_sz | The vtype register has five fields, vill, vma, vta, vsew[2:0], and vlmul[2:0]. Bits vtype[XLEN-2:8] should be written with zero, and non-zero values in this field are reserved. | norm:vtype_fields_sz |
| vtype_vsew_op | The value in vsew sets the dynamic selected element width (SEW). By default, a vector register is viewed as being divided into VLEN/SEW elements. | norm:vtype_vsew_op |
| vtype_vsew_rsv | While it is anticipated the larger vsew[2:0] encodings (100-111) will be used to encode larger SEW, the encodings are formally reserved at this point. |
norm:vtype_vsew_rsv |
| vtype_lmul_val | Implementations must support LMUL integer values of 1, 2, 4, and 8. |
norm:vtype_lmul_val |
| vtype_lmul_fval | Implementations must provide fractional LMUL settings that allow the narrowest supported type to occupy a fraction of a vector register corresponding to the ratio of the narrowest supported type’s width to that of the largest supported type’s width. In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value. In the standard extensions, SEWMIN=8. For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported. | norm:vtype_lmul_fval |
| vtype_sew_val | For a given supported fractional LMUL setting, implementations must support SEW settings between SEWMIN and LMUL * ELEN, inclusive. | norm:vtype_sew_val |
| vtype_lmul_fval_rsv | The use of vtype encodings with LMUL < SEWMIN/ELEN is reserved, but implementations can set vill if they do not support these configurations. | norm:vtype_lmul_fval_rsv |
| LMUL | LMUL is set by the signed vlmul field in vtype (i.e., LMUL = 2vlmul[2:0]). | norm:lmul |
| VLMAX | The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number of elements that can be operated on with a single vector instruction given the current SEW and LMUL settings as shown in the table below. | norm:vlmax |
| vreg_offgroup_LMUL2_rsv | Instructions specifying an LMUL=2 vector register group with an odd-numbered vector register are reserved. |
norm:vreg_offgroup_lmul2_rsv |
| vreg_offgroup_LMUL4_rsv | instructions specifying an LMUL=4 vector register group using vector register numbers that are not multiples of four are reserved. |
norm:vreg_offgroup_lmul4_rsv |
| vreg_offgroup_LMUL8_rsv | instructions specifying an LMUL=8 vector register group using register numbers that are not multiples of eight are reserved. |
norm:vreg_offgroup_lmul8_rsv |
| vreg_mask_LMUL_indp | Mask registers are always contained in a single vector register, regardless of LMUL. | norm:vreg_mask_lmul_indp |
| vtype_vta_op | These two bits modify the behavior of destination tail elements and destination inactive masked-off elements respectively during the execution of vector instructions. The tail and inactive sets contain element positions that are not receiving new results during a vector operation, as defined in . | norm:vtype_vta-vma_op |
| vtype_vma_op | These two bits modify the behavior of destination tail elements and destination inactive masked-off elements respectively during the execution of vector instructions. The tail and inactive sets contain element positions that are not receiving new results during a vector operation, as defined in . | norm:vtype_vta-vma_op |
| vtype_vta_val | All systems must support all four options: | norm:vtype_vta-vma_val |
| vtype_vma_val | All systems must support all four options: | norm:vtype_vta-vma_val |
| vreg_mask_tail_agn | Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of vta. | norm:vreg_mask_tail_agn |
| vreg_mask_op | When a set is marked undisturbed, the corresponding set of destination elements in a vector register group retain the value they previously held. | norm:vreg_mask_op |
| vreg_agnostic_op | When a set is marked agnostic, the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s. Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs. | norm:vreg_agnostic_op |
| vreg_mask_tail_op | In addition, except for mask load instructions, any element in the tail of a mask result can also be written with the value the mask-producing operation would have calculated with vl=VLMAX. Furthermore, for mask-logical instructions and vmsbf.m, vmsif.m, vmsof.m mask-manipulation instructions, any element in the tail of the result can be written with the value the mask-producing operation would have calculated with vl=VLEN, SEW=8, and LMUL=8 (i.e., all bits of the mask register can be overwritten). | norm:vreg_mask_tail_op |
| vtype_vill_op | If the vill bit is set, then any attempt to execute a vector instruction that depends upon vtype will raise an illegal-instruction exception. | norm:vtype_vill_op |
| vl_acc | The XLEN-bit-wide read-only vl CSR can only be updated by the vset{i}vl{i} instructions, and the fault-only-first vector load instruction variants. | norm:vl_acc |
| vl_op | The vl register holds an unsigned integer specifying the number of elements to be updated with results from a vector instruction, as further detailed in . | norm:vl_op |
| vlenb_op | The XLEN-bit-wide read-only CSR vlenb holds the value VLEN/8, i.e., the vector register length in bytes. | norm:vlenb_acc_op |
| vlenb_acc | The XLEN-bit-wide read-only CSR vlenb holds the value VLEN/8, i.e., the vector register length in bytes. | norm:vlenb_acc_op |
| vstart_acc | The XLEN-bit-wide read-write vstart CSR specifies the index of the first element to be executed by a vector instruction, as described in . | norm:vstart_acc_sz |
| vstart_sz | The XLEN-bit-wide read-write vstart CSR specifies the index of the first element to be executed by a vector instruction, as described in . | norm:vstart_acc_sz |
| vstart_op | All vector instructions are defined to begin execution with the element number given in the vstart CSR, leaving earlier elements in the destination vector undisturbed |
norm:vstart_op |
| vstart_update | reset the vstart CSR to zero at the end of execution. |
norm:vstart_update |
| vstart_unmodified | vstart is not modified by vector instructions that raise illegal-instruction exceptions. | norm:vstart_unmodified |
| vstart_sz_writable | The vstart CSR is defined to have only enough writable bits to hold the largest element index (one less than the maximum VLMAX). | norm:vstart_sz_writable |
| vstart_val_rsv | The use of vstart values greater than the largest element index for the current vtype setting is reserved. | norm:vstart_val_rsv |
| vstart_vtype_dep | Implementations are permitted to raise illegal-instruction exceptions when attempting to execute a vector instruction with a value of vstart that the implementation can never produce when executing that same instruction with the same vtype setting. | norm:vstart_vtype_dep |
| vxrm_acc | The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the least-significant bits (vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as zeros. | norm:vxrm_val_sz_acc |
| vxrm_sz | The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the least-significant bits (vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as zeros. | norm:vxrm_val_sz_acc |
| vxrm_val | The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the least-significant bits (vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as zeros. | norm:vxrm_val_sz_acc |
| vcsr_vxrm_op | The vector fixed-point rounding-mode is given a separate CSR address to allow independent access, but is also reflected as a field in vcsr. | norm:vcsr_vxrm_op |
| vxrm_op | The fixed-point rounding algorithm is specified as follows. Suppose the pre-rounding result is v, and d bits of that result are to be rounded off. Then the rounded result is (v >> d) + r, where r depends on the rounding mode as specified in the following table. | norm:vxrm_op |
| vxsat_op | The vxsat CSR has a single read-write least-significant bit (vxsat[0]) that indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format. Bits vxsat[XLEN-1:1] should be written as zeros. | norm:vxsat_op_acc_sz |
| vxsat_acc | The vxsat CSR has a single read-write least-significant bit (vxsat[0]) that indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format. Bits vxsat[XLEN-1:1] should be written as zeros. | norm:vxsat_op_acc_sz |
| vxsat_sz | The vxsat CSR has a single read-write least-significant bit (vxsat[0]) that indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format. Bits vxsat[XLEN-1:1] should be written as zeros. | norm:vxsat_op_acc_sz |
| vcsr_vxsat_op | The vxsat bit is mirrored in vcsr. | norm:vcsr_vxsat_op |
| vcsr_vxsat_acc | The vxrm and vxsat separate CSRs can also be accessed via fields in the XLEN-bit-wide vector control and status CSR, vcsr. | norm:vcsr_vxrm-vxsat_acc |
| vcsr_vxrm_acc | The vxrm and vxsat separate CSRs can also be accessed via fields in the XLEN-bit-wide vector control and status CSR, vcsr. | norm:vcsr_vxrm-vxsat_acc |
| vreg_lmul1_op | When LMUL=1, elements are simply packed in order from the least-significant to most-significant bits of the vector register. | norm:vreg_lmul1_op |
| vreg_flmul_op | When LMUL < 1, only the first LMUL*VLEN/SEW elements in the vector register are used. The remaining space in the vector register is treated as part of the tail, and hence must obey the vta setting. | norm:vreg_flmul_op |
| vreg_lmulge2_op | When vector registers are grouped, the elements of the vector register group are packed contiguously in element order beginning with the lowest-numbered vector register and moving to the next-highest-numbered vector register in the group once each vector register is filled. | norm:vreg_lmulge2_op |
| vreg_mask_vtype_indp | A vector mask occupies only one vector register regardless of SEW and LMUL. | norm:vreg_mask_vtype_indp |
| vreg_mask_sz | Each element is allocated a single mask bit in a mask vector register. The mask bit for element i is located in bit i of the mask register, independent of SEW or LMUL. | norm:vreg_mask_sz |
| vreg_scalar_lmul_indp | Any vector register can be used to hold a scalar regardless of the current LMUL setting. |
norm:vreg_scalar_lmul_indp |
| EEW | Each vector operand has an effective element width (EEW) and an effective LMUL (EMUL) that is used to determine the size and location of all the elements within a vector register group. By default, for most operands of most instructions, EEW=SEW and EMUL=LMUL. | norm:eew_emul |
| EMUL | Each vector operand has an effective element width (EEW) and an effective LMUL (EMUL) that is used to determine the size and location of all the elements within a vector register group. By default, for most operands of most instructions, EEW=SEW and EMUL=LMUL. | norm:eew_emul |
| EMUL_SEW_LMUL_dep | EEW/EMUL = SEW/LMUL. | norm:eew_emul_sew_lmul_dep |
| EEW_SEW_LMUL_dep | EEW/EMUL = SEW/LMUL. | norm:eew_emul_sew_lmul_dep |
| vnarrowing_EEW | Narrowing instructions have a source operand that has EEW=2*SEW and EMUL=2*LMUL but with a destination where EEW=SEW and EMUL=LMUL. |
norm:vnarrowing_eew_emul |
| vnarrowing_EMUL | Narrowing instructions have a source operand that has EEW=2*SEW and EMUL=2*LMUL but with a destination where EEW=SEW and EMUL=LMUL. |
norm:vnarrowing_eew_emul |
| EMUL_offgroup_rsv | Using other than the lowest-numbered vector register to specify a vector register group is a reserved encoding. |
norm:emul_offgroup_rsv |
| vreg_source_EEW_rsv | A vector register cannot be used to provide source operands with more than one EEW for a single instruction. A mask register source is considered to have EEW=1 for this constraint. An encoding that would result in the same vector register being read with two or more different EEWs, including when the vector register appears at different positions within two or more vector register groups, is reserved. | norm:vreg_source_eew_rsv |
| vreg_overlap_legal | A destination vector register group can overlap a source vector register group only if one of the following holds: | norm:vreg_overlap_legal |
| vreg_mask_overlap | For the purpose of determining register group overlap constraints, mask elements have EEW=1. | norm:vreg_mask_overlap |
| vreg_overlap_rsv | Any instruction encoding that violates the overlap constraints is reserved. | norm:vreg_overlap_rsv |
| vreg_overlap_agn | When source and destination registers overlap and have different EEW, the instruction is mask- and tail-agnostic, regardless of the setting of the vta and vma bits in vtype. | norm:vreg_overlap_agn |
| EMUL_rsv | The largest vector register group used by an instruction can not be greater than 8 vector registers (i.e., EMUL≤8), and if a vector instruction would require greater than 8 vector registers in a group, the instruction encoding is reserved. For example, a widening operation that produces a widened vector register group result when LMUL=8 is reserved as this would imply a result EMUL=16. | norm:emul_rsv |
| vreg_scalar_EMUL | Widened scalar values, e.g., input and output to a widening reduction operation, are held in the first element of a vector register and have EMUL=1. | norm:vreg_scalar_emul |
| vmask_op | Element operations that are masked off (inactive) never generate exceptions. |
norm:vmask_inactive_op |
| The destination vector register elements corresponding to masked-off elements are handled with either a mask-undisturbed or mask-agnostic policy depending on the setting of the vma bit in vtype |
norm:vmask_agn_op | |
| Where available, masking is encoded in a single-bit vm field in the instruction (inst[25]). | norm:vmask_vm_enc | |
| vreg_vmask | The mask value used to control execution of a masked vector instruction is always supplied by vector register v0. | norm:vreg_vmask |
| vreg_vmask_rsv | The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction. These instruction encodings are reserved. | norm:vreg_vmask_rsv |
| vstart_vl_dep | When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. | norm:vstart_vl_dep |
| vstart_vl_scalar_indp | Instructions that write an x register or f register do so even when vstart ≥ vl, including when vl=0. | norm:vstart_vl_scalar_indp |
| vector_prestart_element | The prestart elements do not raise exceptions and do not update the destination vector register. | norm:vector_prestart_element |
| vector_inactive_element | The inactive elements do not raise exceptions and do not update any destination vector register group unless masked agnostic is specified (vtype.vma=1), in which case inactive elements may be overwritten with 1s. | norm:vector_inactive_element |
| vector_tail_element | The tail elements do not raise exceptions, and do not update any destination vector register group unless tail agnostic is specified (vtype.vta=1), in which case tail elements may be overwritten with 1s, or with the result of the instruction in the case of mask-producing instructions except for mask loads. When LMUL < 1, the tail includes the elements past VLMAX that are held in the same vector register. | norm:vector_tail_element |
| vset_op | The vset{i}vl{i} instructions set the vtype and vl CSRs based on their arguments, and write the new value of vl into rd. |
norm:vset_op |
| vtype_vstart_op | the vl register is also set to zero. | norm:vtype_vstart_op |
| vtype_acc | The new vtype value is encoded in the immediate fields of vsetvli and vsetivli, and in the rs2 register for vsetvl. | norm:vtype_acc |
| The read-only XLEN-wide vector type CSR, vtype provides the default type used to interpret the contents of the vector register file, and can only be updated by vset{i}vl{i} instructions. |
norm:vtype_sz_acc_op | |
| vtype_vill_set | If the vtype value is not supported by the implementation, then the vill bit is set in vtype, the remaining bits in vtype are set to zero |
norm:vtype_vill_val |
| A vtype value with vill set is treated as an unsupported configuration. | norm:vtype_vill_val_vill | |
| Implementations must consider all bits of the vtype value to determine if the configuration is supported. An unsupported value in any location within the vtype value must result in vill being set. | norm:vtype_vill_all_bits | |
| vsetvl_op | When rs1 is not x0, the AVL is an unsigned integer held in the x register specified by rs1, and the new vl value is also written to the x register specified by rd. | norm:vsetvl_op |
| When rs1=x0 but rd≠x0, the maximum unsigned integer value (~0) is used as the AVL, and the resulting VLMAX is written to vl and also to the x register specified by rd. | norm:vsetvl_op_rs1_x0_rd_nx0 | |
| When rs1=x0 and rd=x0, the instructions operate as if the current vector length in vl is used as the AVL, and the resulting value is written to vl, but not to a destination register. This form can only be used when VLMAX and hence vl is not actually changed by the new SEW/LMUL ratio. | norm:vsetvl_op_rs1_x0_rd_x0 | |
| vtype_vset_rsv | Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if vill was 1 beforehand. | norm:vtype_vset_rsv |
| vsetivli_op | For the vsetivli instruction, the AVL is encoded as a 5-bit zero-extended immediate (0—31) in the rs1 field. | norm:vsetivli_op |
| vl_val | The vset{i}vl{i} instructions first set VLMAX according to their vtype argument, then set vl obeying the following constraints: | norm:vl_val_lead-in |
| vl = AVL if AVL ≤ VLMAX ceil(AVL / 2) ≤ vl ≤ VLMAX if AVL < (2 * VLMAX) vl = VLMAX if AVL ≥ (2 * VLMAX) Deterministic on any given implementation for same input AVL and VLMAX values These specific properties follow from the prior rules: vl = 0 if AVL = 0 vl > 0 if AVL > 0 vl ≤ VLMAX vl ≤ AVL a value read from vl when used as the AVL argument to vset{i}vl{i} results in the same value in vl, provided the resultant VLMAX equals the value of VLMAX at the time that vl was read |
norm:vl_val_list | |
| VECTOR_LS_VSTART | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| All vector loads and stores may generate and accept a non-zero vstart value. | norm:vector_ls_vstart | |
| vector_ls_base_stride_regtype | Vector load/store base registers and strides are taken from the GPR x registers. |
norm:vector_ls_base_stride_regtype |
| vector_ls_base | The base effective address for all vector accesses is given by the contents of the x register named in rs1. | norm:vector_ls_base |
| vector_ls_unit_stride_op | Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. | norm:vector_ls_unit_stride_op |
| vector_ls_constant_stride_op | Vector constant-stride operations access the first memory element at the base effective address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. | norm:vector_ls_constant_stride_op |
| vector_ls_strided_EEW | Vector memory unit-stride and constant-stride operations directly encode EEW of the data to be transferred statically in the instruction to reduce the number of vtype changes when accessing memory in a mixed-width routine. | norm:vector_ls_strided_eew |
| vector_ls_seg_unit_stride_vd_vs3 | For loads, the vd register will hold the first field loaded from the segment. For stores, the vs3 register is read to provide the first field to be stored to each segment. | norm:vector_ls_seg_unit_stride_vd_vs3 |
| vector_ls_scalar_missaligned_independence | Support for misaligned vector memory accesses is independent of an implementation’s support for misaligned scalar memory accesses. | norm:vector_ls_scalar_missaligned_independence |
| vector_ls_scalar_missaligned_dependence | Vector misaligned memory accesses follow the same rules for atomicity as scalar misaligned memory accesses. | norm:vector_ls_scalar_missaligned_dependence |
| vector_ls_seg_indexed_unordered | However, even for the ordered form, accesses to the fields within an individual segment are not ordered with respect to each other. | norm:vector_ls_seg_indexed_unordered |
| vector_ff_op | If element 0 raises an exception, vl is not modified, and the trap is taken. If an element > 0 raises an exception, the corresponding trap is not taken, and the vector length vl is reduced to the index of the element that would have raised an exception. | norm:vector_ff_op |
| vector_ls_indexed_op | Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. The data vector register group has EEW=SEW, EMUL=LMUL, while the offset vector register group has EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL. | norm:vector_ls_indexed_op |
| vector_ls_indexed_EEW | Indexed operations use the explicit EEW encoding in the instruction to set the size of the indices used, and use SEW/LMUL to specify the data width. | norm:vector_ls_indexed_eew |
| vector_ls_ins_req | Implementations must provide vector loads and stores with EEWs corresponding to all supported SEW settings. | norm:vector_ls_ins_req |
| vector_ls_ins_rsv | Vector load/store encodings for unsupported EEW widths are reserved. | norm:vector_ls_ins_rsv |
| vector_ls_bytewise | The vector offset operand is treated as a vector of byte-address offsets. | norm:vector_ls_bytewise |
| vector_ls_XLEN_dep | If the vector offset elements are narrower than XLEN, they are zero-extended to XLEN before adding to the base effective address. If the vector offset elements are wider than XLEN, the least-significant XLEN bits are used in the address calculation. | norm:vector_ls_xlen_dep |
| vector_ls_EEW_rsv | If the implementation does not support the EEW of the offset elements, the instruction is reserved. | norm:vector_ls_eew_rsv |
| vector_ls_stride_ordered_op | Vector unit-stride and constant-stride memory accesses do not guarantee ordering between individual element accesses. The vector indexed load and store memory operations have two forms, ordered and unordered. The indexed-ordered variants preserve element ordering on memory accesses. | norm:vector_ls_stride_ordered_op |
| vector_ls_stride_unordered_op | For unordered instructions (mop[1:0]!=11) there is no guarantee on element access order. If the accesses are to a strongly ordered IO region, the element accesses can be initiated in any order. | norm:vector_ls_stride_unordered_op |
| vector_ls_stride_unordered_precise | For implementations with precise vector traps, exceptions on indexed-unordered stores must also be precise. | norm:vector_ls_stride_unordered_precise |
| vector_ls_nf_op | The nf[2:0] field encodes the number of fields in each segment. For regular vector loads and stores, nf=0, indicating that a single value is moved between a vector register group and memory at each element position. Larger values in the nf field are used to access multiple contiguous fields within a segment as described below in . | norm:vector_ls_nf_op |
| vector_wholels_nf_op | The nf[2:0] field also encodes the number of whole vector registers to transfer for the whole vector register load/store instructions. | norm:vector_wholels_nf_op |
| vector_ls_EEW | Vector loads and stores have an EEW encoded directly in the instruction. The corresponding EMUL is calculated as EMUL = (EEW/SEW)*LMUL. |
norm:vector_ls_eew_emul |
| vector_ls_EMUL | Vector loads and stores have an EEW encoded directly in the instruction. The corresponding EMUL is calculated as EMUL = (EEW/SEW)*LMUL. |
norm:vector_ls_eew_emul |
| vector_ls_EMUL_rsv | If the EMUL would be out of range (EMUL>8 or EMUL<1/8), the instruction encoding is reserved. |
norm:vector_ls_emul_rsv |
| vector_ls_EMUL_offgroup_rsv | The vector register groups must have legal register specifiers for the selected EMUL, otherwise the instruction encoding is reserved. |
norm:vector_ls_emul_offgroup_rsv |
| vector_ls_indexed_EMUL | Vector unit-stride and constant-stride use the EEW/EMUL encoded in the instruction for the data values, while vector indexed loads and stores use the EEW/EMUL encoded in the instruction for the index values and the SEW/LMUL encoded in vtype for the data values. | norm:vector_ls_indexed_eew_emul |
| vector_ls_mew_rsv | The mew bit (inst[28]) when set is expected to be used to encode expanded memory sizes of 128 bits and above, but these encodings are currently reserved. | norm:vector_ls_mew_rsv |
| vector_ls_unit_stride_mask | Additional unit-stride mask load and store instructions are provided to transfer mask values to/from memory. These operate similarly to unmasked byte loads or stores (EEW=8), except that the effective vector length is evl=ceil(vl/8) (i.e. EMUL=1), and the destination register is always written with a tail-agnostic policy. | norm:vector_ls_unit_stride_mask |
| vector_ls_neg_stride | Negative and zero strides are supported. | norm:vector_ls_neg_zero_stride |
| vector_ls_zero_stride | Negative and zero strides are supported. | norm:vector_ls_neg_zero_stride |
| vector_ls_constant_stride_unordered | Element accesses within a constant-stride instruction are unordered with respect to each other. | norm:vector_ls_constant_stride_unordered |
| VECTOR_LS_CONSTANT_STRIDE_X0 | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| When rs2=x0, then an implementation is allowed, but not required, to perform fewer memory operations than the number of active elements, and may perform different numbers of memory operations across different dynamic executions of the same static instruction. | norm:vector_ls_constant_stride_x0 | |
| vector_ff_trigger | The unit-stride fault-only-first load instructions are used to vectorize loops with data-dependent exit conditions ("while" loops). These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception on element 0. |
norm:vector_ff_trigger |
| VECTOR_LS_OVERWRITE_PAST_TRAP | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported. |
norm:vector_ls_overwrite_past_trap | |
| VECTOR_FF_PAST_TRAP | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming of the vector length (but not past the original vector length). The values of these spurious updates do not have to correspond to the values in memory at the addressed memory locations. Non-idempotent memory locations can only be accessed when it is known the corresponding element load operation will not be restarted due to a trap or vector-length trimming. | norm:vector_ff_past_trap | |
| vector_ff_no_exception | Even when an exception is not raised, implementations are permitted to process fewer than vl elements and reduce vl accordingly, but if vstart=0 and vl>0, then at least one element must be processed. | norm:vector_ff_no_exception |
| vector_ff_interrupt_behavior | When the fault-only-first instruction takes a trap due to an interrupt, implementations should not reduce vl and should instead set a vstart value. | norm:vector_ff_interrupt_behavior |
| NFIELDS | The three-bit nf field in the vector instruction encoding is an unsigned integer that contains one less than the number of fields per segment, NFIELDS. | norm:nfields |
| Each field will be held in successively numbered vector register groups. When EMUL>1, each field will occupy a vector register group held in multiple successively numbered vector registers, and the vector register group for each field must follow the usual vector register alignment constraints (e.g., when EMUL=2 and NFIELDS=4, each field’s vector register group must start at an even vector register, but does not have to start at a multiple of 8 vector register number). | norm:nfields_op | |
| EMUL_NFIELDS_rsv | The EMUL setting must be such that EMUL * NFIELDS ≤ 8, otherwise the instruction encoding is reserved. | norm:emul_nfields_rsv |
| vector_ls_seg_rsv | If the vector register numbers accessed by the segment load or store would increment past 31, then the instruction encoding is reserved. | norm:vector_ls_seg_rsv |
| vector_ls_seg_op | The vl register gives the number of segments to move, which is equal to the number of elements transferred to each vector register group. Masking is also applied at the level of whole segments. | norm:vector_ls_seg_op |
| vector_ls_seg_unordered | For segment loads and stores, the individual memory accesses used to access fields within each segment are unordered with respect to each other even for ordered indexed segment loads and stores. | norm:vector_ls_seg_unordered |
| vector_ls_seg_vstart_dep | The vstart value is in units of whole segments. | norm:vector_ls_seg_vstart_dep |
| VECTOR_LS_SEG_PARTIAL_ACCESS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| If a trap occurs during access to a segment, it is implementation-defined whether a subset of the faulting segment's accesses are performed before the trap is taken. |
norm:vector_ls_seg_partial_access | |
| vector_ls_seg_unit_stride_op | The vector unit-stride load and store segment instructions move packed contiguous segments into multiple destination vector register groups. | norm:vector_ls_seg_unit_stride_op |
| vector_ls_seg_ff_unit_stride_op | For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken. If an exception is detected partway through accessing a subsequent segment, vl is reduced to the index of that segment. | norm:vector_ls__seg_ff_unit-stride_op |
| VECTOR_FF_SEG_PARTIAL_ACCESS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| [CONTEXT] For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken. If an exception is detected partway through accessing a subsequent segment, vl is reduced to the index of that segment. | norm:vector_ls__seg_ff_unit-stride_op | |
| In both cases, it is implementation-defined whether a subset of the segment is loaded. | norm:vector_ff_seg_partial_access | |
| VECTOR_LS_SEG_FF_OVERLOAD | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| These instructions may overwrite destination vector register group elements past the point at which a trap is reported or past the point at which vector length is trimmed. | norm:vector_ls_seg_ff_overload | |
| vector_ls_seg_constant_stride_op | Vector constant-stride segment loads and stores move contiguous segments where each segment is separated by the byte-stride offset given in the rs2 GPR argument. | norm:vector_ls_seg_constant_stride_op |
| vector_ls_seg_constant_stride_unordered | Accesses to the fields within each segment can occur in any order, including the case where the byte stride is such that segments overlap in memory. | norm:vector_ls_seg_constant_stride_unordered |
| vector_ls_seg_indexed_op | Vector indexed segment loads and stores move contiguous segments where each segment is located at an address given by adding the scalar base address in the rs1 field to byte offsets in vector register vs2. | norm:vector_ls_seg_indexed_op |
| vector_ls_seg_indexed_EMUL_op | The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL. | norm:vector_ls_seg_indexed_eew_emul_op |
| vector_ls_seg_indexed_EEW_op | The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL. | norm:vector_ls_seg_indexed_eew_emul_op |
| vector_ls_seg_indexed_EMUL_NFIELDS_val | The EMUL * NFIELDS ≤ 8 constraint applies to the data vector register group. | norm:vector_ls_seg_indexed_emul_nfields_val |
| vector_ls_seg_indexed_vreg_rsv | For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by vs2), else the instruction encoding is reserved. | norm:vector_ls_seg_indexed_vreg_rsv |
| vector_ls_seg_wholereg_EEW | The load instructions have an EEW encoded in the mew and width fields following the pattern of regular unit-stride loads. | norm:vector_ls_seg_wholereg_eew |
| vector_ls_seg_wholereg_op | NFIELDS indicates the number of vector registers to transfer, numbered successively after the base. |
norm:vector_ls_seg_wholereg_op |
| vector_ls_seg_wholereg_nf_rsv | Only NFIELDS values of 1, 2, 4, 8 are supported, with other values reserved. |
norm:vector_ls_seg_wholereg_nf_rsv |
| vector_ls_seg_wholereg_op_cont | When multiple registers are transferred, the lowest-numbered vector register is held in the lowest-numbered memory addresses and successive vector register numbers are placed contiguously in memory. |
norm:vector_ls_seg_wholereg_op_cont |
| vector_ls_seg_wholereg_evl | The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW, regardless of current settings in vtype and vl. The usual property that no elements are written if vstart ≥ vl does not apply to these instructions. Similarly, the property that the instructions are reserved if vstart exceeds the largest element index for the current vtype setting does not apply. Instead, the instructions are reserved if vstart ≥ evl. | norm:vector_ls_seg_wholereg_evl |
| VECTOR_LS_WHOLEREG_MISSALIGNED_EXCEPTION | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation’s smallest supported SEW size in bytes (SEWMIN/8). | norm:vector_ls_wholereg_missaligned_exception | |
| VECTOR_LS_MISSALIGNED_EXCEPTION | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address-misaligned exception is raised on that element. | norm:vector_ls_missaligned_exception | |
| vector_ls_program_order | Vector memory instructions appear to execute in program order on the local hart. | norm:vector_ls_program_order |
| vector_ls_RVWMO | Vector memory instructions follow RVWMO at the instruction level. | norm:vector_ls_rvwmo |
| vector_ls_indexed_ordered_ordered | Except for vector indexed-ordered loads and stores, element operations are unordered within the instruction. | norm:vector_ls_indexed_ordered_ordered |
| vector_ls_indexed_ordered_RVWMO | Vector indexed-ordered loads and stores read and write elements from/to memory in element order respectively, obeying RVWMO at the element level. | norm:vector_ls_indexed_ordered_rvwmo |
| vector_load_store_semantics | Vector loads and stores move values between vector registers and memory. |
norm:vector_load_store_semantics |
| vector_masked_memory_access | Vector loads and stores can be masked, and they only access memory or raise exceptions for active elements. |
norm:vector_masked_memory_access |
| vector_masked_inactive_behavior | Masked vector loads do not update inactive elements in the destination vector register group, unless masked agnostic is specified (vtype.vma=1). |
norm:vector_masked_inactive_behavior |
| vl_control_dependency | Instructions affected by the vector length register vl have a control dependency on vl, rather than a data dependency. | norm:vl_control_dependency |
| vmask_control_dependency | Similarly, masked vector instructions have a control dependency on the source mask register, rather than a data dependency. | norm:vmask_control_dependency |
| V_fp_frm | All vector floating-point operations use the dynamic rounding mode in the frm register. | norm:V_fp_frm |
| V_inv_frm_rsv | Use of the frm field when it contains an invalid rounding mode by any vector floating-point instruction--even those that do not depend on the rounding mode, or when vl=0, or when vstart {ge} vl--is reserved. |
norm:V_inv_frm_rsv |
| vop-vv_vreg_vs2_vs1 | Vector-vector operations take two vectors of operands from vector register groups specified by vs2 and vs1 respectively. | norm:vop-vv_vreg_vs2_vs1 |
| vop-vx_vreg_vs2 | the vector register group operand is specified by vs2. | norm:vop-vx_vop-vi_vreg_vs2 |
| vop-vi_vreg_vs2 | the vector register group operand is specified by vs2. | norm:vop-vx_vop-vi_vreg_vs2 |
| vop-vi_imm_5bit | For integer operations, the scalar can be a 5-bit immediate, imm[4:0], encoded in the rs1 field. The value is sign-extended to SEW bits, unless otherwise specified. |
norm:vop-vi_imm_5bit |
| vop-vx_xreg_rs1 | For integer operations, the scalar can be taken from the scalar x register specified by rs1. |
norm:vop-vx_xreg_rs1 |
| vop-vx_rs1_trunc_lsb_sewbits | If XLEN>SEW, the least-significant SEW bits of the x register are used, unless otherwise specified. | norm:vop-vx_rs1_trunc_lsb_sewbits |
| vop-vx_rs1_sext_sewbits | If XLEN<SEW, the value from the x register is sign-extended to SEW bits. |
norm:vop-vx_rs1_sext_sewbits |
| vfop_freg | For floating-point operations, the scalar can be taken from a scalar f register. |
norm:vfop_freg |
| vfop_freg_NaNbox_lsb_sewbits | If FLEN > SEW, the value in the f registers is checked for a valid NaN-boxed value, in which case the least-significant SEW bits of the f register are used, else the canonical NaN value is used. |
norm:vfop_freg_NaNbox_lsb_sewbits |
| V_fp_eew_rsv | Vector instructions where any floating-point vector operand's EEW is not a supported floating-point type width (which includes when FLEN < SEW) are reserved. |
norm:V_fp_eew_rsv |
| V_Zfinx_fp_scalar | When adding a vector extension to the Zfinx/Zdinx/Zhinx extensions, floating-point scalar arguments are taken from the x registers. NaN-boxing is not supported in these extensions, and so operands narrower than XLEN bits are not checked for a NaN box; bits XLEN-1:EEW are ignored. For RV32_Zdinx, EEW=64 scalar arguments are supplied by an x-register pair. |
norm:V_Zinx_fp_scalar |
| V_masked | Vector arithmetic instructions are masked under control of the vm field. |
norm:V_masked |
| vwop_vd_eew_emul | A few vector arithmetic instructions are defined to be widening operations where the destination vector register group has EEW=2*SEW and EMUL=2*LMUL. |
norm:vwop_vd_eew_emul |
| vnop_vd_eew_emul | A few instructions are provided to convert double-width source vectors into single-width destination vectors. These instructions convert a vector register group specified by vs2 with EEW/EMUL=2*SEW/2*LMUL to a vector register group with the current SEW/LMUL setting. |
norm:vnop_vd_vs2_eew_emul |
| vnop_vs2_eew_emul | A few instructions are provided to convert double-width source vectors into single-width destination vectors. These instructions convert a vector register group specified by vs2 with EEW/EMUL=2*SEW/2*LMUL to a vector register group with the current SEW/LMUL setting. |
norm:vnop_vd_vs2_eew_emul |
| vnop_vs1_eew_emul | Where there is a second source vector register group (specified by vs1), this has the same (narrower) width as the result (i.e., EEW=SEW). |
norm:vnop_vs1_eew_emul |
| vadd_op | Vector integer add and subtract are provided. | norm:vadd_vsub_op |
| vsub_op | Vector integer add and subtract are provided. | norm:vadd_vsub_op |
| vrsub_op | Reverse-subtract instructions are also provided for the vector-scalar forms. |
norm:vrsub_op |
| vwaddu_op | The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign- or zero-extended before forming the double-width sum. |
norm:vwaddu_vwadd_vwsubu_vwsub_op |
| vwadd_op | The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign- or zero-extended before forming the double-width sum. |
norm:vwaddu_vwadd_vwsubu_vwsub_op |
| vwsubu_op | The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign- or zero-extended before forming the double-width sum. |
norm:vwaddu_vwadd_vwsubu_vwsub_op |
| vwsub_op | The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign- or zero-extended before forming the double-width sum. |
norm:vwaddu_vwadd_vwsubu_vwsub_op |
| vsext_op | The vector integer extension instructions zero- or sign-extend a source vector integer operand with EEW less than SEW to fill SEW-sized elements in the destination. |
norm:vsext_vzext_op |
| vzext_op | The vector integer extension instructions zero- or sign-extend a source vector integer operand with EEW less than SEW to fill SEW-sized elements in the destination. |
norm:vsext_vzext_op |
| vsext_vs_eew_emul | The EEW of the source is 1/2, 1/4, or 1/8 of SEW, while EMUL of the source is (EEW/SEW)*LMUL. |
norm:vsext_vzext_vs_eew_emul |
| vzext_vs_eew_emul | The EEW of the source is 1/2, 1/4, or 1/8 of SEW, while EMUL of the source is (EEW/SEW)*LMUL. |
norm:vsext_vzext_vs_eew_emul |
| vsext_vd_eew_emul | The destination has EEW equal to SEW and EMUL equal to LMUL. |
norm:vsext_vzext_vd_eew_emul |
| vzext_vd_eew_emul | The destination has EEW equal to SEW and EMUL equal to LMUL. |
norm:vsext_vzext_vd_eew_emul |
| vsext_ill_eew_emul_rsv | If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, the instruction encoding is reserved. |
norm:vsext_vzext_ill_eew_emul_rsv |
| vzext_ill_eew_emul_rsv | If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, the instruction encoding is reserved. |
norm:vsext_vzext_ill_eew_emul_rsv |
| vmadc_carry_v0 | The carry inputs and outputs are represented using the mask register layout as described in sec-mask-register-layout. Due to encoding constraints, the carry input must come from the implicit v0 register, |
norm:vmadc_vmsbc_vadc_vsbc_carry_v0 |
| vmsbc_carry_v0 | The carry inputs and outputs are represented using the mask register layout as described in sec-mask-register-layout. Due to encoding constraints, the carry input must come from the implicit v0 register, |
norm:vmadc_vmsbc_vadc_vsbc_carry_v0 |
| vadc_carry_v0 | The carry inputs and outputs are represented using the mask register layout as described in sec-mask-register-layout. Due to encoding constraints, the carry input must come from the implicit v0 register, |
norm:vmadc_vmsbc_vadc_vsbc_carry_v0 |
| vsbc_carry_v0 | The carry inputs and outputs are represented using the mask register layout as described in sec-mask-register-layout. Due to encoding constraints, the carry input must come from the implicit v0 register, |
norm:vmadc_vmsbc_vadc_vsbc_carry_v0 |
| vadc_op | vadc and vsbc add or subtract the source operands and the carry-in or borrow-in, and write the result to vector register vd. |
norm:vadc_vsbc_op |
| vsbc_op | vadc and vsbc add or subtract the source operands and the carry-in or borrow-in, and write the result to vector register vd. |
norm:vadc_vsbc_op |
| vadc_masked_write_all_elem | These instructions are encoded as masked instructions (vm=0), but they operate on and write back all body elements. |
norm:vadc_vsbc_masked_write_all_elem |
| vsbc_masked_write_all_elem | These instructions are encoded as masked instructions (vm=0), but they operate on and write back all body elements. |
norm:vadc_vsbc_masked_write_all_elem |
| vadc_unmasked_rsv | Encodings corresponding to the unmasked versions (vm=1) are reserved. | norm:vadc_vsbc_unmasked_rsv |
| vsbc_unmasked_rsv | Encodings corresponding to the unmasked versions (vm=1) are reserved. | norm:vadc_vsbc_unmasked_rsv |
| vmadc_op | vmadc and vmsbc add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (vm=0), and write the resulting carry-out or borrow-out back to mask register vd. |
norm:vmadc_vmsbc_op_masked |
| If unmasked (vm=1), there is no carry-in or borrow-in. | norm:vmadc_vmsbc_op_unmasked | |
| vmsbc_op | vmadc and vmsbc add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (vm=0), and write the resulting carry-out or borrow-out back to mask register vd. |
norm:vmadc_vmsbc_op_masked |
| If unmasked (vm=1), there is no carry-in or borrow-in. | norm:vmadc_vmsbc_op_unmasked | |
| vmadc_masked_write_all_elem | These instructions operate on and write back all body elements, even if masked. |
norm:vmadc_vmsbc_masked_write_all_elem |
| vmsbc_masked_write_all_elem | These instructions operate on and write back all body elements, even if masked. |
norm:vmadc_vmsbc_masked_write_all_elem |
| vmadc_tail_agnostic | Because these instructions produce a mask value, they always operate with a tail-agnostic policy. |
norm:vmadc_vmsbc_tail_agnostic |
| vmsbc_tail_agnostic | Because these instructions produce a mask value, they always operate with a tail-agnostic policy. |
norm:vmadc_vmsbc_tail_agnostic |
| vmsbc_borrow_neg | For vmsbc, the borrow is defined to be 1 iff the difference, prior to truncation, is negative. |
norm:vmsbc_borrow_neg |
| vadc_vd_v0_rsv | For vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0. |
norm:vadc_vsbc_vd_v0_rsv |
| vsbc_vd_v0_rsv | For vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0. |
norm:vadc_vsbc_vd_v0_rsv |
| vand_op | # Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate vor.vv vd, vs2, vs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # vector-scalar vor.vi vd, vs2, imm, vm # vector-immediate vxor.vv vd, vs2, vs1, vm # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # vector-immediate |
norm:vand_vor_vxor_op |
| vor_op | # Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate vor.vv vd, vs2, vs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # vector-scalar vor.vi vd, vs2, imm, vm # vector-immediate vxor.vv vd, vs2, vs1, vm # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # vector-immediate |
norm:vand_vor_vxor_op |
| vxor_op | # Bitwise logical operations. vand.vv vd, vs2, vs1, vm # Vector-vector vand.vx vd, vs2, rs1, vm # vector-scalar vand.vi vd, vs2, imm, vm # vector-immediate vor.vv vd, vs2, vs1, vm # Vector-vector vor.vx vd, vs2, rs1, vm # vector-scalar vor.vi vd, vs2, imm, vm # vector-immediate vxor.vv vd, vs2, vs1, vm # Vector-vector vxor.vx vd, vs2, rs1, vm # vector-scalar vxor.vi vd, vs2, imm, vm # vector-immediate |
norm:vand_vor_vxor_op |
| vsll_op | A full set of vector shift instructions are provided, including logical shift left (sll), and logical (zero-extending srl) and arithmetic (sign-extending sra) shift right. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. |
norm:vsll_vsrl_vsra_op |
| vsrl_op | A full set of vector shift instructions are provided, including logical shift left (sll), and logical (zero-extending srl) and arithmetic (sign-extending sra) shift right. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. |
norm:vsll_vsrl_vsra_op |
| vsra_op | A full set of vector shift instructions are provided, including logical shift left (sll), and logical (zero-extending srl) and arithmetic (sign-extending sra) shift right. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. |
norm:vsll_vsrl_vsra_op |
| vsll_shamt | Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount. |
norm:vsll_vsrl_vsra_shamt |
| vsrl_shamt | Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount. |
norm:vsll_vsrl_vsra_shamt |
| vsra_shamt | Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount. |
norm:vsll_vsrl_vsra_shamt |
| vnsrl_op | The narrowing right shifts extract a smaller field from a wider operand and have both zero-extending (srl) and sign-extending (sra) forms. The shift amount can come from a vector register group, or a scalar x register, or a zero-extended 5-bit immediate. |
norm:vnsrl_vnsra_op |
| vnsra_op | The narrowing right shifts extract a smaller field from a wider operand and have both zero-extending (srl) and sign-extending (sra) forms. The shift amount can come from a vector register group, or a scalar x register, or a zero-extended 5-bit immediate. |
norm:vnsrl_vnsra_op |
| vnsrl_shamt | The low lg2(2*SEW) bits of the shift-amount value are used (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation). |
norm:vnsrl_vnsra_shamt |
| vnsra_shamt | The low lg2(2*SEW) bits of the shift-amount value are used (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation). |
norm:vnsrl_vnsra_shamt |
| vmseq_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmsne_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmsltu_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmslt_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmsleu_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmsle_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmsgtu_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmsgt_op | The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise. The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_op |
| vmseq_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmsne_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmsltu_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmslt_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmsleu_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmsle_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmsgtu_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmsgt_vd_v0_legal | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_vd_v0_legal |
| vmseq_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmsne_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmsltu_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmslt_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmsleu_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmsle_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmsgtu_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmsgt_maskundisturbed | Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is v0, | norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_maskundisturbed |
| vmseq_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vmsne_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vmsltu_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vmslt_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vmsleu_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vmsle_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vmsgtu_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vmsgt_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmseq_vmsne_vmsltu_vmslt_vmsleu_vmsle_vmsgtu_vmsgt_tail_agnostic |
| vminu_op | Signed and unsigned integer minimum and maximum instructions are supported. |
norm:vminu_vmin_vmaxu_vmax_op |
| vmin_op | Signed and unsigned integer minimum and maximum instructions are supported. |
norm:vminu_vmin_vmaxu_vmax_op |
| vmaxu_op | Signed and unsigned integer minimum and maximum instructions are supported. |
norm:vminu_vmin_vmaxu_vmax_op |
| vmax_op | Signed and unsigned integer minimum and maximum instructions are supported. |
norm:vminu_vmin_vmaxu_vmax_op |
| vmul_op | The single-width multiply instructions perform a SEW-bit*SEW-bit multiply to generate a 2*SEW-bit product, then return one half of the product in the SEW-bit-wide destination. The mul versions write the low half of the product to the destination register, while the mulh versions write the high half of the product to the destination register. |
norm:vmul_vmulh_vmulhu_vmulhsu_op |
| vmulh_op | The single-width multiply instructions perform a SEW-bit*SEW-bit multiply to generate a 2*SEW-bit product, then return one half of the product in the SEW-bit-wide destination. The mul versions write the low half of the product to the destination register, while the mulh versions write the high half of the product to the destination register. |
norm:vmul_vmulh_vmulhu_vmulhsu_op |
| vmulhu_op | The single-width multiply instructions perform a SEW-bit*SEW-bit multiply to generate a 2*SEW-bit product, then return one half of the product in the SEW-bit-wide destination. The mul versions write the low half of the product to the destination register, while the mulh versions write the high half of the product to the destination register. |
norm:vmul_vmulh_vmulhu_vmulhsu_op |
| vmulhsu_op | The single-width multiply instructions perform a SEW-bit*SEW-bit multiply to generate a 2*SEW-bit product, then return one half of the product in the SEW-bit-wide destination. The mul versions write the low half of the product to the destination register, while the mulh versions write the high half of the product to the destination register. |
norm:vmul_vmulh_vmulhu_vmulhsu_op |
| vdivu_op | The divide and remainder instructions are equivalent to the RISC-V standard scalar integer multiply/divides, with the same results for extreme inputs. |
norm:vdivu_vdiv_vremu_vrem_op |
| vdiv_op | The divide and remainder instructions are equivalent to the RISC-V standard scalar integer multiply/divides, with the same results for extreme inputs. |
norm:vdivu_vdiv_vremu_vrem_op |
| vremu_op | The divide and remainder instructions are equivalent to the RISC-V standard scalar integer multiply/divides, with the same results for extreme inputs. |
norm:vdivu_vdiv_vremu_vrem_op |
| vrem_op | The divide and remainder instructions are equivalent to the RISC-V standard scalar integer multiply/divides, with the same results for extreme inputs. |
norm:vdivu_vdiv_vremu_vrem_op |
| vwmul_op | The widening integer multiply instructions return the full 2*SEW-bit product from an SEW-bit*SEW-bit multiply. |
norm:vwmul_wmulu_vwmulsu_op |
| vwmulu_op | The widening integer multiply instructions return the full 2*SEW-bit product from an SEW-bit*SEW-bit multiply. |
norm:vwmul_wmulu_vwmulsu_op |
| vwmulsu_op | The widening integer multiply instructions return the full 2*SEW-bit product from an SEW-bit*SEW-bit multiply. |
norm:vwmul_wmulu_vwmulsu_op |
| vmacc_op | The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that overwrites the first multiplicand (vmadd, vnmsub). |
norm:vmacc_vnmsac_vmadd_vnmsub_op |
| The low half of the product is added or subtracted from the third operand. | norm:vmacc_vnmsac_vmadd_vnmsub_op_lowhalf | |
| vnmsac_op | The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that overwrites the first multiplicand (vmadd, vnmsub). |
norm:vmacc_vnmsac_vmadd_vnmsub_op |
| The low half of the product is added or subtracted from the third operand. | norm:vmacc_vnmsac_vmadd_vnmsub_op_lowhalf | |
| vmadd_op | The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that overwrites the first multiplicand (vmadd, vnmsub). |
norm:vmacc_vnmsac_vmadd_vnmsub_op |
| The low half of the product is added or subtracted from the third operand. | norm:vmacc_vnmsac_vmadd_vnmsub_op_lowhalf | |
| vnmsub_op | The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (vmacc, vnmsac) and one that overwrites the first multiplicand (vmadd, vnmsub). |
norm:vmacc_vnmsac_vmadd_vnmsub_op |
| The low half of the product is added or subtracted from the third operand. | norm:vmacc_vnmsac_vmadd_vnmsub_op_lowhalf | |
| vwmaccu_op | The widening integer multiply-add instructions add the full 2*SEW-bit product from a SEW-bit*SEW-bit multiply to a 2*SEW-bit value and produce a 2*SEW-bit result. |
norm:vwmaccu_vwmacc_vwmaccsu_vwmaccus_op |
| vwmacc_op | The widening integer multiply-add instructions add the full 2*SEW-bit product from a SEW-bit*SEW-bit multiply to a 2*SEW-bit value and produce a 2*SEW-bit result. |
norm:vwmaccu_vwmacc_vwmaccsu_vwmaccus_op |
| vwmaccsu_op | The widening integer multiply-add instructions add the full 2*SEW-bit product from a SEW-bit*SEW-bit multiply to a 2*SEW-bit value and produce a 2*SEW-bit result. |
norm:vwmaccu_vwmacc_vwmaccsu_vwmaccus_op |
| vwmaccus_op | The widening integer multiply-add instructions add the full 2*SEW-bit product from a SEW-bit*SEW-bit multiply to a 2*SEW-bit value and produce a 2*SEW-bit result. |
norm:vwmaccu_vwmacc_vwmaccsu_vwmaccus_op |
| vmerge_op | The vector integer merge instructions combine two source operands based on a mask. |
norm:vmerge_op |
| The vmerge instructions are encoded as masked instructions (vm=0). The instructions combine two sources as follows. At elements where the mask value is zero, the first operand is copied to the destination element, otherwise the second operand is copied to the destination element. The first operand is always a vector register group specified by vs2. The second operand is a vector register group specified by vs1 or a scalar x register specified by rs1 or a 5-bit sign-extended immediate. |
norm:vmerge_op_mask | |
| vmerge_all_elem | Unlike regular arithmetic instructions, the merge operates on all body elements (i.e., the set of elements from vstart up to the current vector length in vl). |
norm:vmerge_all_elem |
| vmv_op | The vector integer move instructions copy a source operand to a vector register group. The vmv.v.v variant copies a vector register group, whereas the vmv.v.x and vmv.v.i variants splat a scalar register or immediate to all active elements of the destination vector register group. |
norm:vmv_op |
| vmv_vs2_nv0_rsv | The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved. |
norm:vmv_vs2_nv0_rsv |
| vsaddu_op | Saturating forms of integer add and subtract are provided, for both signed and unsigned integers. |
norm:vsaddu_vsadd_vssubu_vssub_op |
| If the result would overflow the destination, the result is replaced with the closest representable value, and the vxsat bit is set. |
norm:vsaddu_vsadd_vssubu_vssub_op_overflow_vxsat_op_vsaddsub | |
| vsadd_op | Saturating forms of integer add and subtract are provided, for both signed and unsigned integers. |
norm:vsaddu_vsadd_vssubu_vssub_op |
| If the result would overflow the destination, the result is replaced with the closest representable value, and the vxsat bit is set. |
norm:vsaddu_vsadd_vssubu_vssub_op_overflow_vxsat_op_vsaddsub | |
| vssubu_op | Saturating forms of integer add and subtract are provided, for both signed and unsigned integers. |
norm:vsaddu_vsadd_vssubu_vssub_op |
| If the result would overflow the destination, the result is replaced with the closest representable value, and the vxsat bit is set. |
norm:vsaddu_vsadd_vssubu_vssub_op_overflow_vxsat_op_vsaddsub | |
| vssub_op | Saturating forms of integer add and subtract are provided, for both signed and unsigned integers. |
norm:vsaddu_vsadd_vssubu_vssub_op |
| If the result would overflow the destination, the result is replaced with the closest representable value, and the vxsat bit is set. |
norm:vsaddu_vsadd_vssubu_vssub_op_overflow_vxsat_op_vsaddsub | |
| vxsat_op_vsaddsub | If the result would overflow the destination, the result is replaced with the closest representable value, and the vxsat bit is set. |
norm:vsaddu_vsadd_vssubu_vssub_op_overflow_vxsat_op_vsaddsub |
| vaaddu_op | The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in vxrm. Computation is performed in infinite precision before rounding and truncating. |
norm:vaaddu_vaadd_vasubu_vasub_op |
| For vasub and vasubu, overflow is ignored and the result wraps around. | norm:vasub_vasubu_op_overflow | |
| vaadd_op | The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in vxrm. Computation is performed in infinite precision before rounding and truncating. |
norm:vaaddu_vaadd_vasubu_vasub_op |
| For vasub and vasubu, overflow is ignored and the result wraps around. | norm:vasub_vasubu_op_overflow | |
| vasubu_op | The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in vxrm. Computation is performed in infinite precision before rounding and truncating. |
norm:vaaddu_vaadd_vasubu_vasub_op |
| For vasub and vasubu, overflow is ignored and the result wraps around. | norm:vasub_vasubu_op_overflow | |
| vasub_op | The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in vxrm. Computation is performed in infinite precision before rounding and truncating. |
norm:vaaddu_vaadd_vasubu_vasub_op |
| For vasub and vasubu, overflow is ignored and the result wraps around. | norm:vasub_vasubu_op_overflow | |
| vsmul_op | The signed fractional multiply instruction produces a 2*SEW product of the two SEW inputs, then shifts the result right by SEW-1 bits, rounding these bits according to vxrm, then saturates the result to fit into SEW bits. |
norm:vsmul_op |
| If the result causes saturation, the vxsat bit is set. |
norm:vxsat_op_vsmul | |
| vxsat_op_vsmul | If the result causes saturation, the vxsat bit is set. |
norm:vxsat_op_vsmul |
| vssrl_op | These instructions shift the input value right, and round off the shifted out bits according to vxrm. The scaling right shifts have both zero-extending (vssrl) and sign-extending (vssra) forms. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. |
norm:vssrl_vssra_op |
| vssra_op | These instructions shift the input value right, and round off the shifted out bits according to vxrm. The scaling right shifts have both zero-extending (vssrl) and sign-extending (vssra) forms. The data to be shifted is in the vector register group specified by vs2 and the shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. |
norm:vssrl_vssra_op |
| vssrl_shamt | Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount. | norm:vssrl_vssra_shamt |
| vssra_shamt | Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount. | norm:vssrl_vssra_shamt |
| vnclipu_op | The vnclip instructions are used to pack a fixed-point value into a narrower destination. The instructions support rounding, scaling, and saturation into the final destination format. The source data is in the vector register group specified by vs2. The scaling shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. |
norm:vnclipu_vnclip_op |
| vnclip_op | The vnclip instructions are used to pack a fixed-point value into a narrower destination. The instructions support rounding, scaling, and saturation into the final destination format. The source data is in the vector register group specified by vs2. The scaling shift amount value can come from a vector register group vs1, a scalar integer register rs1, or a zero-extended 5-bit immediate. |
norm:vnclipu_vnclip_op |
| vnclipu_shamt | The low lg2(2*SEW) bits of the vector or scalar shift-amount value (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation) are used to control the right shift amount, which provides the scaling. |
norm:vnclipu_vnclip_shamt |
| vnclip_shamt | The low lg2(2*SEW) bits of the vector or scalar shift-amount value (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation) are used to control the right shift amount, which provides the scaling. |
norm:vnclipu_vnclip_shamt |
| vnclipu_overflow | For vnclipu, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer. |
norm:vnclipu_overflow |
| vnclip_overflow | For vnclip, the shifted rounded source value is treated as a signed integer and saturates if the result would overflow the destination viewed as a signed integer. |
norm:vnclip_overflow |
| vxsat_op_vnclip_u | If any destination element is saturated, the vxsat bit is set in the vxsat register. |
norm:vxsat_op_vnclip_u |
| V_fp_EEW_IEEE_nsupported_rsv | If the EEW of a vector floating-point operand does not correspond to a supported IEEE floating-point type, the instruction encoding is reserved. |
norm:V_fp_EEW_IEEE_nsupported_rsv |
| mstatus_FS_off_V_fp_ill | If the floating-point unit status field mstatus.FS is Off then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception. |
norm:mstatus_FS_off_V_fp_ill |
| mstatus_FS_dirty_V_fp | Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or f registers) must set mstatus.FS to Dirty. |
norm:mstatus_FS_dirty_V_fp |
| vsstatus_FS_off_hypervisor_V_fp_ill | If the hypervisor extension is implemented and V=1, the vsstatus.FS field is additionally in effect for vector floating-point instructions. If vsstatus.FS or mstatus.FS is Off then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception. |
norm:vsstatus_mstatus_FS_off_hypervisor_V_fp_ill |
| mstatus_FS_off_hypervisor_V_fp_ill | If the hypervisor extension is implemented and V=1, the vsstatus.FS field is additionally in effect for vector floating-point instructions. If vsstatus.FS or mstatus.FS is Off then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception. |
norm:vsstatus_mstatus_FS_off_hypervisor_V_fp_ill |
| vsstatus_FS_dirty_hypervisor_V_fp | Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or f registers) must set both mstatus.FS and vsstatus.FS to Dirty. |
norm:vsstatus_mstatus_FS_dirty_hypervisor_V_fp |
| mstatus_FS_dirty_hypervisor_V_fp | Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or f registers) must set both mstatus.FS and vsstatus.FS to Dirty. |
norm:vsstatus_mstatus_FS_dirty_hypervisor_V_fp |
| fflags_op_V_fp | A vector floating-point exception at any active floating-point element sets the standard FP exception flags in the fflags register. Inactive elements do not set FP exception flags. |
norm:fflags_op_V_fp |
| vfadd_op | # Floating-point add vfadd.vv vd, vs2, vs1, vm # Vector-vector vfadd.vf vd, vs2, rs1, vm # vector-scalar # Floating-point subtract vfsub.vv vd, vs2, vs1, vm # Vector-vector vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] |
norm:vfadd_vfsub_vfrsub_op |
| vfsub_op | # Floating-point add vfadd.vv vd, vs2, vs1, vm # Vector-vector vfadd.vf vd, vs2, rs1, vm # vector-scalar # Floating-point subtract vfsub.vv vd, vs2, vs1, vm # Vector-vector vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] |
norm:vfadd_vfsub_vfrsub_op |
| vfrsub_op | # Floating-point add vfadd.vv vd, vs2, vs1, vm # Vector-vector vfadd.vf vd, vs2, rs1, vm # vector-scalar # Floating-point subtract vfsub.vv vd, vs2, vs1, vm # Vector-vector vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] |
norm:vfadd_vfsub_vfrsub_op |
| vfwadd_op | # Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm # vector-vector vfwadd.vf vd, vs2, rs1, vm # vector-scalar vfwsub.vv vd, vs2, vs1, vm # vector-vector vfwsub.vf vd, vs2, rs1, vm # vector-scalar # Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW vfwadd.wv vd, vs2, vs1, vm # vector-vector vfwadd.wf vd, vs2, rs1, vm # vector-scalar vfwsub.wv vd, vs2, vs1, vm # vector-vector vfwsub.wf vd, vs2, rs1, vm # vector-scalar |
norm:vfwadd_op |
| vfmul_op | # Floating-point multiply vfmul.vv vd, vs2, vs1, vm # Vector-vector vfmul.vf vd, vs2, rs1, vm # vector-scalar # Floating-point divide vfdiv.vv vd, vs2, vs1, vm # Vector-vector vfdiv.vf vd, vs2, rs1, vm # vector-scalar # Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] |
norm:vfmul_vfdiv_vfrdiv_op |
| vfdiv_op | # Floating-point multiply vfmul.vv vd, vs2, vs1, vm # Vector-vector vfmul.vf vd, vs2, rs1, vm # vector-scalar # Floating-point divide vfdiv.vv vd, vs2, vs1, vm # Vector-vector vfdiv.vf vd, vs2, rs1, vm # vector-scalar # Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] |
norm:vfmul_vfdiv_vfrdiv_op |
| vfrdiv_op | # Floating-point multiply vfmul.vv vd, vs2, vs1, vm # Vector-vector vfmul.vf vd, vs2, rs1, vm # vector-scalar # Floating-point divide vfdiv.vv vd, vs2, vs1, vm # Vector-vector vfdiv.vf vd, vs2, rs1, vm # vector-scalar # Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] |
norm:vfmul_vfdiv_vfrdiv_op |
| vfwmul_op | # Widening floating-point multiply vfwmul.vv vd, vs2, vs1, vm # vector-vector vfwmul.vf vd, vs2, rs1, vm # vector-scalar |
norm:vfwmul_op |
| vfmacc_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfnmacc_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfmsac_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfnmsac_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfmadd_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfnmadd_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfmsub_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfnmsub_op | All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand. |
norm:vfmacc_vfnmacc_vfmsac_vfnmsac_vfmadd_vfnmadd_vfmsub_vfnmsub_op |
| vfwmacc_op | The widening floating-point fused multiply-add instructions all overwrite the wide addend with the result. The multiplier inputs are all SEW wide, while the addend and destination is 2*SEW bits wide. |
norm:vfwmacc_vfwnmacc_vfwmsac_vfwnmsac_op |
| vfwnmacc_op | The widening floating-point fused multiply-add instructions all overwrite the wide addend with the result. The multiplier inputs are all SEW wide, while the addend and destination is 2*SEW bits wide. |
norm:vfwmacc_vfwnmacc_vfwmsac_vfwnmsac_op |
| vfwmsac_op | The widening floating-point fused multiply-add instructions all overwrite the wide addend with the result. The multiplier inputs are all SEW wide, while the addend and destination is 2*SEW bits wide. |
norm:vfwmacc_vfwnmacc_vfwmsac_vfwnmsac_op |
| vfwnmsac_op | The widening floating-point fused multiply-add instructions all overwrite the wide addend with the result. The multiplier inputs are all SEW wide, while the addend and destination is 2*SEW bits wide. |
norm:vfwmacc_vfwnmacc_vfwmsac_vfwnmsac_op |
| vfsqrt_op | # Floating-point square root vfsqrt.v vd, vs2, vm # Vector-vector square root |
norm:vfsqrt_op |
| vfrsqrt7_op | This is a unary vector-vector instruction that returns an estimate of 1/sqrt(x) accurate to 7 bits. |
norm:vfrsqrt7_op |
| For the non-exceptional cases, the low bit of the exponent and the six high bits of significand (after the leading one) are concatenated and used to address the following table. The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero. Subnormal inputs are normalized and the exponent adjusted appropriately before the lookup. The output exponent is chosen to make the result approximate the reciprocal of the square root of the argument. |
norm:vfrsqrt7_op_unex | |
| More precisely, the result is computed as follows. Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise. If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit. The output exponent equals floor((3*B - 1 - the normalized input exponent) / 2), where B is the exponent bias. The output sign equals the input sign. |
norm:vfrsqrt7_op_precise | |
| vfrec7_op | This is a unary vector-vector instruction that returns an estimate of 1/x accurate to 7 bits. |
norm:vfrec7_op |
| For the non-exceptional cases, the seven high bits of significand (after the leading one) are used to address the following table. The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero. Subnormal inputs are normalized and the exponent adjusted appropriately before the lookup. The output exponent is chosen to make the result approximate the reciprocal of the argument, and subnormal outputs are denormalized accordingly. |
norm:vfrec7_op_unex | |
| More precisely, the result is computed as follows. Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise. The normalized output exponent equals (2*B - 1 - the normalized input exponent). If the normalized output exponent is outside the range [-1, 2*B], the result corresponds to one of the exceptional cases in the table above. |
norm:vfrec7_op_precise | |
| If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit. Otherwise, the normalized input significand equals the input significand. The following table gives the seven MSBs of the normalized output significand as a function of the seven MSBs of the normalized input significand; the other bits of the normalized output significand are zero. |
norm:vfrec7_op_subnorm | |
| If the normalized output exponent is 0 or -1, the result is subnormal: the output exponent is 0, and the output significand is given by concatenating a 1 bit to the left of the normalized output significand, then shifting that quantity right by 1 minus the normalized output exponent. Otherwise, the output exponent equals the normalized output exponent, and the output significand equals the normalized output significand. The output sign equals the input sign. |
norm:vfrec7_op_output | |
| vfmin_op | The vector floating-point vfmin and vfmax instructions have the same behavior as the corresponding scalar floating-point instructions in version 2.2 of the RISC-V F/D/Q extension: they perform the minimumNumber or maximumNumber operation on active elements. |
norm:vfmin_vfmax_op |
| vfmax_op | The vector floating-point vfmin and vfmax instructions have the same behavior as the corresponding scalar floating-point instructions in version 2.2 of the RISC-V F/D/Q extension: they perform the minimumNumber or maximumNumber operation on active elements. |
norm:vfmin_vfmax_op |
| vfsgnj_op | Vector versions of the scalar sign-injection instructions. The result takes all bits except the sign bit from the vector vs2 operands. |
norm:vfsgnj_vfsgnjn_vfsgnjx_op |
| vfsgnjn_op | Vector versions of the scalar sign-injection instructions. The result takes all bits except the sign bit from the vector vs2 operands. |
norm:vfsgnj_vfsgnjn_vfsgnjx_op |
| vfsgnjx_op | Vector versions of the scalar sign-injection instructions. The result takes all bits except the sign bit from the vector vs2 operands. |
norm:vfsgnj_vfsgnjn_vfsgnjx_op |
| vmfeq_op | These vector FP compare instructions compare two source operands and write the comparison result to a mask register. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_op |
| vmfne_op | These vector FP compare instructions compare two source operands and write the comparison result to a mask register. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_op |
| vmflt_op | These vector FP compare instructions compare two source operands and write the comparison result to a mask register. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_op |
| vmfle_op | These vector FP compare instructions compare two source operands and write the comparison result to a mask register. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_op |
| vmfgt_op | These vector FP compare instructions compare two source operands and write the comparison result to a mask register. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_op |
| vmfge_op | These vector FP compare instructions compare two source operands and write the comparison result to a mask register. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_op |
| vmfeq_vd_single_vreg | The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_single_vreg |
| vmfne_vd_single_vreg | The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_single_vreg |
| vmflt_vd_single_vreg | The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_single_vreg |
| vmfle_vd_single_vreg | The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_single_vreg |
| vmfgt_vd_single_vreg | The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_single_vreg |
| vmfge_vd_single_vreg | The destination mask vector is always held in a single vector register, with a layout of elements as described in sec-mask-register-layout. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_single_vreg |
| vmfeq_vd_eq_v0 | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_eq_v0 |
| vmfne_vd_eq_v0 | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_eq_v0 |
| vmflt_vd_eq_v0 | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_eq_v0 |
| vmfle_vd_eq_v0 | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_eq_v0 |
| vmfgt_vd_eq_v0 | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_eq_v0 |
| vmfge_vd_eq_v0 | The destination mask vector register may be the same as the source vector mask register (v0). |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_vd_eq_v0 |
| vmfeq_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_tail_agnostic |
| vmfne_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_tail_agnostic |
| vmflt_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_tail_agnostic |
| vmfle_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_tail_agnostic |
| vmfgt_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_tail_agnostic |
| vmfge_tail_agnostic | Compares write mask registers, and so always operate under a tail-agnostic policy. |
norm:vmfeq_vmfne_vmflt_vmfle_vmfgt_vmfge_tail_agnostic |
| vmfeq_sNaN_invalid | vmfeq and vmfne raise the invalid operation exception only on signaling NaN inputs. |
norm:vmfeq_vmfne_sNaN_invalid |
| vmfne_sNaN_invalid | vmfeq and vmfne raise the invalid operation exception only on signaling NaN inputs. |
norm:vmfeq_vmfne_sNaN_invalid |
| vmflt_sqNaN_invalid | vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both signaling and quiet NaN inputs. |
norm:vmflt_vmfle_vmfgt_vmfge_sqNaN_invalid |
| vmfle_sqNaN_invalid | vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both signaling and quiet NaN inputs. |
norm:vmflt_vmfle_vmfgt_vmfge_sqNaN_invalid |
| vmfgt_sqNaN_invalid | vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both signaling and quiet NaN inputs. |
norm:vmflt_vmfle_vmfgt_vmfge_sqNaN_invalid |
| vmfge_sqNaN_invalid | vmflt, vmfle, vmfgt, and vmfge raise the invalid operation exception on both signaling and quiet NaN inputs. |
norm:vmflt_vmfle_vmfgt_vmfge_sqNaN_invalid |
| vmfne_vdval1_NaN | vmfne writes 1 to the destination element when either operand is NaN, |
norm:vmfne_vdval1_NaN |
| vmfeq_vdval0_NaN | whereas the other compares write 0 when either operand is NaN. |
norm:vmfeq_vmflt_vmfle_vmfgt_vmfge_vdval0_NaN |
| vmflt_vdval0_NaN | whereas the other compares write 0 when either operand is NaN. |
norm:vmfeq_vmflt_vmfle_vmfgt_vmfge_vdval0_NaN |
| vmfle_vdval0_NaN | whereas the other compares write 0 when either operand is NaN. |
norm:vmfeq_vmflt_vmfle_vmfgt_vmfge_vdval0_NaN |
| vmfgt_vdval0_NaN | whereas the other compares write 0 when either operand is NaN. |
norm:vmfeq_vmflt_vmfle_vmfgt_vmfge_vdval0_NaN |
| vmfge_vdval0_NaN | whereas the other compares write 0 when either operand is NaN. |
norm:vmfeq_vmflt_vmfle_vmfgt_vmfge_vdval0_NaN |
| vfclass_op | This is a unary vector-vector instruction that operates in the same way as the scalar classify instruction. |
norm:vfclass_op |
| The 10-bit mask produced by this instruction is placed in the least-significant bits of the result elements. The upper (SEW-10) bits of the result are filled with zeros. |
norm:vfclass_op_result | |
| vfclass_SEWge16 | The instruction is only defined for SEW=16b and above, so the result will always fit in the destination elements. |
norm:vfclass_SEWge16 |
| vfmerge_op | A vector-scalar floating-point merge instruction is provided, | norm:vfmerge_op |
| At elements where the mask value is zero, the first vector operand is copied to the destination element, otherwise a scalar floating-point register value is copied to the destination element. |
norm:vfmerge_op_mask | |
| vfmerge_all_elem | operates on all body elements from vstart up to the current vector length in vl regardless of mask value. |
norm:vfmerge_all_elem |
| vfmv_op | The vector floating-point move instruction splats a floating-point scalar operand to a vector register group. The instruction copies a scalar f register value to all active elements of a vector register group. |
norm:vfmv_op |
| vfmv_vs2_nv0_rsv | The instruction must have the vs2 field set to v0, with all other values for vs2 reserved. |
norm:vfmv_vs2_nv0_rsv |
| vfcvt_op | Conversion operations are provided to convert to and from floating-point values and unsigned and signed integers, where both source and destination are SEW wide. |
norm:vfcvt_op |
| The conversions follow the same rules on exceptional conditions as the scalar conversion instructions. |
norm:vfcvt_op_exceptions | |
| The conversions use the dynamic rounding mode in frm, except for the rtz variants, which round towards zero. |
norm:vfcvt_op_frm | |
| vfwcvt_op | A set of conversion instructions is provided to convert between narrower integer and floating-point datatypes to a type of twice the width. |
norm:vfwcvt_op |
| vfwcvt_vreg_constr | These instructions have the same constraints on vector register overlap as other widening instructions (see sec-widening). |
norm:vfwcvt_vreg_constr |
| vfncvt_op | A set of conversion instructions is provided to convert wider integer and floating-point datatypes to a type of half the width. |
norm:vfncvt_op |
| vfncvt_vreg_constr | These instructions have the same constraints on vector register overlap as other narrowing instructions (see sec-narrowing). |
norm:vfncvt_vreg_constr |
| vreduction_scalar | Vector reduction operations take a vector register group of elements and a scalar held in element 0 of a vector register, and perform a reduction using some binary operator, to produce a scalar result in element 0 of a vector register. |
norm:vreduction_scalar_def |
| The scalar input and output operands are held in element 0 of a single vector register, not a vector register group, so any vector register can be the scalar source or destination of a vector reduction regardless of LMUL setting. |
norm:vreduction_scalar_disregard_LMUL | |
| Inactive elements from the source vector register group are excluded from the reduction, but the scalar operand is always included regardless of the mask values. |
norm:vreduction_scalar_disregard_maskval | |
| vreduction_vd_overlap_vs | The destination vector register can overlap the source operands, including the mask register. |
norm:vreduction_vd_overlap_vs |
| vreduction_tail_agnostic | The other elements in the destination vector register ( 0 < index < VLEN/SEW) are considered the tail and are managed with the current tail agnostic/undisturbed policy. |
norm:vreduction_tail_policy |
| vreduction_vl_0 | If vl=0, no operation is performed and the destination register is not updated. |
norm:vreduction_vl_0 |
| vreduction_trap | Traps on vector reduction instructions are always reported with a vstart of 0. |
norm:vreduction_trap |
| vreduction_vstart_n0_ill | Vector reduction operations raise an illegal-instruction exception if vstart is non-zero. |
norm:vreduction_vstart_n0_ill |
| vredsum_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredmaxu_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredmax_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredminu_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredmin_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredand_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredor_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredxor_op | All operands and results of single-width reduction instructions have the same SEW width. |
norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_op |
| vredsum_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vredmaxu_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vredmax_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vredminu_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vredmin_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vredand_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vredor_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vredxor_overflow | Overflows wrap around on arithmetic sums. | norm:vredsum_vredmaxu_vredmax_vredminu_vredmin_vredand_vredor_vredxor_overflow |
| vwredsumu_op | The unsigned vwredsumu.vs instruction zero-extends the SEW-wide vector elements before summing them, then adds the 2*SEW-width scalar element, and stores the result in a 2*SEW-width scalar element. |
norm:vwredsumu_op |
| For both vwredsumu.vs and vwredsum.vs, overflows wrap around. | norm:vwredsumu_vwredsum_op_overflow | |
| vwredsum_op | The vwredsum.vs instruction sign-extends the SEW-wide vector elements before summing them. |
norm:vwredsum_op |
| For both vwredsumu.vs and vwredsum.vs, overflows wrap around. | norm:vwredsumu_vwredsum_op_overflow | |
| vfredosum_op | The vfredosum instruction must sum the floating-point values in element order, starting with the scalar in vs1[0] |
norm:vfredosum_op |
| where each addition operates identically to the scalar floating-point instructions in terms of raising exception flags and generating or propagating special values. |
norm:vfredosum_op_exceptions | |
| When the operation is masked (vm=0), the masked-off elements do not affect the result or the exception flags. |
norm:vfredosum_maskoff | |
| vfredusum_op | The implementation must produce a result equivalent to a reduction tree composed of binary operator nodes, with the inputs being elements from the source vector register group (vs2) and the source scalar value (vs1[0]). Each operator in the tree accepts two inputs and produces one result. Each operator first computes an exact sum as a RISC-V scalar floating-point addition with infinite exponent range and precision, then converts this exact sum to a floating-point format with range and precision each at least as great as the element floating-point format indicated by SEW, rounding using the currently active floating-point dynamic rounding mode and raising exception flags as necessary. A different floating-point range and precision may be chosen for the result of each operator. A node where one input is derived only from elements masked-off or beyond the active vector length may either treat that input as the additive identity of the appropriate EEW or simply copy the other input to its output. The rounded result from the root node in the tree is converted (rounded again, using the dynamic rounding mode) to the standard floating-point format indicated by SEW. |
norm:vfredusum_op |
| vfredusum_additive_impl | The additive identity is +0.0 when rounding down (towards -{inf}) or -0.0 for all other rounding modes. |
norm:vfredusum_additive_impl |
| vfredusum_redtree | The reduction tree structure must be deterministic for a given value in vtype and vl. |
norm:vfredusum_redtree |
| vfredmin_op | The vfredmin and vfredmax instructions reduce the scalar argument in vs1[0] and active elements in vs2 using the minimumNumber and maximumNumber operations, respectively. |
norm:vfredmin_vfredmax_op |
| vfredmax_op | The vfredmin and vfredmax instructions reduce the scalar argument in vs1[0] and active elements in vs2 using the minimumNumber and maximumNumber operations, respectively. |
norm:vfredmin_vfredmax_op |
| vfwredosum_op | Widening forms of the sum reductions are provided that read and write a double-width reduction result. |
norm:vfwredosum_vfwredusum_op |
| The reduction of the SEW-width elements is performed as in the single-width reduction case, with the elements in vs2 promoted to 2*SEW bits before adding to the 2*SEW-bit accumulator. |
norm:vfwredosum_vfwredusum_op_reduction | |
| vfwredusum_op | Widening forms of the sum reductions are provided that read and write a double-width reduction result. |
norm:vfwredosum_vfwredusum_op |
| The reduction of the SEW-width elements is performed as in the single-width reduction case, with the elements in vs2 promoted to 2*SEW bits before adding to the 2*SEW-bit accumulator. |
norm:vfwredosum_vfwredusum_op_reduction | |
| vmask_maskreg | Vector mask-register logical operations operate on mask registers. Each element in a mask register is a single bit, |
norm:vmask_maskreg_def |
| vmask_vd_overlap_vs | The destination vector register may be the same as either source vector register. |
norm:vmask_vd_overlap_vs |
| vmask_vstart | As with other vector instructions, the elements with indices less than vstart are unchanged, and vstart is reset to zero after execution. |
norm:vmask_vstart |
| vmasklogical_unmasked | Vector mask logical instructions are always unmasked, | norm:vmasklogical_unmasked |
| vmasklogical_masked_rsv | so there are no inactive elements, and the encodings with vm=0 are reserved. |
norm:vmasklogical_masked_rsv |
| vmasklogical_tail_agnostic | Mask elements past vl, the tail elements, are always updated with a tail-agnostic policy. |
norm:vmasklogical_tail_agnostic |
| vmand_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vmnand_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vmandn_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vmxor_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vmor_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vmnor_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vmorn_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vmxnor_op | vmand.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 # vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 # vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) |
norm:vmand_vmnand_vmandn_vmxor_vmor_vmnor_vmorn_vmxnor_op |
| vcpop_vs_single_vreg | The source operand is a single vector register holding mask register values as described in sec-mask-register-layout. |
norm:vcpop_vs_single_vreg |
| vcpop_op | The vcpop.m instruction counts the number of mask elements of the active elements of the vector source mask register that have the value 1 and writes the result to a scalar x register. |
norm:vcpop_op |
| The operation can be performed under a mask, in which case only the masked elements are counted. |
norm:vcpop_op_mask | |
| vcpop_vl0 | The vcpop.m instruction writes x[rd] even if vl=0 (with the value 0, since no mask elements are active). |
norm:vcpop_vl0 |
| vcpop_trap | Traps on vcpop.m are always reported with a vstart of 0. | norm:vcpop_trap |
| vcpop_vstart_n0_ill | The vcpop.m instruction will raise an illegal-instruction exception if vstart is non-zero. |
norm:vcpop_vstart_n0_ill |
| vfirst_op | The vfirst instruction finds the lowest-numbered active element of the source mask vector that has the value 1 and writes that element's index to a GPR. If no active element has the value 1, -1 is written to the GPR. |
norm:vfirst_op |
| vfirst_vl0 | The vfirst.m instruction writes x[rd] even if vl=0 (with the value -1, since no mask elements are active). |
norm:vfirst_vl0 |
| vfirst_trap | Traps on vfirst are always reported with a vstart of 0. | norm:vfirst_trap |
| vfirst_vstart_n0_ill | The vfirst instruction will raise an illegal-instruction exception if vstart is non-zero. |
norm:vfirst_vstart_n0_ill |
| vmsbf_op | The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first active source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the active elements of the source vector, then all active elements in the destination are written with a 1. |
norm:vmsbf_op |
| vmsbf_tail_agnostic | The tail elements in the destination mask register are updated under a tail-agnostic policy. |
norm:vmsbf_tail_agnostic |
| vmsbf_trap | Traps on vmsbf.m are always reported with a vstart of 0. | norm:vmsbf_trap |
| vmsbf_vstart_n0_ill | The vmsbf instruction will raise an illegal-instruction exception if vstart is non-zero. |
norm:vmsbf_vstart_n0_ill |
| vmsbf_vreg_constr | The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (v0). |
norm:vmsbf_vreg_constr |
| vmsif_op | The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit. |
norm:vmsif_op |
| vmsif_tail_agnostic | The tail elements in the destination mask register are updated under a tail-agnostic policy. |
norm:vmsif_tail_agnostic |
| vmsif_trap | Traps on vmsif.m are always reported with a vstart of 0. | norm:vmsif_trap |
| vmsif_vstart_n0_ill | The vmsif instruction will raise an illegal-instruction exception if vstart is non-zero. |
norm:vmsif_vstart_n0_ill |
| vmsif_vreg_constr | The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (v0). |
norm:vmsif_vreg_constr |
| vmsof_op | The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any. |
norm:vmsof_op |
| vmsof_tail_agnostic | The tail elements in the destination mask register are updated under a tail-agnostic policy. |
norm:vmsof_tail_agnostic |
| vmsof_trap | Traps on vmsof.m are always reported with a vstart of 0. | norm:vmsof_trap |
| vmsof_vstart_n0_ill | The vmsof instruction will raise an illegal-instruction exception if vstart is non-zero. |
norm:vmsof_vstart_n0_ill |
| vmsof_vreg_constr | The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (v0). |
norm:vmsof_vreg_constr |
| viota_op | The viota.m instruction reads a source vector mask register and writes to each element of the destination vector register group the sum of all the bits of elements in the mask register whose index is less than the element, e.g., a parallel prefix sum of the mask values. |
norm:viota_op |
| This instruction can be masked, in which case only the enabled elements contribute to the sum. |
norm:viota_op_masked | |
| The result value is zero-extended to fill the destination element if SEW is wider than the result. |
norm:viota_op_zext | |
| If the result value would overflow the destination SEW, the least-significant SEW bits are retained. |
norm:viota_op_overflow | |
| viota_trap | Traps on viota.m are always reported with a vstart of 0, | norm:viota_trap |
| viota_vstart_n0_ill | An illegal-instruction exception is raised if vstart is non-zero. |
norm:viota_vstart_n0_ill |
| viota_vreg_constr | The destination register group cannot overlap the source register and, if masked, cannot overlap the mask register (v0). |
norm:viota_vreg_constr |
| vid_op | The vid.v instruction writes each element's index to the destination vector register group, from 0 to vl-1. |
norm:vid_op |
| The instruction can be masked. Masking does not change the index value written to active elements. |
norm:vid_op_mask | |
| The result value is zero-extended to fill the destination element if SEW is wider than the result. |
norm:vid_op_zext | |
| If the result value would overflow the destination SEW, the least-significant SEW bits are retained. |
norm:vid_op_overflow | |
| vid_vs2_nv0_rsv | The vs2 field of the instruction must be set to v0, otherwise the encoding is reserved. |
norm:vid_vs2_nv0_rsv |
| vmv-x-s_ignoreLMUL | The instructions ignore LMUL and vector register groups. | norm:vmv-x-s_vmv-s-x_ignoreLMUL |
| vmv-s-x_ignoreLMUL | The instructions ignore LMUL and vector register groups. | norm:vmv-x-s_vmv-s-x_ignoreLMUL |
| vmv-x-s_op | The vmv.x.s instruction copies a single SEW-wide element from index 0 of the source vector register to a destination integer register. If SEW > XLEN, the least-significant XLEN bits are transferred and the upper SEW-XLEN bits are ignored. If SEW < XLEN, the value is sign-extended to XLEN bits. |
norm:vmv-x-s_op |
| vmv-x-s_vstart_ge_vl | vmv.x.s performs its operation even if vstart {ge} vl or vl=0. | norm:vmv-x-s_vstartgevl_vl0 |
| vmv-x-s_vl0 | vmv.x.s performs its operation even if vstart {ge} vl or vl=0. | norm:vmv-x-s_vstartgevl_vl0 |
| vmv-s-x_op | The vmv.s.x instruction copies the scalar integer register to element 0 of the destination vector register. If SEW < XLEN, the least-significant bits are copied and the upper XLEN-SEW bits are ignored. If SEW > XLEN, the value is sign-extended to SEW bits. The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy. |
norm:vmv-s-x_op |
| vmv-s-x_vstart_ge_vl | If vstart {ge} vl, no operation is performed and the destination register is not updated. |
norm:vmv-s-x_vstart_ge_vl |
| vmv-s-x_masked_rsv | The encodings corresponding to the masked versions (vm=0) of vmv.x.s and vmv.s.x are reserved. |
norm:vmv-s-x_vmv-x-s_masked_rsv |
| vmv-x-s_masked_rsv | The encodings corresponding to the masked versions (vm=0) of vmv.x.s and vmv.s.x are reserved. |
norm:vmv-s-x_vmv-x-s_masked_rsv |
| vfmv-f-s_ignoreLMUL | The instructions ignore LMUL and vector register groups. | norm:vfmv-f-s_vfmv-s-f_ignoreLMUL |
| vfmv-s-f_ignoreLMUL | The instructions ignore LMUL and vector register groups. | norm:vfmv-f-s_vfmv-s-f_ignoreLMUL |
| vfmv-f-s_op | The vfmv.f.s instruction copies a single SEW-wide element from index 0 of the source vector register to a destination scalar floating-point register. |
norm:vfmv-f-s_op |
| vfmv-s-f_op | The vfmv.s.f instruction copies the scalar floating-point register to element 0 of the destination vector register. The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy. |
norm:vfmv-s-f_op |
| vfmv-s-f_vstart_ge_vl | If vstart {ge} vl, no operation is performed and the destination register is not updated. |
norm:vfmv-s-f_vstart_ge_vl |
| vfmv-s-f_masked_rsv | The encodings corresponding to the masked versions (vm=0) of vfmv.f.s and vfmv.s.f are reserved. |
norm:vfmv-s-f_masked_rsv |
| vslideup_vstart_ge_vl | For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart {ge} vl, the instruction performs no operation and leaves the destination vector register unchanged. |
norm:vslide_vstart_ge_vl |
| vslidedown_vstart_ge_vl | For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart {ge} vl, the instruction performs no operation and leaves the destination vector register unchanged. |
norm:vslide_vstart_ge_vl |
| vslide1up_vstart_ge_vl | For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart {ge} vl, the instruction performs no operation and leaves the destination vector register unchanged. |
norm:vslide_vstart_ge_vl |
| vslide1down_vstart_ge_vl | For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart {ge} vl, the instruction performs no operation and leaves the destination vector register unchanged. |
norm:vslide_vstart_ge_vl |
| vfslide1up_vstart_ge_vl | For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart {ge} vl, the instruction performs no operation and leaves the destination vector register unchanged. |
norm:vslide_vstart_ge_vl |
| vfslide1down_vstart_ge_vl | For all of the vslideup, vslidedown, v[f]slide1up, and v[f]slide1down instructions, if vstart {ge} vl, the instruction performs no operation and leaves the destination vector register unchanged. |
norm:vslide_vstart_ge_vl |
| vslideup_mask | The slide instructions may be masked, with mask element i controlling whether destination element i is written. The mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vslide_mask |
| vslidedown_mask | The slide instructions may be masked, with mask element i controlling whether destination element i is written. The mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vslide_mask |
| vslide1up_mask | The slide instructions may be masked, with mask element i controlling whether destination element i is written. The mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vslide_mask |
| vslide1down_mask | The slide instructions may be masked, with mask element i controlling whether destination element i is written. The mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vslide_mask |
| vfslide1up_mask | The slide instructions may be masked, with mask element i controlling whether destination element i is written. The mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vslide_mask |
| vfslide1down_mask | The slide instructions may be masked, with mask element i controlling whether destination element i is written. The mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vslide_mask |
| vslideup_op | For vslideup, the value in vl specifies the maximum number of destination elements that are written. The start index (OFFSET) for the destination can be either specified using an unsigned integer in the x register specified by rs1, or a 5-bit immediate, zero-extended to XLEN bits. If XLEN > SEW, OFFSET is not truncated to SEW bits. Destination elements OFFSET through vl-1 are written if unmasked and if OFFSET < vl. |
norm:vslideup_op |
| vslideup_vreg_constr | The destination vector register group for vslideup cannot overlap the source vector register group, otherwise the instruction encoding is reserved. |
norm:vslideup_vreg_constr |
| vslidedown_op | For vslidedown, the value in vl specifies the maximum number of destination elements that are written. The remaining elements past vl are handled according to the current tail policy (sec-agnostic). |
norm:vslidedown_op |
| The start index (OFFSET) for the source can be either specified using an unsigned integer in the x register specified by rs1, or a 5-bit immediate, zero-extended to XLEN bits. If XLEN > SEW, OFFSET is not truncated to SEW bits. |
norm:vslidedown_op_src | |
| vslide1up-vx_op | The vslide1up instruction places the x register argument at location 0 of the destination vector register group, provided that element 0 is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy. If XLEN < SEW, the value is sign-extended to SEW bits. If XLEN > SEW, the least-significant bits are copied over and the high XLEN-SEW bits are ignored. |
norm:vslide1up-vx_op |
| The remaining active vl-1 elements are copied over from index i in the source vector register group to index i+1 in the destination vector register group. |
norm:vslide1up-vx_op_rem_elem | |
| The vl register specifies the maximum number of destination vector register elements updated with source values, and remaining elements past vl are handled according to the current tail policy (sec-agnostic). |
norm:vslide1up-vx_op_vl | |
| vslide1up-vx_vreg_constr | The vslide1up instruction requires that the destination vector register group does not overlap the source vector register group. Otherwise, the instruction encoding is reserved. |
norm:vslide1up-vx_vreg_constr |
| vslide1up-vf_op | The vfslide1up instruction is defined analogously to vslide1up, but sources its scalar argument from an f register. |
norm:vslide1up-vf_op |
| vslide1down-vx_op | The vslide1down instruction copies the first vl-1 active elements values from index i+1 in the source vector register group to index i in the destination vector register group. |
norm:vslide1down-vx_op |
| The vl register specifies the maximum number of destination vector register elements written with source values, and remaining elements past vl are handled according to the current tail policy (sec-agnostic). |
norm:vslide1down-vx_op_vl | |
| The vslide1down instruction places the x register argument at location vl-1 in the destination vector register, provided that element vl-1 is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy. If XLEN < SEW, the value is sign-extended to SEW bits. If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored. |
norm:vslide1down-vx_op_details | |
| vslide1down-vf_op | The vfslide1down instruction is defined analogously to vslide1down, but sources its scalar argument from an f register. |
norm:vslide1down-vf_op |
| vrgather_vs2_uint | The index values in the second vector are treated as unsigned integers. |
norm:vrgather_vrgatherei16_vs2_uint |
| vrgatherei16_vs2_uint | The index values in the second vector are treated as unsigned integers. |
norm:vrgather_vrgatherei16_vs2_uint |
| vrgather_vs_ignore_vl | The source vector can be read at any index < VLMAX regardless of vl. |
norm:vrgather_vrgatherei16_vs_ignore_vl |
| vrgatherei16_vs_ignore_vl | The source vector can be read at any index < VLMAX regardless of vl. |
norm:vrgather_vrgatherei16_vs_ignore_vl |
| vrgather_vl | The maximum number of elements to write to the destination register is given by vl, |
norm:vrgather_vrgatherei16_vl |
| vrgatherei16_vl | The maximum number of elements to write to the destination register is given by vl, |
norm:vrgather_vrgatherei16_vl |
| vrgather_tail | and the remaining elements past vl are handled according to the current tail policy (sec-agnostic). |
norm:vrgather_vrgatherei16_tail |
| vrgatherei16_tail | and the remaining elements past vl are handled according to the current tail policy (sec-agnostic). |
norm:vrgather_vrgatherei16_tail |
| vrgather_mask | The operation can be masked, and the mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vrgather_vrgatherei16_mask |
| vrgatherei16_mask | The operation can be masked, and the mask undisturbed/agnostic policy is followed for inactive elements. |
norm:vrgather_vrgatherei16_mask |
| vrgather-vv_sew_lmul | The vrgather.vv form uses SEW/LMUL for both the data and indices. |
norm:vrgather-vv_sew_lmul |
| vrgatherei16-vv_sew_lmul | The vrgatherei16.vv form uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1. |
norm:vrgatherei16-vv_sew_lmul |
| vrgather_id_ge_VLMAX | If an element index is out of range ( vs1[i] {ge} VLMAX ) then zero is returned for the element value. |
norm:vrgather_vrgatherei16_id_ge_VLMAX |
| vrgatherei16_id_ge_VLMAX | If an element index is out of range ( vs1[i] {ge} VLMAX ) then zero is returned for the element value. |
norm:vrgather_vrgatherei16_id_ge_VLMAX |
| vrgather-vx_op | Vector-scalar and vector-immediate forms of the register gather are also provided. These read one element from the source vector at the given index, and write this value to the active elements of the destination vector register. The index value in the scalar register and the immediate, zero-extended to XLEN bits, are treated as unsigned integers. If XLEN > SEW, the index value is not truncated to SEW bits. |
norm:vrgather-vx_vrgather-vi_op |
| vrgather-vi_op | Vector-scalar and vector-immediate forms of the register gather are also provided. These read one element from the source vector at the given index, and write this value to the active elements of the destination vector register. The index value in the scalar register and the immediate, zero-extended to XLEN bits, are treated as unsigned integers. If XLEN > SEW, the index value is not truncated to SEW bits. |
norm:vrgather-vx_vrgather-vi_op |
| vrgather_vreg_constr | For any vrgather instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved. |
norm:vrgather_vrgatherei16_vreg_constr |
| vrgatherei16_vreg_constr | For any vrgather instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved. |
norm:vrgather_vrgatherei16_vreg_constr |
| vcompress_op | The vector mask register specified by vs1 indicates which of the first vl elements of vector register group vs2 should be extracted and packed into contiguous elements at the beginning of vector register vd. The remaining elements of vd are treated as tail elements according to the current tail policy (sec-agnostic). |
norm:vcompress_op |
| vcompress_enc | T`vcompress` is encoded as an unmasked instruction (vm=1). | norm:vcompress_enc |
| vcompress_masked_rsv | The equivalent masked instruction (vm=0) is reserved. |
norm:vcompress_masked_rsv |
| vcompress_vreg_constr | The destination vector register group cannot overlap the source vector register group or the source mask register, otherwise the instruction encoding is reserved. |
norm:vcompress_vreg_constr |
| vcompress_trap | A trap on a vcompress instruction is always reported with a vstart of 0. |
norm:vcompress_trap |
| vcompress_vstart_n0_ill | Executing a vcompress instruction with a non-zero vstart raises an illegal-instruction exception. |
norm:vcompress_vstart_n0_ill |
| vmv-nr-r_op | The vmv<nr>r.v instructions copy whole vector registers (i.e., all VLEN bits) and can copy whole vector register groups. The nr value in the opcode is the number of individual vector registers, NREG, to copy. The instructions operate as if EEW=SEW, EMUL = NREG, effective length evl= EMUL * VLEN/SEW. |
norm:vmv-nr-r_op |
| vmv-nr-r_enc | The instruction is encoded as an OPIVI instruction. The number of vector registers to copy is encoded in the low three bits of the simm field (simm[2:0]) using the same encoding as the nf[2:0] field for memory instructions (Figure fig-nf), i.e., simm[2:0] = NREG-1. |
norm:vmv-nr-r_enc |
| vmv-nr-r_nreg_rsv | The value of NREG must be 1, 2, 4, or 8, and values of simm[4:0] other than 0, 1, 3, and 7 are reserved. |
norm:vmv-nr-r_nreg_rsv |
| vmv-nr-r_vreg_constr | The source and destination vector register numbers must be aligned appropriately for the vector register group size, |
norm:vmv-nr-r_vreg_constr |
| vmv-nr-r_unaligned_rsv | encodings with other vector register numbers are reserved. |
norm:vmv-nr-r_unaligned_rsv |
| epc_op_V_trap | On a trap during a vector instruction (caused by either a synchronous exception or an asynchronous interrupt), the existing *epc CSR is written with a pointer to the trapping vector instruction, while the vstart CSR contains the element index on which the trap was taken. |
norm:epc_vstart_op_V_trap |
| vstart_op_V_trap | On a trap during a vector instruction (caused by either a synchronous exception or an asynchronous interrupt), the existing *epc CSR is written with a pointer to the trapping vector instruction, while the vstart CSR contains the element index on which the trap was taken. |
norm:epc_vstart_op_V_trap |
| Zve_XLEN | Any of these extensions can be added to base ISAs with XLEN=32 or XLEN=64. |
norm:Zve_XLEN |
| Zve32f_Zve64x_dependent_Zve32x | The Zve32f and Zve64x extensions depend on the Zve32x extension. | norm:Zve32f_Zve64x_dependent_Zve32x |
| Zve64f_dependent_Zve32f_Zve64x | The Zve64f extension depends on the Zve32f and Zve64x extensions. | norm:Zve64f_dependent_Zve32f_Zve64x |
| Zve64d_dependent_Zve64f | The Zve64d extension depends on the Zve64f extension. | norm:Zve64d_dependent_Zve64f |
| Zve_precise_traps | All Zve* extensions have precise traps. | norm:Zve_precise_traps |
| Zve_eew | All Zve* extensions provide support for EEW of 8, 16, and 32, and Zve64* extensions also support EEW of 64. |
norm:Zve_eew |
| Zve_nsupport_eew64_xlen32 | All Zve* extensions support all vector load and store instructions (sec-vector-memory), except Zve64* extensions do not support EEW=64 for index values when XLEN=32. |
norm:Zve_nsupport_eew64_xlen32 |
| Zve64_eew64_nsupport_vmulh | All Zve* extensions support all vector integer instructions (sec-vector-integer), except that the vmulh integer multiply variants that return the high half of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*. |
norm:Zve64_eew64_nsupport_vmulh |
| Zve64_eew64_nsupport_vsmul | All Zve* extensions support all vector fixed-point arithmetic instructions (sec-vector-fixed-point), except that vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*. |
norm:Zve64_eew64_nsupport_vsmul |
| Zve32x_Zve64x_nsupport_freg | All Zve* extensions support all vector permutation instructions (sec-vector-permute), except that Zve32x and Zve64x do not include those with floating-point operands, and Zve64f does not include those with EEW=64 floating-point operands. |
norm:Zve32x_Zve64x_nsupport_freg |
| Zve32x_dependent_Zicsr | The Zve32x extension depends on the Zicsr extension. | norm:Zve32x_dependent_Zicsr |
| Zve32f_dependent_F | The Zve32f and Zve64f extensions depend upon the F extension, and implement all vector floating-point instructions (sec-vector-float) for floating-point operands with EEW=32. Vector single-width floating-point reduction operations (sec-vector-float-reduce) for EEW=32 are supported. |
norm:Zve32f_Zve64f_dependent_F |
| Zve64f_dependent_F | The Zve32f and Zve64f extensions depend upon the F extension, and implement all vector floating-point instructions (sec-vector-float) for floating-point operands with EEW=32. Vector single-width floating-point reduction operations (sec-vector-float-reduce) for EEW=32 are supported. |
norm:Zve32f_Zve64f_dependent_F |
| misa_v_op | The misa.v bit is set for implementations providing misa and supporting V. |
norm:misa_v_op |
| V_precise_traps | The V vector extension has precise traps. | norm:V_precise_traps |
| V_dependent_Zvl128b_Zve64d | The V vector extension depends upon the Zvl128b and Zve64d extensions. | norm:V_dependent_Zvl128b_Zve64d |
| V_supported_eew | The V extension supports EEW of 8, 16, and 32, and 64. | norm:V_supported_eew |
| V_instr | The V extension supports the vector configuration instructions (sec-vector-config). |
norm:V_instr_config |
| The V extension supports all vector load and store instructions (sec-vector-memory), except the V extension does not support EEW=64 for index values when XLEN=32. |
norm:V_instr_ls_eew64_nsupported_xlen32 | |
| The V extension supports all vector integer instructions (sec-vector-integer). |
norm:V_instr_int | |
| The V extension supports all vector fixed-point arithmetic instructions (sec-vector-fixed-point). |
norm:V_instr_fixedpt | |
| The V extension supports all vector integer single-width and widening reduction operations (sec-vector-integer-reduce, sec-vector-integer-reduce-widen). |
norm:V_instr_red | |
| The V extension supports all vector mask instructions (sec-vector-mask). |
norm:V_instr_mask | |
| The V extension supports all vector permutation instructions (sec-vector-permute). |
norm:V_instr_perm | |
| V_dependent_F_D | The V extension depends upon the F and D extensions, and implements all vector floating-point instructions (sec-vector-float) for floating-point operands with EEW=32 or EEW=64 (including widening instructions and conversions between FP32 and FP64). Vector single-width floating-point reductions (sec-vector-float-reduce) for EEW=32 and EEW=64 are supported as well as widening reductions from FP32 to FP64. |
norm:V_dependent_F_D |
| Zvfhmin_dependent_Zve32f | The Zvfhmin extension depends on the Zve32f extension. | norm:Zvfhmin_dependent_Zve32f |
| Zvfh_instr | When the Zvfh extension is implemented, all instructions in sec-vector-float, sec-vector-float-reduce, sec-vector-float-reduce-widen, sec-vector-float-move, sec-vfslide1up, and sec-vfslide1down become defined when SEW=16. |
norm:Zvfh_instr |
| Additionally, conversions between 8-bit integers and binary16 values are provided. The floating-point-to-integer narrowing conversions (vfncvt[.rtz].x[u].f.w) and integer-to-floating-point widening conversions (vfwcvt.f.x[u].v) become defined when SEW=8. |
norm:Zvfh_instr_cvt | |
| Zvfh_eew16 | The EEW=16 floating-point operands of these instructions use the binary16 format. |
norm:Zvfh_eew16 |
| Zvfh_dependent_Zve32f_Zfhmin | The Zvfh extension depends on the Zve32f and Zfhmin extensions. | norm:Zvfh_dependent_Zve32f_Zfhmin |
| egs_ge_vlmax_rsv | Vector instructions with EGS > VLMAX are reserved. | norm:egs_ge_vlmax_rsv |
| egs_vl_rsv | When an operand is a vector of element groups, the vl setting must correspond to an integer multiple of the element group size, with other values of vl reserved. |
norm:egs_vl_rsv |
| egs_vl_avl | When element group instructions are present, an additional constraint is placed on the setting of vl based on an AVL value (augmenting constraints-on-setting-vl). EGSMAX is the largest EGS supported by the implementation. When AVL > VLMAX, the value of vl must be set to either VLMAX or a positive integer multiple of EGSMAX. |
norm:egs_vl_avl |
| egs_sew_eew | The vtype SEW can be used to indicate or calculate the effective element size (EEW) of one or more operands of an element group instruction. Where the operand is an element group, SEW and EEW refer to the number of bits in each individual element within a group not the number of bits in the group as a whole. |
norm:egs_sew_eew |
| egs_lmul_emul | The vtype LMUL setting can be used to indicate or calculate the effective length multiplier (EMUL) for one or more operands. Element group instructions tend to exhibit a much wider range of relationships between various operand EEW/EMUL values. For example, an instruction might take a vector of length N of 4-element groups with EEW=8b and reduce each group to produce a vector length N of 1-element groups with EEW=32b. In this case, the input and output EMUL values are equal even though the EEW settings differ by a factor of 4. |
norm:egs_lmul_emul |
| egs_egw | The element group width (EGW) is the number of bits in the element group as a whole. For example, the SHA-256 instructions in the Zvknha extension operate on an EGW of 128, with EGS=4 and EEW=32. It is possible to use LMUL to concatenate multiple vector registers together to support larger EGW>VLEN. |
norm:egs_egw |
| vector_active_element | The active elements can raise exceptions and update the destination vector register group. | norm:vector_active_element |
| vector_ls_rvtso | If the Ztso extension is implemented, vector memory instructions additionally follow RVTSO at the instruction level. | norm:vector_ls_rvtso |
| vnclipu_vnclip_rounding | For vnclipu/vnclip, the rounding mode is specified in the vxrm CSR. Rounding occurs around the least-significant bit of the destination and before saturation. |
norm:vnclipu_vnclip_rounding |
| Vf_requrires_Vx | Vector floating-point instructions require the presence of base scalar floating-point extensions corresponding to the supported vector floating-point element widths. |
norm:Vf_requrires_Vx |
| instrgrp_vmask_disregard_vlmul | so these instructions all operate on single vector registers regardless of the setting of the vlmul field in vtype. They do not change the value of vlmul. |
norm:instrgrp_vmask_disregard_vlmul |
| viota_restart | execution is always restarted from the beginning when resuming after a trap handler. |
norm:viota_restart |
| vrgather-vv_op_vrgatherei16-vv_op | vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; |
norm:vrgather-vv_op_vrgatherei16-vv_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| veccrypto_eeweqsew | For all of the vector crypto instructions in this specification, EEW=SEW. | norm:veccrypto_eeweqsew |
| veccrypto_vl_egsconstr | Since vl and vstart refer to elements, Vector Crypto instructions that use elements groups (See crypto-vector-element-groups) require that these values are an integer multiple of the Element Group Size (EGS). |
norm:veccrypto_vl_vstart_egsconstr |
| veccrypto_vstart_egsconstr | Since vl and vstart refer to elements, Vector Crypto instructions that use elements groups (See crypto-vector-element-groups) require that these values are an integer multiple of the Element Group Size (EGS). |
norm:veccrypto_vl_vstart_egsconstr |
| veccrypto_vl_rsv | Instructions that violate the vl or vstart requirements are reserved. | norm:veccrypto_vl_vstart_rsv |
| veccrypto_vstart_rsv | Instructions that violate the vl or vstart requirements are reserved. | norm:veccrypto_vl_vstart_rsv |
| veccrypto_lmul_egwconstr | For element-group instructions, LMUL*VLEN must always be at least as large as EGW, otherwise an illegal-instruction exception is raised, even if vl=0. |
norm:veccrypto_lmul_egwconstr |
| veccrypto_sew_rsv | Some Vector Crypto instructions are only defined for a specific SEW. In such a case all other SEW values are reserved. |
norm:veccrypto_sew_rsv |
| veccrypto_vsins_vs2 | In the case of the .vs instructions defined in this specification, vs2 holds a 128-bit scalar element group. | norm:veccrypto_vsins_vs2 |
| These instructions enable a single key, specified as a scalar element group in vs2, to be applied to each element group of register group vd. |
norm:veccrypto_vsins_vs2function | |
| veccrypto_vsins_vdvs2overlap | For implementations with VLEN ≥ 128, vs2 refers to a single register. Thus, the vd register group must not overlap the vs2 register. However, in implementations where VLEN < 128, vs2 refers to a register group comprised of the number of registers needed to hold the 128-bit scalar element group. In this case, the vd register group must not overlap this vs2 register group. |
norm:veccrypto_vsins_vdvs2overlap |
| veccrypto_vsins_vd | they return vector results to vd, which is also a source vector operand. | norm:veccrypto_vsins_vd |
| Zvknhb_depZve64x | The Zvknhb and zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- depend on Zve64x. |
norm:Zvknhb_Zvbc_Zvkn_Zvknc_Zvkng_depZve64x |
| Zvbc_depZve64x | The Zvknhb and zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- depend on Zve64x. |
norm:Zvknhb_Zvbc_Zvkn_Zvknc_Zvkng_depZve64x |
| Zvkn_depZve64x | The Zvknhb and zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- depend on Zve64x. |
norm:Zvknhb_Zvbc_Zvkn_Zvknc_Zvkng_depZve64x |
| Zvknc_depZve64x | The Zvknhb and zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- depend on Zve64x. |
norm:Zvknhb_Zvbc_Zvkn_Zvknc_Zvkng_depZve64x |
| Zvkng_depZve64x | The Zvknhb and zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn, Zvknc, Zvkng, and Zvksc-- depend on Zve64x. |
norm:Zvknhb_Zvbc_Zvkn_Zvknc_Zvkng_depZve64x |
| Zvbb_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvkb_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvkg_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvkned_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvknha_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvksed_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvksh_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvks_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvksc_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvksg_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvkt_depZve32x | All of the other Vector Crypto Extensions depend on Zve32x. | norm:Zvbb_Zvkb_Zvkg_Zvkned_Zvknha_Zvksed_Zvksh_Zvks_Zvksc_Zvksg_Zvkt_depZve32x |
| Zvknhb_impZvknha | Zvknhb implies Zvknha. | norm:Zvknhb_impZvknha |
| veccrypto_indepZkt | It is important to note that the Vector Crypto instructions are independent of the implementation of the Zkt extension and do not require that Zkt is implemented. |
norm:veccrypto_indepZkt |
| Zvbc_sew64only | These instructions are only defined for SEW=64. | norm:Zvbc_sew64only |
| Zvkg_egw128b_elem32b | All of these instructions work on 128-bit element groups comprised of four 32-bit elements. | norm:Zvkg_egw128b_elem32b |
| Zvkg_dataindeptiming | To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. | norm:Zvkg_dataindeptiming |
| Zvkg_vl | The number of element groups to be processed is vl/EGS. vl must be set to the number of SEW=32 elements to be processed and therefore must be a multiple of EGS=4. |
norm:Zvkg_vl |
| Zvkg_vstart | Likewise, vstart must be a multiple of EGS=4. | norm:Zvkg_vstart |
| Zvkned_egw128b_elem32b | All of these instructions work on 128-bit element groups comprised of four 32-bit elements. |
norm:Zvkned_egw128b_elem32b |
| Zvkned_dataindeptiming | To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. | norm:Zvkned_dataindeptiming |
| Zvkned_vl | The number of element groups to be processed is vl/EGS. vl must be set to the number of SEW=32 elements to be processed and therefore must be a multiple of EGS=4. |
norm:Zvkned_vl |
| Zvkned_vstart | Likewise, vstart must be a multiple of EGS=4. | norm:Zvkned_vstart |
| Zvknha_sha256_egw128b_elem32b | SHA-256: these instructions work on 128-bit element groups comprised of four 32-bit elements. | norm:Zvknha_Zvknhb_sha256_egw128b_elem32b |
| Zvknhb_sha256_egw128b_elem32b | SHA-256: these instructions work on 128-bit element groups comprised of four 32-bit elements. | norm:Zvknha_Zvknhb_sha256_egw128b_elem32b |
| Zvknhb_sha512_egw256b_elem64b | SHA-512: these instructions work on 256-bit element groups comprised of four 64-bit elements. | norm:Zvknhb_sha512_egw256b_elem64b |
| Zvknhb_sha256_sha512 | Zvknhb supports SHA-256 and SHA-512. | norm:Zvknhb_sha256_sha512 |
| Zvknha_sha256 | Zvknha supports only SHA-256. | norm:Zvknha_sha256 |
| Zvknha_dataindeptiming | To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. | norm:Zvknha_Zvknhb_dataindeptiming |
| Zvknhb_dataindeptiming | To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. | norm:Zvknha_Zvknhb_dataindeptiming |
| Zvknha_vl | The number of element groups to be processed is vl/EGS. vl must be set to the number of SEW elements to be processed and therefore must be a multiple of EGS=4. |
norm:Zvknha_Zvknhb_vl |
| Zvknhb_vl | The number of element groups to be processed is vl/EGS. vl must be set to the number of SEW elements to be processed and therefore must be a multiple of EGS=4. |
norm:Zvknha_Zvknhb_vl |
| Zvknha_vstart | Likewise, vstart must be a multiple of EGS=4. | norm:Zvknha_Zvknhb_vstart |
| Zvknhb_vstart | Likewise, vstart must be a multiple of EGS=4. | norm:Zvknha_Zvknhb_vstart |
| Zvksed_egw128b_elem32b | All of these instructions work on 128-bit element groups comprised of four 32-bit elements. |
norm:Zvksed_egw128b_elem32b |
| Zvksed_dataindeptiming | To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. | norm:Zvksed_dataindeptiming |
| Zvksed_vl | The number of element groups to be processed is vl/EGS. vl must be set to the number of SEW=32 elements to be processed and therefore must be a multiple of EGS=4. |
norm:Zvksed_vl |
| Zvksed_vstart | Likewise, vstart must be a multiple of EGS=4. | norm:Zvksed_vstart |
| Zvksh_egw256b_elem32b | All of these instructions work on 256-bit element groups comprised of eight 32-bit elements. |
norm:Zvksh_egw256b_elem32b |
| Zvksh_dataindeptiming | To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing. | norm:Zvksh_dataindeptiming |
| Zvksh_vl | The number of element groups to be processed is vl/EGS. vl must be set to the number of SEW=32 elements to be processed and therefore must be a multiple of EGS=8. |
norm:Zvksh_vl |
| Zvksh_vstart | Likewise, vstart must be a multiple of EGS=8. | norm:Zvksh_vstart |
| vandn_op | Each bit of Op1 is inverted and logically ANDed with the corresponding bits in vs2. | norm:vandn_op |
| vandn-vx_rs1 | In the vector-scalar version, Op1 is the sign-extended or truncated value in scalar register rs1. |
norm:vandn-vx_rs1 |
| vandn-vv_vs1 | In the vector-vector version, Op1 is vs1. | norm:vandn-vv_vs1 |
| vbrev-v_op | A bit reversal is performed on the bits of each element. | norm:vbrev-v_op |
| vbrev8-v_op | A bit reversal is performed on the bits of each byte. | norm:vbrev8-v_op |
| vclmul_op | Each 64-bit element in the vs2 vector register is carry-less multiplied by either each 64-bit element in vs1 (vector-vector), or the 64-bit value from integer register rs1 (vector-scalar). The result is the least significant 64 bits of the carry-less product. |
norm:vclmul_op |
| vclmul_sewn64_rsv | SEW is any value other than 64 | norm:vclmul_sewn64_rsv |
| vclmulh_op | Each 64-bit element in the vs2 vector register is carry-less multiplied by either each 64-bit element in vs1 (vector-vector), or the 64-bit value from integer register rs1 (vector-scalar). The result is the most significant 64 bits of the carry-less product. |
norm:vclmulh_op |
| vclmulh_sewn64_rsv | SEW is any value other than 64 | norm:vclmulh_sewn64_rsv |
| vclz-v_op | A leading zero count is performed on each element. | norm:vclz-v_op |
| The result for zero-valued inputs is the value SEW. | norm:vclz-v_op_zeroinput | |
| vcpop-v_op | A population count is performed on each element. | norm:vcpop-v_op |
| vctz-v_op | A trailing zero count is performed on each element. | norm:vctz-v_op |
| vghsh-vv_sewn32_rsv | SEW is any value other than 32 | norm:vghsh-vv_sewn32_rsv |
| vghsh-vv_op | This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2]. It produces the next partial hash (Yi+1) by adding the current partial hash (Yi) to the cipher text block (Xi) and then multiplying (over GF(2128)) this sum by the Hash Subkey (H). |
norm:vghsh-vv_op |
| The multiplication over GF(2128) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x128 + x7 + x2 + x + 1). |
norm:vghsh-vv_op_gf | |
| The NIST specification (see zvkg) orders the coefficients from left to right x0x1x2...x127 for a polynomial x0 + x1u +x2 u2 + ... + x127u127. This can be viewed as a collection of byte elements in memory with the byte containing the lowest coefficients (i.e., 0,1,2,3,4,5,6,7) residing at the lowest memory address. Since the bits in the bytes are reversed, this instruction internally performs bit swaps within bytes to put the bits in the standard ordering (e.g., 7,6,5,4,3,2,1,0). |
norm:vghsh-vv_op_coeff | |
| vghsh-vv_exeindepdata | This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. |
norm:vghsh-vv_exeindepdata |
| vgmul-vv_sewn32_rsv | SEW is any value other than 32 | norm:vgmul-vv_sewn32_rsv |
| vgmul-vv_op | This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2]. It produces the product over GF(2128) of the two 128-bit inputs. |
norm:vgmul-vv_op |
| The multiplication over GF(2128) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x128 + x7 + x2 + x + 1). |
norm:vgmul-vv_op_gf | |
| The NIST specification (see zvkg) orders the coefficients from left to right x0x1x2...x127 for a polynomial x0 + x1u +x2 u2 + ... + x127u127. This can be viewed as a collection of byte elements in memory with the byte containing the lowest coefficients (i.e., 0,1,2,3,4,5,6,7) residing at the lowest memory address. Since the bits in the bytes are reversed, This instruction internally performs bit swaps within bytes to put the bits in the standard ordering (e.g., 7,6,5,4,3,2,1,0). |
norm:vgmul-vv_op_coeff | |
| vgmul-vv_exeindepdata | This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. |
norm:vgmul-vv_exeindepdata |
| vrev8-v_op | A byte reversal is performed on each element of vs2, effectively performing an endian swap. | norm:vrev8-v_op |
| vrol_op | The elements in vs2 are rotated left by the rotate amount specified by either the corresponding elements of vs1 (vector-vector), or integer register rs1 (vector-scalar). Only the low log2(SEW) bits of the rotate-amount value are used, all other bits are ignored. |
norm:vrol_op |
| vror_op | The elements in vs2 are rotated right by the rotate amount specified by either the corresponding elements of vs1 (vector-vector), integer register rs1 (vector-scalar), or an immediate value (vector-immediate). Only the low log2(SEW) bits of the rotate-amount value are used, all other bits are ignored. |
norm:vror_op |
| vsha2ch-vv_Zvknha_sewn32_rsv | zvknha: SEW is any value other than 32 | norm:vsha2chl-vv_Zvknha_sewn32_rsv |
| vsha2cl-vv_Zvknha_sewn32_rsv | zvknha: SEW is any value other than 32 | norm:vsha2chl-vv_Zvknha_sewn32_rsv |
| vsha2ch-vv_Zvknhb_sewn32or64_rsv | zvknhb: SEW is any value other than 32 or 64 | norm:vsha2chl-vv_Zvknhb_sewn32or64_rsv |
| vsha2cl-vv_Zvknhb_sewn32or64_rsv | zvknhb: SEW is any value other than 32 or 64 | norm:vsha2chl-vv_Zvknhb_sewn32or64_rsv |
| vsha2ch-vv_vdoverlapvs1vs2_rsv | The vd register group overlaps with either vs1 or vs2 | norm:vsha2chl-vv_vdoverlapvs1vs2_rsv |
| vsha2cl-vv_vdoverlapvs1vs2_rsv | The vd register group overlaps with either vs1 or vs2 | norm:vsha2chl-vv_vdoverlapvs1vs2_rsv |
| vsha2ch-vv_op | Two words of vs1 are processed with the 8 words of current state held in vd and vs2 to perform two rounds of hash computation producing four words of the next state. |
norm:vsha2chl-vv_op |
| SEW=32: 2 rounds of SHA-256 compression are performed (zvknha and zvknhb) | norm:vsha2chl-vv_op_sew32 | |
| SEW=64: 2 rounds of SHA-512 compression are performed (zvknhb) | norm:vsha2chl-vv_op_sew64 | |
| vsha2cl-vv_op | Two words of vs1 are processed with the 8 words of current state held in vd and vs2 to perform two rounds of hash computation producing four words of the next state. |
norm:vsha2chl-vv_op |
| SEW=32: 2 rounds of SHA-256 compression are performed (zvknha and zvknhb) | norm:vsha2chl-vv_op_sew32 | |
| SEW=64: 2 rounds of SHA-512 compression are performed (zvknhb) | norm:vsha2chl-vv_op_sew64 | |
| vsha2ms-vv_Zvknha_sewn32_rsv | zvknha: SEW is any value other than 32 | norm:vsha2ms-vv_Zvknha_sewn32_rsv |
| vsha2ms-vv_Zvknhb_sewn32or64_rsv | zvknhb: SEW is any value other than 32 or 64 | norm:vsha2ms-vv_Zvknhb_sewn32or64_rsv |
| vsha2ms-vv_vdoverlapvs1vs2_rsv | The vd register group overlaps with either vs1 or vs2 | norm:vsha2ms-vv_vdoverlapvs1vs2_rsv |
| vsha2ms-vv_op | Eleven of the last 16 SEW-sized message-schedule words from vd (oldest), vs2, and vs1 (most recent) are processed to produce the next 4 message-schedule words. |
norm:vsha2ms-vv_op |
| SEW=32: Four rounds of SHA-256 message schedule expansion are performed (zvknha and zvknhb) | norm:vsha2ms-vv_op_sew32 | |
| SEW=64: Four rounds of SHA-512 message schedule expansion are performed (zvknhb) | norm:vsha2ms-vv_op_sew64 | |
| vsm3c-vi_sewn32_rsv | SEW is any value other than 32 | norm:vsm3c-vi_sewn32_rsv |
| vsm3c-vi_vdoverlapvs2_rsv | The vd register group overlaps with the vs2 register group | norm:vsm3c-vi_vdoverlapvs2_rsv |
| vsm3c-vi_op | Two rounds of SM3 compression are performed. | norm:vsm3c-vi_op |
| The current state of eight 32-bit words is read in as an element group from vd. Eight 32-bit message words are read in as an element group from vs2, although only four of them are used. All of the 32-bit input words are byte-swapped from big endian to little endian. These inputs are processed somewhat differently based on the round group (as specified in rnds), and the next state is generated as an element group of eight 32-bit words. The next state of eight 32-bit words are generated, swapped from little endian to big endian, and are returned in an eight-element group. |
norm:vsm3c-vi_op_sm3 | |
| The round number is provided by the 5-bit rnds unsigned immediate. Legal values are 0 - 31 and indicate which group of two rounds are being performed. For example, if rnds=1, then rounds 2 and 3 are being performed. |
norm:vsm3c-vi_op_rnd | |
| vsm3me-vv_sewn32_rsv | SEW is any value other than 32 | norm:vsm3me-vv_sewn32_rsv |
| vsm3me-vv_vdoverlapvs2_rsv | The vd register group overlaps with the vs2 register group. | norm:vsm3me-vv_vdoverlapvs2_rsv |
| vsm3me-vv_op | Eight rounds of SM3 message expansion are performed. | norm:vsm3me-vv_op |
| The sixteen most recent 32-bit message words are read in as two eight-element groups from vs1 and vs2. Each of these words is swapped from big endian to little endian. The next eight 32-bit message words are generated, swapped from little endian to big endian, and are returned in an eight-element group. |
norm:vsm3me-vv_op_sm3 | |
| vsm4k-vi_sewn32_rsv | SEW is any value other than 32 | norm:vsm4k-vi_sewn32_rsv |
| vsm4k-vi_op | Four rounds of the SM4 Key Expansion are performed. | norm:vsm4k-vi_op |
| Four round keys are read in as a 4-element group from vs2. Each of the next four round keys are generated by iteratively XORing the last three round keys with a constant that is indexed by the Round Group Number, performing a byte-wise substitution, and then performing XORs between rotated versions of this value and the corresponding current round key. |
norm:vsm4k-vi_op_sm4k | |
| The Round group number (rnd) comes from uimm[2:0]; the bits in uimm[4:3] are ignored. Round group numbers range from 0 to 7 and indicate which group of four round keys are being generated. Round Keys range from 0-31. For example, if rnd=1, then round keys 4, 5, 6, and 7 are being generated. |
norm:vsm4k-vi_op_rnd | |
| vsm4r_sewn32_rsv | SEW is any value other than 32 | norm:vsm4r_sewn32_rsv |
| vsm4r-vs_vdoverlapvs2_rsv | Only for the .vs form: the vd register group overlaps the vs2 register | norm:vsm4r-vs_vdoverlapvs2_rsv |
| vsm4r_op | Four rounds of SM4 Encryption/Decryption are performed. | norm:vsm4r_op |
| The four words of current state are read as a 4-element group from vd and the round keys are read from either the corresponding 4-element group in vs2 (vector-vector form) or the scalar element group in vs2 (vector-scalar form). The next four words of state are generated by iteratively XORing the last three words of the state with the corresponding round key, performing a byte-wise substitution, and then performing XORs between rotated versions of this value and the corresponding current state. |
norm:vsm4r_op_sm4encdec | |
| vwsll_op | The elements in vs2 are zero-extended to 2*SEW bits, then shifted left by the shift amount specified by either the corresponding elements of vs1 (vector-vector), integer register rs1 (vector-scalar), or an immediate value (vector-immediate). Only the low log2(2*SEW) bits of the shift-amount value are used, all other bits are ignored. |
norm:vwsll_op |
| vaesdf_final | (No text available) | norm:vaesdf_final |
| vaesdf_ops | The InvShiftRows and InvSubBytes steps are applied to each round state element group from vd. | norm:vaesdf_ops |
| vaesdf_xor_form | This is then XORed with the round key in either the corresponding element group in vs2 (vector-vector form) or scalar element group in vs2 (vector-scalar form). |
norm:vaesdf_xor_form |
| vaesdm_mid | (No text available) | norm:vaesdm_mid |
| vaesdm_ops | The InvShiftRows and InvSubBytes steps are applied to each round state element group from vd. | norm:vaesdm_ops |
| vaesdm_xor_form | This is then XORed with the round key in either the corresponding element group in vs2 (vector-vector form) or the scalar element group in vs2 (vector-scalar form). |
norm:vaesdm_xor_form |
| vaesdm_invmix | InvMixColumns step. | norm:vaesdm_invmix |
| vaesef_final | (No text available) | norm:vaesef_final |
| vaesef_ops | The SubBytes and ShiftRows steps are applied to each round state element group from vd. | norm:vaesef_ops |
| vaesef_xor_form | This is then XORed with the round key in either the corresponding element group in vs2 (vector-vector form) or the scalar element group in vs2 (vector-scalar form). |
norm:vaesef_xor_form |
| vaesem_mid | (No text available) | norm:vaesem_mid |
| vaesem_ops | The SubBytes, ShiftRows, and MixColumns steps are applied to each round state element group from vd. | norm:vaesem_ops |
| vaesem_xor_form | This is then XORed with the round key in either the corresponding element group in vs2 (vector-vector form) or the scalar element group in vs2 (vector-scalar form). |
norm:vaesem_xor_form |
| vaeskf1_round | A single round of the forward AES-128 KeySchedule is performed. | norm:vaeskf1_round |
| vaeskf1_wordgen | The next round key is generated word by word from the current round key element group in vs2 and the immediately previous word of the round key. |
norm:vaeskf1_wordgen |
| vaeskf1_uimm_src | ranges from 1 to 10, comes from uimm[3:0]; uimm[4] is ignored. |
norm:vaeskf1_uimm_src |
| vaeskf1_uimm_map | The out-of-range uimm[3:0] values of 0 and 11-15 are mapped to in-range values by inverting uimm[3]. |
norm:vaeskf1_uimm_map |
| vaeskf2_round | A single round of the forward AES-256 KeySchedule is performed. | norm:vaeskf2_round |
| vaeskf2_wordgen | The next round key is generated word by word from the previous round key element group in vd and the immediately previous word of the round key. |
norm:vaeskf2_wordgen |
| vaeskf2_rcon_lsw | least significant word of the next round key is generated by applying a function to the most significant word of the current round key and then XORing the result with the round constant. |
norm:vaeskf2_rcon_lsw |
| vaeskf2_rcon_func | The round number is used to select the round constant as well as the function. | norm:vaeskf2_rcon_func |
| vaeskf2_uimm_src | ranges from 2 to 14, comes from uimm[3:0]; uimm[4] is ignored. |
norm:vaeskf2_uimm_src |
| vaeskf2_uimm_map | The out-of-range uimm[3:0] values of 0-1 and 15 are mapped to in-range values by inverting uimm[3]. |
norm:vaeskf2_uimm_map |
| vaesz_round0 | A round-0 AES block cipher operation is performed. | norm:vaesz_round0 |
| vaesz_vs_only | There is only a .vs form of the instruction. | norm:vaesz_vs_only |
| vaesz_vs2_rk | Vs2 holds a scalar element group that is used as the round key for all of the round state element groups. |
norm:vaesz_vs2_rk |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zacas_rv32_amocas-w_op | For RV32, AMOCAS.W atomically loads a 32-bit data value from address in rs1, compares the loaded value to the 32-bit value held in rd, and if the comparison is bitwise equal, then stores the 32-bit value held in rs2 to the original address in rs1. The value loaded from memory is placed into register rd. |
norm:Zacas_rv32_amocas-w_op |
| Zacas_rv32_amocas-d_op | For RV32, AMOCAS.D atomically loads 64-bits of a data value from address in rs1, compares the loaded value to a 64-bit value held in a register pair consisting of rd and rd+1, and if the comparison is bitwise equal, then stores the 64-bit value held in the register pair rs2 and rs2+1 to the original address in rs1. The value loaded from memory is placed into the register pair rd and rd+1. |
norm:Zacas_rv32_amocas-d_op |
| Zacas_rv32_amocas-d_frst_pair_entry_reg_even | The instruction requires the first register in the pair to be even numbered; encodings with odd numbered registers specified in rs2 and rd are reserved. |
norm:Zacas_rv32_amocas-d_frst_pair_entry_reg_even |
| Zacas_rv32_amocas-d_rs2_frst_reg_x0 | When the first register of a source register pair is x0, then both halves of the pair read as zero. |
norm:Zacas_rv32_amocas-d_rs2_frst_reg_x0 |
| Zacas_rv32_amocas-d_rd_frst_reg_x0 | When the first register of a destination register pair is x0, then the entire register result is discarded and neither destination register is written. |
norm:Zacas_rv32_amocas-d_rd_frst_reg_x0 |
| Zacas_rv64_amocas-w_op | For RV64, AMOCAS.W atomically loads a 32-bit data value from address in rs1, compares the loaded value to the lower 32 bits of the value held in rd, and if the comparison is bitwise equal, then stores the lower 32 bits of the value held in rs2 to the original address in rs1. The 32-bit value loaded from memory is sign-extended and is placed into register rd. |
norm:Zacas_rv64_amocas-w_op |
| Zacas_rv64_amocas-d_op | For RV64, AMOCAS.D atomically loads 64-bits of a data value from address in rs1, compares the loaded value to a 64-bit value held in rd, and if the comparison is bitwise equal, then stores the 64-bit value held in rs2 to the original address in rs1. The value loaded from memory is placed into register rd. |
norm:Zacas_rv64_amocas-d_op |
| Zacas_rv64_amocas-q_op | AMOCAS.Q (RV64 only) atomically loads 128-bits of a data value from address in rs1, compares the loaded value to a 128-bit value held in a register pair consisting of rd and rd+1, and if the comparison is bitwise equal, then stores the 128-bit value held in the register pair rs2 and rs2+1 to the original address in rs1. The value loaded from memory is placed into the register pair rd and rd+1. |
norm:Zacas_rv64_amocas-q_op |
| Zacas_rv64_amocas-q_frst_pair_entry_reg_even | The instruction requires the first register in the pair to be even numbered; encodings with odd numbered registers specified in rs2 and rd are reserved. |
norm:Zacas_rv64_amocas-q_frst_pair_entry_reg_even |
| Zacas_rv64_amocas-q_rs2_frst_reg_x0 | When the first register of a source register pair is x0, then both halves of the pair read as zero. |
norm:Zacas_rv64_amocas-q_rs2_frst_reg_x0 |
| Zacas_rv64_amocas-q_rd_frst_reg_x0 | When the first register of a destination register pair is x0, then the entire register result is discarded and neither destination register is written. |
norm:Zacas_rv64_amocas-q_rd_frst_reg_x0 |
| Zacas_amocas_rs1_addr_alignment | AMOCAS.W/D/Q requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., 16-byte aligned for quadwords, eight-byte aligned for doublewords, and four-byte aligned for words). |
norm:Zacas_amocas_rs1_addr_alignment |
| Zacas_amocas_mem_op_success_aq_rl | The memory operation performed by an AMOCAS.W/D/Q, when successful, has acquire semantics if aq bit is 1 and has release semantics if rl bit is 1. |
norm:Zacas_amocas_mem_op_success_aq_rl |
| Zacas_amocas_mem_op_fail_aq_rl | The memory operation performed by an AMOCAS.W/D/Q, when not successful, has acquire semantics if aq bit is 1 but does not have release semantics, regardless of rl. |
norm:Zacas_amocas_mem_op_fail_aq_rl |
| Zacas_amocas_w_permission | An AMOCAS.W/D/Q instruction always requires write permissions. | norm:Zacas_amocas_w_permission |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| zalasr_def | The Zalasr (Load-Acquire and Store-Release) extension provides load-acquire and store-release instructions in RISC-V. These can be important for high performance designs by enabling finer-grained synchronisation than is possible with fences alone, by providing a unidirectional fence. |
norm:zalasr_def |
| zalasr_builds_on_amo | The Zalasr extension builds on the atomic support provided by the Zaamo (Atomic Memory Operations), Zalrsc (Load-Reserved and Store-Conditional), and Zabha (Byte and Halfword Atomic Memory Operations) extensions by providing additional atomic operations (although it can be implemented independently of them). | norm:zalasr_builds_on_amo |
| zalasr_atomic_ordered | The Zalasr instructions are atomic loads and stores that support ordering annotations. | norm:zalasr_atomic_ordered |
| zalasr_signext_rd | The Zalasr instructions always sign-extend the value placed in rd | norm:zalasr_signext_rd |
| zalasr_ignore_rs2_upper | ignore the upper bits of the value of rs2. | norm:zalasr_ignore_rs2_upper |
| zalasr_natural_align | The instructions in the Zalasr extension require that the address held in rs1 be naturally aligned to the size in bytes (2width) of the operand. | norm:zalasr_natural_align |
| zalasr_misaligned_exception | If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated. | norm:zalasr_misaligned_exception |
| zalasr_misaligned_pma_relax | The misaligned atomicity granule PMA, defined in Volume II of this manual, optionally relaxes this alignment requirement. | norm:zalasr_misaligned_pma_relax |
| zalasr_misaligned_single_op | If all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO—i.e., it will execute atomically. | norm:zalasr_misaligned_single_op |
| ldaq_atomic_load_enc | Encoding | norm:ldaq_atomic_load_enc |
| ldaq_atomic_load_op | This instruction loads 2width bytes of memory from rs1 atomically and writes the result into rd. | norm:ldaq_atomic_load_op |
| ldaq_signext_rule | If the size (2width+3) is less than XLEN, it is sign-extended to fill the destination register. | norm:ldaq_signext_rule |
| ldaq_aq_required | This load must have the ordering annotation aq | norm:ldaq_aq_required |
| ldaq_rl_optional | may have ordering annotation rl encoded in the instruction. | norm:ldaq_rl_optional |
| ldaq_rcsc_semantics | The instruction always has an "acquire-RCsc" annotation, and if the bit rl is set the instruction has a "release-RCsc" annotation. | norm:ldaq_rcsc_semantics |
| ldaq_no_aq_reserved | The versions without the aq bit set are RESERVED. | norm:ldaq_no_aq_reserved |
| ldaq_rv64_only | LD.{AQ, AQRL} is RV64-only. | norm:ldaq_rv64_only |
| sdrl_atomic_store_enc | Encoding | norm:sdrl_atomic_store_enc |
| sdrl_atomic_store_op | This instruction stores 2width bytes of memory from rs1 atomically. | norm:sdrl_atomic_store_op |
| sdrl_rl_required | This store must have ordering annotation rl | norm:sdrl_rl_required |
| sdrl_aq_optional | may have ordering annotation aq encoded in the instruction. | norm:sdrl_aq_optional |
| sdrl_rcsc_semantics | The instruction always has an "release-RCsc" annotation, and if the bit aq is set the instruction has a "acquire-RCsc" annotation. | norm:sdrl_rcsc_semantics |
| sdrl_no_rl_reserved | The versions without the rl bit set are RESERVED. | norm:sdrl_no_rl_reserved |
| sdrl_rv64_only | SD.{RL, AQRL} is RV64-only. | norm:sdrl_rv64_only |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zawrs_wrs-nto_stall_exec | Then a subsequent WRS.NTO instruction would cause the hart to temporarily stall execution in a low-power state until a store occurs to the reservation set or an interrupt is observed. |
norm:Zawrs_wrs-nto_stall_exec |
| Zawrs_wrs-sto_stall_duration | WRS.STO (WRS-with-short-timeout) is provided that works like WRS.NTO but bounds the stall duration to an implementation-define short timeout such that the stall is terminated on the timeout if no other conditions have occurred to terminate the stall. |
norm:Zawrs_wrs-sto_stall_duration |
| Zawrs_stall_terminate | While stalled, an implementation is permitted to occasionally terminate the stall and complete execution for any reason. |
norm:Zawrs_stall_terminate |
| Zawrs_exec_resume_rules | WRS.NTO and WRS.STO instructions follow the rules of the WFI instruction for resuming execution on a pending interrupt. |
norm:Zawrs_exec_resume_rules |
| Zawrs_priv_illegal_instr_excp | When the TW (Timeout Wait) bit in mstatus is set and WRS.NTO is executed in any privilege mode other than M mode, and it does not complete within an implementation-specific bounded time limit, the WRS.NTO instruction will cause an illegal-instruction exception. |
norm:Zawrs_priv_illegal_instr_excp |
| Zawrs_virtual_instr_excp | When executing in VS or VU mode, if the VTW bit is set in hstatus, the TW bit in mstatus is clear, and the WRS.NTO does not complete within an implementation-specific bounded time limit, the WRS.NTO instruction will cause a virtual-instruction exception. |
norm:Zawrs_virtual_instr_excp |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| misa_c_set | MISA.C is set if the following extensions are selected: | norm:misa_c_set_line |
| Zca and not F Zca, Zcf and F (but not D) is specified (RV32 only) Zca, Zcf and Zcd if D is specified (RV32 only) this configuration excludes Zcmp, Zcmt Zca, Zcd if D is specified (RV64 only) this configuration excludes Zcmp, Zcmt |
norm:misa_c_set_list | |
| c-lbu_op | loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended to XLEN bits and is written to rd'. | norm:c-lbu_op |
| c-lhu_op | loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended to XLEN bits and is written to rd'. | norm:c-lhu_op |
| c-lh_op | loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended to XLEN bits and is written to rd'. | norm:c-lh_op |
| c-sb_op | stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | norm:c-sb_op |
| c-sh_op | stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | norm:c-sh_op |
| c-zext-b_op | zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of the bits more significant than 7. |
norm:c-zext-b_op |
| c-sext-b_op | sign-extends the least-significant byte in the operand to XLEN bits by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. |
norm:c-sext-b_op |
| c-zext-h_op | zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of the bits more significant than 15. |
norm:c-zext-h_op |
| c-sext-h_op | sign-extends the least-significant halfword in the operand to XLEN bits by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. |
norm:c-sext-h_op |
| c-zext-w_op | zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31. |
norm:c-zext-w_op |
| c-not_op | takes the one's complement of rd'/rs1' and writes the result to the same register. | norm:c-not_op |
| c-mul_op | multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'. | norm:c-mul_op |
| Zcmp_trap | Correct execution requires that sp refers to idempotent memory (also see ), because the core must be able to handle traps detected during the sequence. The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence. | norm:Zcmp_reexecute |
| If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap. | norm:Zcmp_trap | |
| INTERRUPTS_ALLOWED_IN_PUSHPOP | extension | Rule's "kind" property |
| Zcmp | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| It is implementation defined whether interrupts can also be taken during the sequence execution. | norm:interrupts_allowed_in_pushpop | |
| Zcmp_bus_fault | Stores may also return imprecise faults from the bus. It is platform defined whether the core implementation waits for the bus responses before continuing to the final stage of the sequence, or handles errors responses after completing the PUSH instruction. | norm:Zcmp_bus_fault |
| Zcmp_push_sp_commit | The stack pointer adjustment must only be committed only when it is certain that the entire PUSH instruction will commit. | norm:Zcmp_push_sp_commit |
| Zcmp_pop_sp_commit | The optional li a0, 0, stack pointer adjustment and optional ret must only be committed only when it is certain that the entire POP/POPRET instruction will commit. | norm:Zcmp_pop_sp_commit |
| cm-push_op | pushes (stores) the registers in reg_list to the memory below the stack pointer, and then creates the stack frame by decrementing the stack pointer by stack_adj, including any additional stack space requested by the value of spimm. |
norm:cm-push_op |
| cm-pop_op | This instruction pops (loads) the registers in reg_list from stack memory, and then adjusts the stack pointer by stack_adj. |
norm:cm-pop_op |
| cm-popretz_op | pops (loads) the registers in reg_list from stack memory, adjusts the stack pointer by stack_adj, moves zero into a0 and then returns to ra. | norm:cm-popretz_op |
| cm-popret_op | pops (loads) the registers in reg_list from stack memory, adjusts the stack pointer by stack_adj and then returns to ra. | norm:cm-popret_op |
| cm-mvsa01_res | For the encoding to be legal r1s' != r2s'. | norm:cm-mvsa01_res |
| cm-mvsa01_op | moves a0 into r1s' and a1 into r2s'. r1s' and r2s' must be different. | norm:cm-mvsa01_op |
| cm-mvsa01_sreg | The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space. | norm:cm-mvsa01_sreg |
| cm-mva01s_op | moves r1s' into a0 and r2s' into a1. | norm:cm-mva01s_op |
| cm-mva01s_sreg | The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space. | norm:cm-mva01s_sreg |
| Zcmt_table | Table jump uses a 256-entry XLEN wide table in instruction memory to contain function addresses. The table must be a minimum of 64-byte aligned. |
norm:Zcmt_table |
| Zcmt_endian | Table entries follow the current data endianness. This is different from normal instruction fetch which is always little-endian. | norm:Zcmt_endian |
| Zcmt_entry_sz | The base of the table is in the jvt CSR (see csrs-jvt), each table entry is XLEN bits. | norm:Zcmt_entry_sz |
| Zcmt_fetch | For a table jump instruction, the table entry that the instruction selects is considered an extension of the instruction itself. Hence, the execution of a table jump instruction involves two instruction fetches, the first to read the instruction (cm.jt/cm.jalt) and the second to read from the jump vector table (JVT). Both instruction fetches are implicit reads, and both require execute permission; read permission is irrelevant. It is recommended that the second fetch be ignored for hardware triggers and breakpoints. |
norm:Zcmt_fetch |
| Zcmt_trap | If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault. | norm:Zcmt_trap |
| jvt_reg | The jvt register is an XLEN-bit WARL read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE). | norm:jvt_reg |
| JVT_WARL | extension | Rule's "kind" property |
| Zcmt | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| The jvt register is an XLEN-bit WARL read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE). | norm:jvt_reg | |
| jvt_op | If Zcmt is implemented then jvt must also be implemented, but can contain a read-only value. If jvt is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary. Note that the CSR contains only bits XLEN-1 through 6 of the address base. When computing jump-table accesses, the lower six bits of base are filled with zeroes to obtain an XLEN-bit jump-table base address jvt.base that is always aligned on a 64-byte boundary. |
norm:jvt_op |
| jvt_base_vm | jvt.base is a virtual address, whenever virtual memory is enabled. | norm:jvt_base_vm |
| jvt_mode_acc | jvt.mode is a WARL field, so can only be programmed to modes which are implemented. | norm:jvt_mode_acc |
| JVT_MODE_WARL | extension | Rule's "kind" property |
| Zcmt | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| jvt.mode is a WARL field, so can only be programmed to modes which are implemented. | norm:jvt_mode_acc | |
| cm-jt_op | cm.jt reads an entry from the jump vector table in memory and jumps to the address that was read. | norm:cm-jt_op |
| cm-jalt_op | cm.jalt reads an entry from the jump vector table in memory and jumps to the address that was read, linking to ra. | norm:cm-jalt_op |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| fli-s_op | The FLI.S instruction loads one of 32 single-precision floating-point constants, encoded in the rs1 field, into floating-point register rd. The correspondence of rs1 field values and single-precision floating-point values is shown in . FLI.S is encoded like FMV.W.X, but with rs2=1. | norm:fli-s_op |
| fli-d_op | If the D extension is implemented, FLI.D performs the analogous operation, but loads a double-precision value into floating-point register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for double-precision than for single-precision. FLI.D is encoded like FLI.S, but with fmt=D. | norm:fli-d_op |
| fli-q_op | If the Q extension is implemented, FLI.Q performs the analogous operation, but loads a quad-precision value into floating-point register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for quad-precision. FLI.Q is encoded like FLI.S, but with fmt=Q. | norm:fli-q_op |
| fli-h_op | If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a half-precision floating-point value into register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for half-precision. Furthermore, since 216 is not representable in half-precision floating-point, entry 29 in the table instead loads positive infinity—i.e., it is redundant with entry 30. FLI.H is encoded like FLI.S, but with fmt=H. | norm:fli-h_op |
| fminm-s_op | The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN. | norm:fmaxm-s_fminm-s_op |
| fmaxm-s_op | The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN. | norm:fmaxm-s_fminm-s_op |
| fminm-d_op | If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on double-precision numbers. | norm:fmaxm-d_fminm-d_op |
| fmaxm-d_op | If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on double-precision numbers. | norm:fmaxm-d_fminm-d_op |
| fminm-q_op | If the Q extension is implemented, FMINM.Q and FMAXM.Q instructions are analogously defined to operate on quad-precision numbers. | norm:fmaxm-q_fminm-q_op |
| fmaxm-q_op | If the Q extension is implemented, FMINM.Q and FMAXM.Q instructions are analogously defined to operate on quad-precision numbers. | norm:fmaxm-q_fminm-q_op |
| fminm-h_op | If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers. | norm:fmaxm-h_fminm-h_op |
| fmaxm-h_op | If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers. | norm:fmaxm-h_fminm-h_op |
| fround-s_op | The FROUND.S instruction rounds the single-precision floating-point number in floating-point register rs1 to an integer, according to the rounding mode specified in the instruction's rm field. It then writes that integer, represented as a single-precision floating-point number, to floating-point register rd |
norm:fround-s_op |
| froundnx-s_op | The FROUNDNX.S instruction is defined similarly, but it also sets the inexact exception flag if the input differs from the rounded result and is not NaN. FROUNDNX.S is encoded like FCVT.S.D, but with rs2=5. | norm:froundnx-s_op |
| fround-d | If the D extension is implemented, FROUND.D and FROUNDNX.D instructions are analogously defined to operate on double-precision numbers. They are encoded like FCVT.D.S, but with rs2=4 and 5, respectively, | norm:fround-d_froundnx-d_op |
| froundnx-d | If the D extension is implemented, FROUND.D and FROUNDNX.D instructions are analogously defined to operate on double-precision numbers. They are encoded like FCVT.D.S, but with rs2=4 and 5, respectively, | norm:fround-d_froundnx-d_op |
| fround-q | If the Q extension is implemented, FROUND.Q and FROUNDNX.Q instructions are analogously defined to operate on quad-precision numbers. They are encoded like FCVT.Q.S, but with rs2=4 and 5, respectively, | norm:fround-q_froundnx-q_op |
| froundnx-q | If the Q extension is implemented, FROUND.Q and FROUNDNX.Q instructions are analogously defined to operate on quad-precision numbers. They are encoded like FCVT.Q.S, but with rs2=4 and 5, respectively, | norm:fround-q_froundnx-q_op |
| fround-h | If the Zfh extension is implemented, FROUND.H and FROUNDNX.H instructions are analogously defined to operate on half-precision numbers. They are encoded like FCVT.H.S, but with rs2=4 and 5, respectively, | norm:fround-h_froundnx-h_op |
| froundnx-h | If the Zfh extension is implemented, FROUND.H and FROUNDNX.H instructions are analogously defined to operate on half-precision numbers. They are encoded like FCVT.H.S, but with rs2=4 and 5, respectively, | norm:fround-h_froundnx-h_op |
| fcvtmod-w-d_op | The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction, with the following differences. FCVTMOD.W.D always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded two’s complement result, then sign-extended to XLEN bits and written to integer register rd. ±∞ and NaN are converted to zero. | norm:fcvtmod-w-d_op |
| fcvtmod-w-d_flags | Floating-point exception flags are raised the same as they would be for FCVT.W.D with the same input operand. | norm:fcvtmod-w-d_flags |
| fcvtmod-w-d_rsw | It is encoded like FCVT.W.D, but with the rs2 field set to 8 and the rm field set to 1 (RTZ). Other rm values are reserved. |
norm:fcvtmod-w-d_rsw |
| fmvh-x-d_op | For RV32 only, if the D extension is implemented, the FMVH.X.D instruction moves bits 63:32 of floating-point register rs1 into integer register rd. It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110001. | norm:fmvh-x-d_op |
| fmvp-d-x_op | For RV32 only, if the D extension is implemented, the FMVP.D.X instruction moves a double-precision number from a pair of integer registers into a floating-point register. Integer registers rs1 and rs2 supply bits 31:0 and 63:32, respectively; the result is written to floating-point register rd. FMVP.D.X is encoded in the OP-FP major opcode with funct3=0 and funct7=1011001. | norm:fmvp-d-x_op |
| fmvh-x-q_op | For RV64 only, if the Q extension is implemented, the FMVH.X.Q instruction moves bits 127:64 of floating-point register rs1 into integer register rd. It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110011. | norm:fmvh-x-q_op |
| fmvp-q-x_op | For RV64 only, if the Q extension is implemented, the FMVP.Q.X instruction moves a double-precision number from a pair of integer registers into a floating-point register. Integer registers rs1 and rs2 supply bits 63:0 and 127:64, respectively; the result is written to floating-point register rd. FMVP.Q.X is encoded in the OP-FP major opcode with funct3=0 and funct7=1011011. | norm:fmvp-q-x_op |
| fleq-s_op | The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set. | norm:fleq-s_fltq-s_op |
| fltq-s_op | The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set. | norm:fleq-s_fltq-s_op |
| fleq-d_op | If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers. | norm:fleq-d_fltq-d_op |
| fltq-d_op | If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers. | norm:fleq-d_fltq-d_op |
| fleq-q_op | If the Q extension is implemented, FLEQ.Q and FLTQ.Q instructions are analogously defined to operate on quad-precision numbers. | norm:fleq-q_fltq-q_op |
| fltq-q_op | If the Q extension is implemented, FLEQ.Q and FLTQ.Q instructions are analogously defined to operate on quad-precision numbers. | norm:fleq-q_fltq-q_op |
| fleq-h_op | If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers. | norm:fleq-h_fltq-h_op |
| fltq-h_op | If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers. | norm:fleq-h_fltq-h_op |
| fround-s_zero_inf | Zero and infinite inputs are copied to rd unmodified |
norm:fround-s_zero_inf |
| fround-s_nan_nv | Signaling NaN inputs cause the invalid operation exception flag to be set; no other exception flags are set |
norm:fround-s_nan_nv |
| Rule Name | Rule Description | Origin of Description | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| fsh_op | New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field. | norm:fsh_flh_op | ||||||||||||||||||||||||||
| flh_op | New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field. | norm:fsh_flh_op | ||||||||||||||||||||||||||
| fsh_atomic_align | FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned. | norm:fsh_flh_atomic_align | ||||||||||||||||||||||||||
| flh_atomic_align | FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned. | norm:fsh_flh_atomic_align | ||||||||||||||||||||||||||
| fsh_bits_maintained | FLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2. | norm:fsh_flh_bits_maintained | ||||||||||||||||||||||||||
| flh_bits_maintained | FLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2. | norm:fsh_flh_bits_maintained | ||||||||||||||||||||||||||
| fadd-h_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmul-h_op | FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 |
norm:fadd-s_fmul-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsub-h_op | FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 |
norm:fsub-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fdiv-h_op | FDIV.S performs the single-precision floating-point division of rs1 by rs2 | norm:fdiv-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fsqrt-h_op | FSQRT.S computes the square root of rs1 | norm:fsqrt-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmadd-h_op | FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. | norm:fmadd-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fmsub-h_op | FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. | norm:fmsub-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmsub-h_op | FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. | norm:fnmsub-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fnmadd-h_op | FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. | norm:fnmadd-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. | norm:Zfh_computational_instrs | |||||||||||||||||||||||||||
| Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. | norm:FP_nontransfer_instrs_improper_nan-boxed_input | |||||||||||||||||||||||||||
| The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. | norm:fma_nv_flag | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-w-h_op | FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively |
norm:fcvt-w-h_fcvt-l-h_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-l-h_op | FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively |
norm:fcvt-w-h_fcvt-l-h_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. |
norm:fcvt_long_half_rv64_only | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-h-w_op | FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number |
norm:fcvt-h-w_fcvt-h-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-h-l_op | FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number |
norm:fcvt-h-w_fcvt-h-l_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. |
norm:fcvt_long_half_rv64_only | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-wu-h_op | FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-h_fcvt-lu-h_fcvt-h-wu_fcvt-h-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-lu-h_op | FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-h_fcvt-lu-h_fcvt-h-wu_fcvt-h-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. |
norm:fcvt_long_half_rv64_only | |||||||||||||||||||||||||||
| int_conv gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs |
norm:fcvt_int_float_valid_input | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-h-wu_op | FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-h_fcvt-lu-h_fcvt-h-wu_fcvt-h-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-h-lu_op | FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values |
norm:fcvt-wu-h_fcvt-lu-h_fcvt-h-wu_fcvt-h-lu_op | ||||||||||||||||||||||||||
| All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. | norm:fcvt_round | |||||||||||||||||||||||||||
| FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. |
norm:fcvt_long_half_rv64_only | |||||||||||||||||||||||||||
| All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. | norm:fcvt_nx | |||||||||||||||||||||||||||
| If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set |
norm:fcvt_unrepresentable_nv | |||||||||||||||||||||||||||
| Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. | norm:ieee_std_subnormal | |||||||||||||||||||||||||||
| In the parlance of the IEEE standard, tininess is detected after rounding. | norm:ieee_std_tininess | |||||||||||||||||||||||||||
|
norm:dyn_round_enc | |||||||||||||||||||||||||||
| Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in norm:dyn_round_enc. A value of 111 in the instruction's rm field selects the dynamic rounding mode held in frm |
norm:roundingmode_dynamic | |||||||||||||||||||||||||||
| fcvt-s-h_op | FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively |
norm:fcvt-s-h_fcvt-h-s_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-h-s_op | FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively |
norm:fcvt-s-h_fcvt-h-s_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-d-h_op | If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively |
norm:fcvt-d-h_fcvt-h-d_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-h-d_op | If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively |
norm:fcvt-d-h_fcvt-h-d_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-q-h_op | If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively |
norm:fcvt-q-h_fcvt-h-q_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fcvt-h-q_op | If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively |
norm:fcvt-q-h_fcvt-h-q_op | ||||||||||||||||||||||||||
| FCVT.S.D rounds according to the RM field; FCVT.D.S will never round |
norm:fcvt_float_rounding | |||||||||||||||||||||||||||
| fsgnj-h_op | Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-h_fsgnjn-h_fsgnjx-h_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-d_fsgnjn-d_fsgnjx-d_op | |||||||||||||||||||||||||||
| fsgnjn-h_op | Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-h_fsgnjn-h_fsgnjx-h_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-d_fsgnjn-d_fsgnjx-d_op | |||||||||||||||||||||||||||
| fsgnjx-h_op | Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-h_fsgnjn-h_fsgnjx-h_op | ||||||||||||||||||||||||||
| Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. | norm:fsgnj-d_fsgnjn-d_fsgnjx-d_op | |||||||||||||||||||||||||||
| fmv-x-h_op | FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd |
norm:fmv-x-d_op | ||||||||||||||||||||||||||
| FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number's sign bit |
norm:fmv-x-h_op | |||||||||||||||||||||||||||
| fmv-h-x_op | FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd |
norm:fmv-d-x_op | ||||||||||||||||||||||||||
| FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result. | norm:fmv-h-x_op | |||||||||||||||||||||||||||
| fmv-x-h_op_bits_preserved | FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fmv_bits_preserved | ||||||||||||||||||||||||||
| fmv-h-x_op_bits_preserved | FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fmv_bits_preserved | ||||||||||||||||||||||||||
| feq-h_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands. | norm:Zfh_compare_instrs | |||||||||||||||||||||||||||
| flt-h_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands. | norm:Zfh_compare_instrs | |||||||||||||||||||||||||||
| fle-h_op | Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. | norm:feq-s_flt-s_fle-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands. | norm:Zfh_compare_instrs | |||||||||||||||||||||||||||
| feq-h_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN |
norm:feq-s_quiet | |||||||||||||||||||||||||||
| The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands. | norm:Zfh_compare_instrs | |||||||||||||||||||||||||||
| flt-h_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands. | norm:Zfh_compare_instrs | |||||||||||||||||||||||||||
| fle-h_NaN | For all three instructions, the result is 0 if either operand is NaN | norm:feq-s_flt-s_fle-s_NaN_input | ||||||||||||||||||||||||||
| FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN |
norm:flt-s_fle-s_signaling | |||||||||||||||||||||||||||
| The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands. | norm:Zfh_compare_instrs | |||||||||||||||||||||||||||
| fclass-h_op | The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags. | norm:fclass-s_op | ||||||||||||||||||||||||||
| The half-precision floating-point classify instruction, FCLASS.H, is defined analogously to its single-precision counterpart, but operates on half-precision operands. | norm:fclass-h_op | |||||||||||||||||||||||||||
| zfhmin_instrs | The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included. If the Q extension is present, the FCVT.Q.H and FCVT.H.Q instructions are additionally included. | norm:zfhmin | ||||||||||||||||||||||||||
| fmv_half_bits_preverved | FMV.X.H and FMV.H.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. | norm:fmv_half_bits_preverved |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zfinx_F_instrs | The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP]. | norm:Zfinx_F_instrs |
| Zfinx_x_regs | The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number. | norm:Zfinx_x_regs |
| Zfinx_narrow_operands | Floating-point operands of width w < XLEN bits occupy bits w-1:0 of an x register. Floating-point operations on w-bit operands ignore operand bits XLEN-1: w. | norm:Zfinx_narrow_operands |
| Zfinx_narrow_result | Floating-point operations that produce w < XLEN-bit results fill bits XLEN-1: w with copies of bit w-1 (the sign bit). | norm:Zfinx_narrow_result |
| Zdinx_D_instrs | The Zdinx extension adds all of the instructions that the D extension adds, except for the transfer instructions FLD, FSD, FMV.D.X, FMV.X.D, C.FLD[SP], and C.FSD[SP]. | norm:Zdinx_D_instrs |
| Zdinx_x_regs | The Zdinx variants of these D-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number. | norm:Zdinx_x_regs |
| Zdinx_x_reg_pair | Double-precision operands in RV32Zdinx are held in aligned x-register pairs, i.e., register numbers must be even. Use of misaligned (odd-numbered) registers for double-width floating-point operands is reserved. | norm:Zdinx_x_reg_pair |
| Zdinx_endianness | Regardless of endianness, the lower-numbered register holds the low-order bits, and the higher-numbered register holds the high-order bits: e.g., bits 31:0 of a double-precision operand in RV32Zdinx might be held in register x14, with bits 63:32 of that operand held in x15. | norm:Zdinx_endianness |
| Zdinx_x0_write | When a double-width floating-point result is written to x0, the entire write takes no effect: e.g., for RV32Zdinx, writing a double-precision result to x0 does not cause x1 to be written. | norm:Zdinx_x0_write |
| Zdinx_x0_read | When x0 is used as a double-width floating-point operand, the entire operand is zero—i.e., x1 is not accessed. | norm:Zdinx_x0_read |
| Zhinx_Zfh_instrs | The Zhinx extension adds all of the instructions that the Zfh extension adds, except for the transfer instructions FLH, FSH, FMV.H.X, and FMV.X.H. | norm:Zhinx_Zfh_instrs |
| Zhinx_x_regs | The Zhinx variants of these Zfh-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number. | norm:Zhinx_x_regs |
| Zfhinxmin_instrs | The Zhinxmin extension includes the following instructions from the Zhinx extension: FCVT.S.H and FCVT.H.S. If the Zdinx extension is present, the FCVT.D.H and FCVT.H.D instructions are also included. | norm:Zfhinxmin_instrs |
| Zfinx_mstatus_FS_zero | In the standard privileged architecture defined in Volume II, the mstatus field FS is hardwired to 0 if the Zfinx extension is implemented, and FS no longer affects the trapping behavior of floating-point instructions or fcsr accesses. | norm:Zfinx_mstatus_FS_zero |
| Zfinx_misa_F_D_Q_zero | The misa bits F, D, and Q are hardwired to 0 when the Zfinx extension is implemented. | norm:Zfinx_misa_F_D_Q_zero |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| czero-eqz_op | If rs2 contains the value zero, this instruction writes the value zero to rd. Otherwise, this instruction copies the contents of rs1 to rd. | norm:czero-eqz_op |
| czero-eqz_inst_ctime | Untestable since timing behavior is a microarchitectural property | Rule's "summary" property |
| Furthermore, if the Zkt extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2. | norm:czero-eqz_inst_ctime | |
| czero-nez_op | If rs2 contains a nonzero value, this instruction writes the value zero to rd. Otherwise, this instruction copies the contents of rs1 to rd. | norm:czero-nez_op |
| czero-nez_zkt_timing | Untestable since timing behavior is a microarchitectural property | Rule's "summary" property |
| Furthermore, if the Zkt extension is implemented, this instruction’s timing is independent of the data values in rs1 and rs2. | norm:czero-nez_zkt_timing |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zicsr_higher_priv | although CSRs and instructions are associated with one privilege level, they are also accessible at all higher privilege levels. |
norm:Zicsr_higher_priv |
| Zicsr_rw | The top two bits (csr[11:10]) indicate whether the register is read/write (00,01, or 10) or read-only (11). | norm:Zicsr_rw |
| Zicsr_access | The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR, with the pattern 10 representing hypervisor CSRs. | norm:Zicsr_access |
| Zicsr_illegal_mode | Attempts to access a CSR without appropriate privilege level raise illegal-instruction exceptions or, as described in sec:hcauses, virtual-instruction exceptions. |
norm:Zicsr_illegal_mode |
| Zicsr_illegal_acc | Attempts to write a read-only register raise illegal-instruction exceptions. | norm:Zicsr_illegal_acc |
| Zicsr_write_ro | A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored. |
norm:Zicwr_write_ro |
| Zicsr_debug_illegal | 0x7B0-0x7BF are only visible to debug mode. Implementations should raise illegal-instruction exceptions on machine-mode access to the latter set of registers. |
norm:Zicsr_debug_illegal |
| Zicsr_wpri_roz | For forward compatibility, implementations that do not furnish these fields must make them read-only zero. These fields are labeled WPRI in the register descriptions. |
norm:Zicsr_wpri_roz |
| Zicsr_wlrl | Software should not write anything other than legal values to such a field, and should not assume a read will return a legal value unless the last write was of a legal value, or the register has not been written since another operation (e.g., reset) set the register to a legal value. These fields are labeled WLRL in the register descriptions. |
norm:Zicsr_wlrl |
| ZICSR_WLRL_EXCEPTION | extension | Rule's "kind" property |
| Zicsr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a WLRL field. |
norm:Zicsr_wlrl_exception | |
| ZICSR_WARL | extension | Rule's "kind" property |
| Zicsr | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| WARL | Implementation-defined behavior category | |
| Implementations will not raise an exception on writes of unsupported values to a WARL field. |
norm:Zicsr_warl |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| csrrw_op | The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. | norm:csrrw_op |
| csrrs_op | The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. | norm:csrrs_op |
| csrrc_op | The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable. | norm:csrrc_op |
| csrrwi_op | The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields. | norm:csrrwi_csrrsi_csrrci_ops |
| csrrsi_op | The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields. | norm:csrrwi_csrrsi_csrrci_ops |
| csrrci_op | The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields. | norm:csrrwi_csrrsi_csrrci_ops |
| zicsr_rs1_x0 | For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register other than x0, and that register holds a zero value, the instruction will not action any attendant per-field side effects, but will action any side effects caused by writing to the entire CSR. | norm:csrrs_csrrc_rs1_x0 |
| A CSRRW with rs1=x0 will attempt to write zero to the destination CSR. | norm:csrrw_rs1_x0 | |
| zicsr_rd_x0 | For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. |
norm:csrrwi_rd_x0 |
| zicsr_uimm_zero | For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. |
norm:csrrsi_csrrci_uimm_zero |
| zicsr_side_effects | summarizes the behavior of the CSR instructions with respect to whether they read and/or write the CSR. | norm:csr_side_effects |
| The CSRRS[I] and CSRRC[I] instructions only action side effects for fields for which the rs1 or uimm argument has at least one bit set corresponding to that field. |
norm:csr_rs1_uimm_side_effect | |
| zicsr_order | In particular, unless specified otherwise, a CSR access is performed after the execution of any prior instructions in program order whose behavior modifies or is modified by the CSR state and before the execution of any subsequent instructions in program order whose behavior modifies or is modified by the CSR state. |
norm:csr_access_order |
| an explicit CSR read returns the CSR state before the execution of the instruction |
norm:csrr_order | |
| an explicit CSR write suppresses and overrides any implicit writes or modifications to the same CSR by the same instruction. |
norm:csrw_order | |
| zicsr_side_effects_synchronous | Likewise, any side effects from an explicit CSR access are normally observed to occur synchronously in program order. Unless specified otherwise, the full consequences of any such side effects are observable by the very next instruction, and no consequences may be observed out-of-order by preceding instructions. |
norm:csr_side_effects_synchronous |
| zicsr_weakly_ordered | For the RVWMO memory consistency model (memorymodel), CSR accesses are weakly ordered by default, so other harts or devices may observe CSR accesses in an order different from program order. |
norm:csr_weakly_ordered |
| zicsr_memory_access_ordering | In addition, CSR accesses are not ordered with respect to explicit memory accesses, unless a CSR access modifies the execution behavior of the instruction that performs the explicit memory access or unless a CSR access and an explicit memory access are ordered by either the syntactic dependencies defined by the memory model or the ordering requirements defined by the Memory-Ordering PMAs section in Volume II of this manual. |
norm:csr_memory_access_ordering |
| zicsr_fence_ordering | To enforce ordering in all other cases, software should execute a FENCE instruction between the relevant accesses. For the purposes of the FENCE instruction, CSR read accesses are classified as device input (I), and CSR write accesses are classified as device output (O). |
norm:csr_fence_ordering |
| zicsr_strongly_ordered | The hardware platform may define that accesses to certain CSRs are strongly ordered, as defined by the Memory-Ordering PMAs section in Volume II of this manual. Accesses to strongly ordered CSRs have stronger ordering constraints with respect to accesses to both weakly ordered CSRs and accesses to memory-mapped I/O regions. |
norm:csr_strongly_ordered |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| fence_i_op | A FENCE.I instruction orders all explicit memory accesses that precede the FENCE.I in program order before all instruction fetches that follow the FENCE.I in program order. | norm:fence_i_op |
| fence_i_rsv | The unused fields in the FENCE.I instruction, funct12, rs1, and rd, are reserved for finer-grain fences in future extensions. For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields. | norm:fence_i_rsv |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| NTL_target_definition | The NTL instructions do not change architectural state, nor do they alter the architecturally visible effects of the target instruction. |
norm:NTL_target_definition |
| [CLARIFICATION] The target instruction of an NTL instruction SHALL be the instruction immediately following it in program order, and only the immediately preceding NTL instruction applies to any given memory-access instruction |
GitHub Issue | |
| NTL-P1_op | NTL.P1 indicates the target instruction does not exhibit temporal locality within the innermost level of private cache | Rule's "summary" property |
| The NTL.P1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of private cache in the memory hierarchy. |
norm:NTL-P1_op | |
| NTL-P1_enc | NTL.P1 is encoded as ADD x0, x0, x2 | Rule's "summary" property |
| NTL.P1 is encoded as ADD x0, x0, x2. |
norm:NTL-P1_enc | |
| NTL-PALL_op | NTL.PALL indicates the target instruction does not exhibit temporal locality within any level of private cache | Rule's "summary" property |
| The NTL.PALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of private cache in the memory hierarchy. |
norm:NTL-PALL_op | |
| NTL-PALL_enc | NTL.PALL is encoded as ADD x0, x0, x3 | Rule's "summary" property |
| NTL.PALL is encoded as ADD x0, x0, x3. | norm:NTL-PALL_enc | |
| NTL-S1_op | NTL.S1 indicates the target instruction does not exhibit temporal locality within the innermost level of shared cache | Rule's "summary" property |
| The NTL.S1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of shared cache in the memory hierarchy. |
norm:NTL-S1_op | |
| NTL-S1_enc | NTL.S1 is encoded as ADD x0, x0, x4 | Rule's "summary" property |
| NTL.S1 is encoded as ADD x0, x0, x4. |
norm:NTL-S1_enc | |
| NTL-ALL_op | NTL.ALL indicates the target instruction does not exhibit temporal locality within any level of cache | Rule's "summary" property |
| The NTL.ALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of cache in the memory hierarchy. |
norm:NTL-ALL_op | |
| NTL-ALL_enc | NTL.ALL is encoded as ADD x0, x0, x5 | Rule's "summary" property |
| NTL.ALL is encoded as ADD x0, x0, x5. | norm:NTL-ALL_enc | |
| C-NTL_availability | If the C or Zca extension is provided, compressed variants of these HINTs are also provided | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-P1_op | C.NTL.P1 indicates the target instruction does not exhibit temporal locality within the innermost private cache (compressed variant) | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-P1_enc | C.NTL.P1 is encoded as C.ADD x0, x2 | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-PALL_op | C.NTL.PALL indicates the target instruction does not exhibit temporal locality within any private cache (compressed variant) | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-PALL_enc | C.NTL.PALL is encoded as C.ADD x0, x3 | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-S1_op | C.NTL.S1 indicates the target instruction does not exhibit temporal locality within the innermost shared cache (compressed variant) | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-S1_enc | C.NTL.S1 is encoded as C.ADD x0, x4 | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-ALL_op | C.NTL.ALL indicates the target instruction does not exhibit temporal locality within any cache (compressed variant) | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| C-NTL-ALL_enc | C.NTL.ALL is encoded as C.ADD x0, x5 | Rule's "summary" property |
| If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5. |
norm:NTL-compressed_variants | |
| NTL_range | NTL instructions affect all memory-access instructions except Zicbom cache-management instructions | Rule's "summary" property |
| The NTL instructions affect all memory-access instructions except the cache-management instructions in the Zicbom extension. |
norm:NTL_range | |
| NTL_Zicob_prefetch_outer | When an NTL is applied to a Zicbop prefetch hint, the cache line is prefetched into a cache outer from the level specified by the NTL | Rule's "summary" property |
| When an NTL instruction is applied to a prefetch hint in the Zicbop extension, it indicates that a cache line should be prefetched into a cache that is outer from the level specified by the NTL. |
norm:NTL_Zicob_prefetch_outer | |
| NTL_TRAP_BEHAVIOR | In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler. Instead, implementations are recommended to ignore the HINT in this case. |
Rule's "summary" property |
| extension | Rule's "kind" property | |
| Zihintntl | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler. Instead, implementations are recommended to ignore the HINT in this case. |
norm:NTL_trap_behavior | |
| NTL-LR_SC_exception | Since the NTL instructions are encoded as ADDs, they can be used within LR/SC loops without voiding the forward-progress guarantee | Rule's "summary" property |
| Since the NTL instructions are encoded as ADDs, they can be used within LR/SC loops without voiding the forward-progress guarantee. But, since using other loads and stores within an LR/SC loop does void the forward-progress guarantee, the only reason to use an NTL within such a loop is to modify the LR or the SC. | norm:NTL-LR_SC_exception |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| pause_op | The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement should be temporarily reduced or paused. The duration of its effect must be bounded and may be zero. |
norm:pause_op |
| pause_enc_fence | PAUSE instruction is encoded in FENCE instruction | Rule's "summary" property |
| PAUSE is encoded as a FENCE instruction with pred=W, succ=0, fm=0, rd=x0, and rs1=x0. |
norm:pause_enc_fence |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| Zilsd_reg_pairs | Operands containing src for store instructions and dest for load instructions are held in aligned x-register pairs, i.e., register numbers must be even. | norm:Zilsd_reg_pairs |
| Zilsd_bits_to_pair | Regardless of endianness, the lower-numbered register holds the low-order bits, and the higher-numbered register holds the high-order bits |
norm:Zilsd_bits_to_pair |
| Zilsd_align8_no_exc | As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8. In this case, these instructions are guaranteed to not raise an address-misaligned exception. |
norm:Zilsd_align8_no_exc |
| ZILSD_ALIGN8_ATOMIC | extension | Rule's "kind" property |
| Zilsd | Rule's "instance" property | |
| Implementation-defined behavior | Rule's property | |
| Even if naturally aligned, the memory access might not be performed atomically. | norm:Zilsd_align8_atomic | |
| Zilsd_align4_atomic | If the effective address is a multiple of 4, then each word access is required to be performed atomically. | norm:Zilsd_align4_atomic |
| Zilsd_ld_resume_trap | The term 'base_register' in this rule means the register providing the memory address is also one of the destination registers for the load operation. |
Rule's "description" property |
| To ensure resumable trap handling is possible for the load instructions, the base register must have its original value if a trap is taken. |
norm:Zilsd_ld_resume_trap | |
| Zilsd_ld_x0 | LD instructions with destination x0 are processed as any other load, but the result is discarded entirely and x1 is not written. |
norm:Zilsd_ld_x0 |
| Zilsd_c-ldsp_x0 | For C.LDSP, usage of x0 as the destination is reserved. | norm:Zilsd_c-ldsp_x0 |
| Zilsd_sd_x0 | If using x0 as src of SD or C.SDSP, the entire 64-bit operand is zero — i.e., register x1 is not accessed. | norm:Zilsd_sd_x0 |
| Zilsd_RVWMO_exc_misaligned | For the purposes of RVWMO and exception handling, LD and SD instructions are considered to be misaligned loads and stores |
norm:Zilsd_RVWMO_exc_misaligned |
| Zilsd_align4_two_4byte | an LD or SD instruction whose effective address is a multiple of 4 gives rise to two 4-byte memory operations. |
norm:Zilsd_align4_two_4byte |
| Zilsd_ld_op | instruction | Rule's "kind" property |
| ld | Rule's "instance" property | |
| Loads a 64-bit value into registers rd and rd+1. The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | norm:Zilsd_ld_op | |
| Zilsd_sd_op | instruction | Rule's "kind" property |
| sd | Rule's "instance" property | |
| Stores a 64-bit value from registers rs2 and rs2+1. The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | norm:Zilsd_sd_op | |
| Zilsd_c-ldsp_op | instruction | Rule's "kind" property |
| c.ldsp | Rule's "instance" property | |
| Loads stack-pointer relative 64-bit value into registers rd' and rd'+1. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld rd, offset(x2). C.LDSP is only valid when rd≠x0; the code points with rd=x0 are reserved. | norm:Zilsd_c-ldsp_op | |
| Zilsd_c-sdsp_op | instruction | Rule's "kind" property |
| c.sdsp | Rule's "instance" property | |
| Stores a stack-pointer relative 64-bit value from registers rs2' and rs2'+1. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd rs2, offset(x2). | norm:Zilsd_c-sdsp_op | |
| Zilsd_c-ld_op | instruction | Rule's "kind" property |
| c.ld | Rule's "instance" property | |
| Loads a 64-bit value into registers rd' and rd'+1. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. | norm:Zilsd_c-ld_op | |
| Zilsd_c-sd_op | instruction | Rule's "kind" property |
| c.sd | Rule's "instance" property | |
| Stores a 64-bit value from registers rs2' and rs2'+1. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'. It expands to sd rs2', offset(rs1'). | norm:Zilsd_c-sd_op |
| Rule Name | Rule Description | Origin of Description | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Zimop_mop-r_op | The Zimop extension defines 32 MOP instructions named MOP.R.n, where n is an integer between 0 and 31, inclusive. Unless redefined by another extension, these instructions simply write 0 to x[rd]. |
norm:Zimop_mop-r_op | |||||||||||||||||||||||||||
| Zimop_mop-r_enc | Encoding for MOP.R.n |
Rule's "description" property | |||||||||||||||||||||||||||
| (No text available) | norm:Zimop_mop-r_enc | ||||||||||||||||||||||||||||
| Zimop_mop-rr_op | The Zimop extension additionally defines 8 MOP instructions named MOP.RR.n, where n is an integer between 0 and 7, inclusive. Unless redefined by another extension, these instructions simply write 0 to x[rd]. |
norm:Zimop_mop-rr_op | |||||||||||||||||||||||||||
| Zimop_mop-rr_enc | Encoding for MOP.RR.n |
Rule's "description" property | |||||||||||||||||||||||||||
| (No text available) | norm:Zimop_mop-rr_enc | ||||||||||||||||||||||||||||
| Zcmop_op | This section defines the "Zcmop" extension, which defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. |
norm:Zcmop_op | |||||||||||||||||||||||||||
| Zcmop_enc | C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0, as shown in norm:c-mop_enc. |
norm:Zcmop_enc | |||||||||||||||||||||||||||
| Zcmop_enc_table |
|
norm:c-mop_enc | |||||||||||||||||||||||||||
| Zcmop_instr_write | Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions are defined to not write any register. |
norm:Zcmop_instr_write |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| ztso_vect_mem | Vector memory instructions in ztso | Rule's "summary" property |
| Additionally, if the Ztso extension is implemented, then vector memory instructions in the V extension and Zve family of extensions follow RVTSO at the instruction level. |
norm:ztso_vect_mem | |
| ztso_ld | RVTSO makes the following adjustments to RVWMO: | norm:rvtso_adj_rvwmo |
| All load operations behave as if they have an acquire-RCpc annotation | norm:ztso_ld | |
| ztso_sd | RVTSO makes the following adjustments to RVWMO: | norm:rvtso_adj_rvwmo |
| All store operations behave as if they have a release-RCpc annotation. | norm:ztso_sd | |
| ztso_amo | RVTSO makes the following adjustments to RVWMO: | norm:rvtso_adj_rvwmo |
| All AMOs behave as if they have both acquire-RCsc and release-RCsc annotations. |
norm:ztso_amo |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| ARCH_ID | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The marchid CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
norm:marchid_sz_acc_op | |
| ASIDLEN | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| The number of ASID bits is UNSPECIFIED and may be zero. The number of implemented ASID bits, termed ASIDLEN, may be determined by writing one to every bit position in the ASID field, then reading back the value in satp to see which bit positions in the ASID field hold a one. The least-significant bits of ASID are implemented first: that is, if ASIDLEN > 0, ASID[ASIDLEN-1:0] is writable. The maximal value of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57. | norm:asidlen | |
| CACHE_BLOCK_SIZE | extension | Rule's "kind" property |
| [Zicbom, Zicbop, Zicboz] | Rule's "instances" property | |
| The capacity and organization of a cache and the size of a cache block are both implementation-specific, and the execution environment provides software a means to discover information about the caches and cache blocks in a system. In the initial set of CMO extensions, the size of a cache block shall be uniform throughout the system. |
norm:cache_block_size | |
| CRITICAL_ERROR | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The actions performed by the platform when a hart asserts a critical-error signal are platform-specific. The range of possible actions include restarting the affected hart or restarting the entire platform, among others. |
norm:critical_error | |
| CTRDATA_CC_SUPPORTED | ctrdata register may optionally include a count of CPU cycles | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| The ctrdata register may optionally include a count of CPU cycles elapsed since the prior CTR record. The elapsed cycle count value is represented by the CC field, which has a 12-bit mantissa component (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE). | norm:ctrdata_cc_supported | |
| CTR_CCOUNTER_IMPL | Implementation can support 0 to 4 exponent bits | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| An implementation that supports cycle counting must implement CCV and all CCM bits, but may implement 0..4 exponent bits in CCE. Unimplemented CCE bits are read-only 0. For implementations that support transfer type filtering, it is recommended to implement at least 3 exponent bits. This allows capturing the full latency of most functions, when recording only calls and returns. |
norm:ctr_ccounter_impl | |
| EE_IMPL_FLEX | base | Rule's "kind" property |
| Any | Rule's "instance" property | |
| The implementation of a RISC-V execution environment can be pure hardware, pure software, or a combination of hardware and software. For example, opcode traps and software emulation can be used to implement functionality not provided in hardware. |
norm:ee_impl_flex | |
| ELEN | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| The maximum size in bits of a vector element that any operation can produce or consume, ELEN {ge} 8, which must be a power of 2. |
norm:elen | |
| ENDIANNESS | base | Rule's "kind" property |
| Any | Rule's "instance" property | |
| The EEI will define whether the memory system is little-endian or big-endian. | norm:ENDIANNESS | |
| GEILEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie. | norm:geilen | |
| HART_ID | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The mhartid CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
norm:mhartid_sz_acc_op | |
| HGATP_VMID | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| The number of VMID bits is UNSPECIFIED and may be zero. | norm:hgatp_vmid | |
| HINT_SXLEN | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., c.addi x8, 0. When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits SXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1. | norm:hint_sxlen | |
| HPM_PLATFORM_SPECIFIC_IMPL | extension | Rule's "kind" property |
| Zihpm | Rule's "instance" property | |
| The implemented number and width of these additional counters, and the set of events they count, are platform-specific. |
norm:hpm_platform_specific_impl | |
| HPM_UNIMPLEMENTED_COUNTER_ACCESS | extension | Rule's "kind" property |
| Zihpm | Rule's "instance" property | |
| Accessing an unimplemented counter may cause an illegal-instruction exception or may return a constant value. |
norm:hpm_unimplemented_counter_access | |
| HSXLEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| we use the term HSXLEN to refer to the effective XLEN when executing in HS-mode |
norm:hsxlen | |
| HTVAL_TRAPVAL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| When a guest-page-fault trap is taken into HS-mode, htval is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, htval is set to zero, but a future standard or extension may redefine htval’s setting for other traps. | norm:htval_trapval | |
| HW_MSTATUS_VS_DIRTY_UPDATE | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementations may also change mstatus.VS or vsstatus.VS from Initial or Clean to Dirty at any time, even when there is no change in vector state. |
norm:hw_mstatus_vs_dirty_update | |
| IMP_ID | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The mimpid CSR provides a unique encoding of the version of the processor implementation. |
norm:mimpid_op | |
| INTERRUPTS_ALLOWED_IN_PUSHPOP | extension | Rule's "kind" property |
| Zcmp | Rule's "instance" property | |
| It is implementation defined whether interrupts can also be taken during the sequence execution. | norm:interrupts_allowed_in_pushpop | |
| LCOFI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| LR_RESERVATION_SET_SIZE | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword. |
norm:lr_reservation_set_size | |
| LR_SC_ALIGNMENT | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| For LR and SC, the Zalrsc extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words). If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated. |
norm:lr_sc_alignment | |
| MCAUSE_RST_ALIAS_OK | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| mcause reset values may alias mcause values following synchronous exceptions |
norm:mcause_rst_alias_ok | |
| MCAUSE_RST_VAL | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The mcause register is set to a value indicating the cause of the reset. | norm:mcause_rst1_val | |
| The mcause values after reset have implementation-specific interpretation |
norm:mcause_rst2_val | |
| MCONFIGPTR_VAL | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| it may be zero to indicate the configuration data structure does not exist or that an alternative mechanism must be used to locate it. |
norm:mconfigptr_val | |
| MCOUNTEREN_CY_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | |
| MCOUNTEREN_HPM_N_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | |
| MCOUNTEREN_IR_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | |
| MCOUNTEREN_TM_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | |
| MCYCLE_SHARED | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The mcycle CSR may be shared between harts on the same core, in which case writes to mcycle will be visible to those harts. |
norm:mcycle_shared | |
| MEDELEG_OP | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| implementations can provide individual read/write bits within medeleg and mideleg to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. |
norm:medeleg_mideleg_op1 | |
| setting a bit in medeleg or mideleg will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler. |
norm:medeleg_mideleg_op2 | |
| MENVCFG_FIOM_RDONLY0_OK | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If S-mode is not supported, or if satp.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero. |
norm:menvcfg_fiom_rdonly0_ok | |
| MEPC_INV_ADDR_CONV | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Prior to writing mepc, implementations may convert an invalid address into some other invalid address that mepc is capable of holding. |
norm:mepc_inv_addr_conv | |
| MHPMCOUNTER_N_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| a legal implementation is to make both the counter and its corresponding event selector be read-only 0. | norm:mhpmcounter_mhpmevent_rdonly0 | |
| MHPMCOUNTER_N_SZ | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| support up to 64 bits of precision on RV32 and RV64. | norm:mhpmcounter_sz | |
| MHPMEVENT_N_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| a legal implementation is to make both the counter and its corresponding event selector be read-only 0. | norm:mhpmcounter_mhpmevent_rdonly0 | |
| MIDELEG_OP | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| implementations can provide individual read/write bits within medeleg and mideleg to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. |
norm:medeleg_mideleg_op1 | |
| setting a bit in medeleg or mideleg will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler. |
norm:medeleg_mideleg_op2 | |
| MIDELEG_RD1_LOWER_LEVEL | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| may do so for lower-level interrupts | norm:mideleg_rd1_lower_level | |
| MIE_MSIE_MAYBE_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then mip.MSIP and mie.MSIE may both be read-only zeros. |
norm:mip_msip_mie_msie_maybe_rdonly0 | |
| MIP_BITS_WR_OR_RDONLY | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Each individual bit in register mip may be writable or may be read-only. | norm:mip_bits_wr_or_rdonly | |
| MIP_MSIP_MAYBE_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then mip.MSIP and mie.MSIE may both be read-only zeros. |
norm:mip_msip_mie_msie_maybe_rdonly0 | |
| MISALIGNED_ATOMICITY_GRANULE_SIZE | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| The misaligned atomicity granule PMA, defined in Volume II of this manual, optionally relaxes this alignment requirement. If present, the misaligned atomicity granule PMA specifies the size of a misaligned atomicity granule, a power-of-two number of bytes. The misaligned atomicity granule PMA applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions, and compressed encodings thereof. For an instruction in that set, if all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO--i.e., it will execute atomically. |
norm:misaligned_atomicity_granule_size | |
| MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| When an EEI does not guarantee misaligned loads and stores are handled invisibly, the EEI must define if exceptions caused by address misalignment result in a contained trap (allowing software running inside the execution environment to handle the trap) or a fatal trap (terminating execution). |
norm:misaligned_ldst_contained_or_fatal_trap | |
| MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| Loads and stores whose effective address is not naturally aligned to the referenced datatype (i.e., the effective address is not divisible by the size of the access in bytes) have behavior dependent on the EEI. |
norm:misaligned_ldst_eei_dependent_behavior | |
| MISALIGNED_LDST_EXC_TYPE | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| loads and stores that are not naturally aligned may either complete execution successfully or raise an exception. The exception raised can be either an address-misaligned exception or an access-fault exception. For a memory access that would otherwise be able to complete except for the misalignment, an access-fault exception can be raised instead of an address-misaligned exception if the misaligned access should not be emulated, e.g., if accesses to the memory region have side effects. |
norm:misaligned_ldst_exc_type | |
| MISALIGNED_LDST_HW_SUPPORT | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| misaligned loads and stores can be handled in hardware, or via an invisible trap into the execution environment implementation, or possibly a combination of hardware and invisible trap depending on address. |
norm:misaligned_ldst_hw_support | |
| MISA_CSR_IMPLEMENTED | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| a value of zero can be returned to indicate the misa register has not been implemented | norm:misa_csr_implemented | |
| MISA_EXTENSIONS_WRITABLE_BITS | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. |
norm:misa_extensions_warl_op | |
| MRET_CLR_LR_RESV | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If the A extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to. |
norm:xret_clr_lr_resv | |
| MSECCFG_MML_MMWP_RLB_RST | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The MML, MMWP, and RLB fields of the mseccfg register are set to 0, unless the platform mandates a different reset value. |
norm:mseccfg_mml_mmwp_rlb_rst | |
| MSECCFG_USEED_SSEED_RST | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The USEED and SSEED fields of the mseccfg CSR must have defined reset values. The system must not allow them to be in an undefined state after reset. |
norm:mseccfg_useed_sseed_rst | |
| MSIP_UPDATE_MAX_TIME | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| When the memory-mapped msip register changes, it is guaranteed to be reflected in mip.MSIP eventually, but not necessarily immediately. |
norm:msip_update_max_time | |
| MSTATUS_FS_IMPRECISE | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified. On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty. |
norm:mstatus_fs_imprecise | |
| MSTATUS_FS_NO_CHANGE_DIRTY | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If an instruction explicitly or implicitly writes a floating-point register or the fcsr but does not alter its contents, and FS=Initial or FS=Clean, it is implementation-defined whether FS transitions to Dirty. |
norm:mstatus_fs_no_change_dirty | |
| MSTATUS_FS_NO_DIRTY_TRACK | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| dirtiness might not be tracked at all, in which case the valid FS states are Off and Dirty, and an attempt to set FS to Initial or Clean causes it to be set to Dirty. |
norm:mstatus_fs_no_dirty_track | |
| MSTATUS_FS_RDONLY0_S_NO_F | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If S-mode is implemented but the F extension is not, FS may optionally be read-only zero. |
norm:mstatus_fs_rdonly0_s_no_f | |
| MSTATUS_SBE_ROCOPY | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If S-mode is supported, an implementation may make SBE be a read-only copy of MBE. |
norm:mstatus_sbe_rocopy | |
| MSTATUS_SXL_RDONLY_MXLEN64 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| an implementation may make SXL be a read-only field whose value always ensures that SXLEN=MXLEN. |
norm:mstatus_sxl_rdonly_mxlen64 | |
| MSTATUS_TW_ALWAYS_ILLEGAL | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| An implementation may have WFI always raise an illegal-instruction exception in modes less privileged than M when TW=1, even if there are pending globally-disabled interrupts when the instruction is executed. |
norm:mstatus_tw_always_illegal | |
| MSTATUS_TW_TIME_LIMIT | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception. |
norm:mstatus_tw_op | |
| MSTATUS_UBE_ROCOPY | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If U-mode is supported, an implementation may make UBE be a read-only copy of either MBE or SBE. |
norm:mstatus_ube_rocopy | |
| MSTATUS_VS_EXISTS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Analogous to the way in which the floating-point unit is handled, the mstatus.VS field may exist even if misa.V is clear. |
norm:mstatus_vs_exists | |
| MSTATUS_VS_IMPRECISE | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| [CONTEXT] Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified. On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty. |
norm:mstatus_fs_imprecise | |
| Implementations may choose to track the dirtiness of the vector register state in an analogous imprecise fashion, including possibly setting VS to Dirty when software attempts to set VS=Initial or VS=Clean. |
norm:mstatus_vs_imprecise | |
| MSTATUS_VS_NO_CHANGE_DIRTY | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| When VS=Initial or VS=Clean, it is implementation-defined whether an instruction that writes a vector register or vector CSR but does not alter its contents causes VS to transition to Dirty. |
norm:mstatus_vs_no_change_dirty | |
| MSTATUS_VS_RDONLY0_S_NO_V | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If S-mode is implemented but the v registers are not, VS may optionally be read-only zero. |
norm:mstatus_vs_rdonly0_s_no_v | |
| MTIME_TICK_PERIOD | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| the platform must provide a mechanism for determining the period of an mtime tick. |
norm:mtime_tick_period | |
| MTVAL2_TRAPVAL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| When a guest-page-fault trap is taken into M-mode, mtval2 is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, mtval2 is set to zero, but a future standard or extension may redefine mtval2’s setting for other traps. | norm:mtval2_trapval | |
| MTVAL_INV_ADDR_CONV | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Prior to writing mtval, implementations may convert an invalid address into some other invalid address that mtval is capable of holding. |
norm:mtval_inv_addr_conv | |
| MTVAL_PER_EXC_BEHAVIOR | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The hardware platform will specify which exceptions must set mtval informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception. |
norm:mtval_per_exc_behavior | |
| MTVAL_RDONLY0 | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If the hardware platform specifies that no exceptions set mtval to a nonzero value, then mtval is read-only zero. |
norm:mtval_rdonly0 | |
| MTVAL_VARLEN_WR | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If mtval is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then mtval will contain the virtual address of the portion of the instruction that caused the fault |
norm:mtval_varlen_wr | |
| MTVEC_BASE_ALIGN_FUNC_MODE | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| the MODE setting may impose additional alignment constraints on the value in the BASE field. |
norm:mtvec_base_align_func_mode | |
| MTVEC_RDONLY | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| [CONTEXT] The mtvec register must always be implemented | norm:mtvec_mandatory | |
| can contain a read-only value. | norm:mtvec_rdonly | |
| MUTABLE_MISA_V | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementations may have a writable misa.V field. | norm:mutable_misa_v | |
| MXLEN | XLEN in M-mode | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Sm | Rule's "instance" property | |
| If misa is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN. |
norm:misa_mxl_op_nz | |
| XLEN is never greater than MXLEN, but XLEN might be smaller than MXLEN in less-privileged modes. |
norm:xlen_le_mxlen | |
| NMI_ADDR | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Reset and NMI vector locations are given in a platform specification. | norm:rst_and_nmi_addr | |
| NMI_MCAUSE_VAL | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| mcause is set to a value indicating the source of the NMI. |
norm:nmi_mcause_val1 | |
| The values written to mcause on an NMI are implementation-defined. | norm:nmi_mcause_val2 | |
| NTL_TRAP_BEHAVIOR | In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler. Instead, implementations are recommended to ignore the HINT in this case. |
Rule's "summary" property |
| extension | Rule's "kind" property | |
| Zihintntl | Rule's "instance" property | |
| In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler. Instead, implementations are recommended to ignore the HINT in this case. |
norm:NTL_trap_behavior | |
| PMA_CACHE_MM_ALL_ATOMICS | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Some platforms might mandate that all of cacheable main memory support all atomic operations |
norm:pma_cache_mm_all_atomics | |
| PMA_IDP_IMPLICIT_SZ | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| [CONTEXT] For non-idempotent regions, implicit reads and writes must not be performed early or speculatively, with the following exceptions. When a non-speculative implicit read is performed, an implementation is permitted to additionally read any of the bytes within a naturally aligned power-of-2 region containing the address of the non-speculative implicit read. Furthermore, when a non-speculative instruction fetch is performed, an implementation is permitted to additionally read any of the bytes within the next naturally aligned power-of-2 region of the same size (with the address of the region taken modulo 2XLEN). |
norm:pma_idp_implicit_ok | |
| The size of these naturally aligned power-of-2 regions is implementation-defined, but, for systems with page-based virtual memory, must not exceed the smallest supported page size. |
norm:pma_idp_implicit_sz | |
| PMA_MAG_EXC | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Implementations may raise access-fault exceptions instead of address-misaligned exceptions for some misaligned accesses, indicating the instruction should not be emulated by a trap handler. |
norm:pma_mag_exc | |
| PMA_MAG_OP_LDST | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| [CONTEXT] If a misaligned AMO accesses a region that does not specify a misaligned atomicity granule PMA, or if not all accessed bytes lie within the same misaligned atomicity granule, then an exception is raised. |
norm:pma_mag_op_amo | |
| For regular loads and stores that access such a region or for which not all accessed bytes lie within the same atomicity granule, then either an exception is raised, or the access proceeds but is not guaranteed to be atomic. |
norm:pma_mag_op_ldst | |
| PMA_MM_IFETCH | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| [CONTEXT] Main memory regions always support read and write of all access widths required by the attached devices |
norm:pma_mm_rw | |
| can specify whether instruction fetch is supported. | norm:pma_mm_ifetch | |
| PMA_MO_DYN | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Systems might support dynamic configuration of ordering properties on each memory region. | norm:pma_mo_dyn | |
| PMP_A_L_RST | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers’ A and L fields. |
norm:pmp_A_L_rst | |
| PMP_ENTRY_COUNT | PMP supports up to 64 entries with allowed implementation counts and ordering rules | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Sm | Rule's "instance" property | |
| Up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first. |
norm:pmp_entry_count | |
| PMP_GRANULARITY | Minimum PMP region granularity supported by the platform | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Sm | Rule's "instance" property | |
| The granularity of PMP access control settings are platform-specific, but the standard PMP encoding supports regions as small as four bytes. |
norm:pmp_granularity | |
| RESERVED_VILL_SET | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| [CONTEXT] Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if vill was 1 beforehand. | norm:vtype_vset_rsv | |
| Implementations may set vill in either case. | norm:reserved_vill_set | |
| RST_ADDR | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Reset and NMI vector locations are given in a platform specification. | norm:rst_and_nmi_addr | |
| SATP_MODE_ROZ_SFENCE_ILLEGAL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| For implementations that make satp.MODE read-only zero (always Bare), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception. | norm:satp_mode_roz_sfence_illegal | |
| SEI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| SRET_CLR_LR_RESV | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| If the A extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to. |
norm:xret_clr_lr_resv | |
| SSI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| STI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| SXLEN | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively. | norm:sxlen_uxlen | |
| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | |
| UXLEN | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively. | norm:sxlen_uxlen | |
| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | |
| VECTOR_FF_PAST_TRAP | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming of the vector length (but not past the original vector length). The values of these spurious updates do not have to correspond to the values in memory at the addressed memory locations. Non-idempotent memory locations can only be accessed when it is known the corresponding element load operation will not be restarted due to a trap or vector-length trimming. | norm:vector_ff_past_trap | |
| VECTOR_FF_SEG_PARTIAL_ACCESS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| [CONTEXT] For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken. If an exception is detected partway through accessing a subsequent segment, vl is reduced to the index of that segment. | norm:vector_ls__seg_ff_unit-stride_op | |
| In both cases, it is implementation-defined whether a subset of the segment is loaded. | norm:vector_ff_seg_partial_access | |
| VECTOR_LS_CONSTANT_STRIDE_X0 | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| When rs2=x0, then an implementation is allowed, but not required, to perform fewer memory operations than the number of active elements, and may perform different numbers of memory operations across different dynamic executions of the same static instruction. | norm:vector_ls_constant_stride_x0 | |
| VECTOR_LS_MISSALIGNED_EXCEPTION | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address-misaligned exception is raised on that element. | norm:vector_ls_missaligned_exception | |
| VECTOR_LS_OVERWRITE_PAST_TRAP | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported. |
norm:vector_ls_overwrite_past_trap | |
| VECTOR_LS_SEG_FF_OVERLOAD | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| These instructions may overwrite destination vector register group elements past the point at which a trap is reported or past the point at which vector length is trimmed. | norm:vector_ls_seg_ff_overload | |
| VECTOR_LS_SEG_PARTIAL_ACCESS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| If a trap occurs during access to a segment, it is implementation-defined whether a subset of the faulting segment's accesses are performed before the trap is taken. |
norm:vector_ls_seg_partial_access | |
| VECTOR_LS_VSTART | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| All vector loads and stores may generate and accept a non-zero vstart value. | norm:vector_ls_vstart | |
| VECTOR_LS_WHOLEREG_MISSALIGNED_EXCEPTION | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation’s smallest supported SEW size in bytes (SEWMIN/8). | norm:vector_ls_wholereg_missaligned_exception | |
| VENDOR_ID_BANK | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | |
| VENDOR_ID_OFFSET | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | |
| VLEN | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| The number of bits in a single vector register, VLEN {ge} ELEN, which must be a power of 2, and must be no greater than 216. | norm:vlen | |
| VSSTATUS_UBE | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| An implementation may make field UBE be a read-only copy of hstatus.VSBE. | norm:vsstatus_ube | |
| VSSTATUS_VS_EXISTS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| For implementations with a writable misa.V field, the vsstatus.VS field may exist even if misa.V is clear. | norm:vsstatus_vs_exists | |
| VSXLEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| VSXLEN to refer to the effective XLEN when executing in VS-mode. |
norm:vsxlen | |
| VSXL_RO | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN. |
norm:vsxl_ro | |
| VTW_VIRTINSTR | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| An implementation may have WFI always raise a virtual-instruction exception in VS-mode when VTW=1 (and mstatus.TW=0), even if there are pending globally-disabled interrupts when the instruction is executed. |
norm:vtw_virtinstr | |
| WFI_OPT_U_MODE | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| optionally available to U-mode. | norm:wfi_opt_U_mode | |
| WFI_RESUME_REASON | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Implementations are permitted to resume execution for any reason, even if an enabled interrupt has not become pending. Hence, a legal implementation is to simply implement the WFI instruction as a NOP. |
norm:wfi_resume_reason | |
| XLEN_REDUCTION_HINT_OP | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., c.addi x8, 0. When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits MXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1. | norm:xlen_reduction_hint_op1 | |
| This definition allows implementations to elide register write-back for some HINTs, while allowing them to execute other HINTs in the same manner as other integer computational instructions. The implementation choice is observable only by privilege modes with an XLEN setting greater than the current XLEN; it is invisible to the current privilege mode. |
norm:xlen_reduction_hint_op2 | |
| ZICSR_WLRL_EXCEPTION | extension | Rule's "kind" property |
| Zicsr | Rule's "instance" property | |
| Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a WLRL field. |
norm:Zicsr_wlrl_exception | |
| ZILSD_ALIGN8_ATOMIC | extension | Rule's "kind" property |
| Zilsd | Rule's "instance" property | |
| Even if naturally aligned, the memory access might not be performed atomically. | norm:Zilsd_align8_atomic |
| Rule Name | Rule Description | Origin of Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| CTRSOURCE_WARL | extension | Rule's "kind" property | |||||||||
| Smctr | Rule's "instance" property | ||||||||||
| ctrsource is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended. | norm:Ssctr_ctrsource_sz_acc_op | ||||||||||
| CTRTARGET_WARL | extension | Rule's "kind" property | |||||||||
| Smctr | Rule's "instance" property | ||||||||||
| ctrtarget is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended. | norm:ctrtarget_sz_acc | ||||||||||
| HCOUNTEREN_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| hcounteren must be implemented. However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when V=1. Hence, they are effectively WARL fields. | norm:hcounteren_warl | ||||||||||
| HEDELEG_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:hedeleg_img | ||||||||||
| HENVCFG_CBIE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to henvcfg. The CBIE field controls execution of the cache block invalidate instruction (CBO.INVAL) in privilege modes VS and VU. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. | norm:henvcfg_cbie | ||||||||||
| HGATP_MODE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| A write to hgatp with an unsupported MODE value is not ignored as it is for satp. Instead, the fields of hgatp are WARL in the normal way, when so indicated. | norm:hgatp_mode_warl | ||||||||||
| HGEIE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:hgeie_img | ||||||||||
| HIDELEG_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:hideleg_img | ||||||||||
| HIE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:hie_img | ||||||||||
| HIP_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:hip_img | ||||||||||
| HSTATUS_VSBE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| The VSBE bit is a WARL field that controls the endianness of explicit memory accesses made from VS-mode. If VSBE=0, explicit load and store memory accesses made from VS-mode are little-endian, and if VSBE=1, they are big-endian. VSBE also controls the endianness of all implicit accesses to VS-level memory management data structures, such as page tables. An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode. | norm:hstatus_vsbe_op | ||||||||||
| HSTATUS_VSXL_64_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| When HSXLEN=64, VSXL is a WARL field that is encoded the same as the MXL field of misa, shown in norm:misa_mxl_enc. |
norm:hstatus_vsxl_64 | ||||||||||
| HTINST_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:htinst_val | ||||||||||
| HTVAL_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:htval_val | ||||||||||
| HVIP_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:hvip_img | ||||||||||
| JVT_MODE_WARL | extension | Rule's "kind" property | |||||||||
| Zcmt | Rule's "instance" property | ||||||||||
| jvt.mode is a WARL field, so can only be programmed to modes which are implemented. | norm:jvt_mode_acc | ||||||||||
| JVT_WARL | extension | Rule's "kind" property | |||||||||
| Zcmt | Rule's "instance" property | ||||||||||
| The jvt register is an XLEN-bit WARL read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE). | norm:jvt_reg | ||||||||||
| MCOUNTEREN_FLDS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| In harts with U-mode, the mcounteren must be implemented, but all fields are WARL |
norm:mcounteren_flds_mandatory_warl | ||||||||||
| MCOUNTINHIBIT_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
norm:mcountinhibit_sz_warl_op1 | ||||||||||
| MEDELEG_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in medeleg or mideleg to see which bit positions hold a one. |
norm:medeleg_mideleg_warl | ||||||||||
| MENVCFG_CBIE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to menvcfg to control execution of the cache block invalidate instruction (CBO.INVAL) in modes less privileged than M. When CBIE is set to 00b, the instruction raises an illegal-instruction exception in modes less privileged than M. |
norm:menvcfg_cbie_warl_op | ||||||||||
| MEPC_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| mepc is a WARL register | norm:mepc_warl | ||||||||||
| MHPMCOUNTER_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mhpmcounters are WARL registers | norm:mhpmcounter_warl | ||||||||||
| MHPMEVENT_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The event selector CSRs, mhpmevent3-mhpmevent31, are 64-bit WARL registers that control which event causes the corresponding counter to increment. |
norm:mhpmevent_sz_warl_op | ||||||||||
| MIDELEG_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in medeleg or mideleg to see which bit positions hold a one. |
norm:medeleg_mideleg_warl | ||||||||||
| MISA_EXTENSIONS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. |
norm:misa_extensions_warl_op | ||||||||||
| MISA_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The misa CSR is a WARL read-write register | norm:misa_acc | ||||||||||
| MISELECT_WARL | extension | Rule's "kind" property | |||||||||
| Smcsrind | Rule's "instance" property | ||||||||||
| miselect is a WARL register. |
norm:miselect_WARL | ||||||||||
| MNCAUSE_WARL | extension | Rule's "kind" property | |||||||||
| Smrnmi | Rule's "instance" property | ||||||||||
| (No text available) | norm:mncause_img | ||||||||||
| MNEPC_WARL | extension | Rule's "kind" property | |||||||||
| Smrnmi | Rule's "instance" property | ||||||||||
| mnepc is a WARL register that must be able to hold all valid virtual addresses. |
norm:mnepc_warl | ||||||||||
| MNSTATUS_WARL | extension | Rule's "kind" property | |||||||||
| Smrnmi | Rule's "instance" property | ||||||||||
| (No text available) | norm:mnstatus_img | ||||||||||
| MSECCFG_MML_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mseccfg.MML (Machine Mode Lockdown) is a WARL field. | norm:mseccfg_mml_warl | ||||||||||
| MSECCFG_MMWP_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mseccfg.MMWP (Machine-Mode Allowlist Policy) is a WARL field. This field changes the default PMP policy for Machine mode when accessing memory regions that don’t have a matching PMP rule. This is a sticky bit, meaning that once set it cannot be unset until a PMP reset. When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching PMP rule, to denied instead of ignored. | norm:mseccfg_mmwp_op_warl | ||||||||||
| MSECCFG_PMM_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
|
norm:mseccfg_pmm_enc | ||||||||||
| MSECCFG_RLB_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| When mseccfg.RLB (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify Locked PMP rules. When mseccfg.RLB is 1, locked PMP rules may be removed or modified and locked PMP rules may be edited. When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset. | norm:mseccfg_rlb_op_warl | ||||||||||
| MSTATUSH_MBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUSH_SBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUSH_UBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUS_FS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The FS[1:0] and VS[1:0] WARL fields | norm:mstatus_fs_vs_warl | ||||||||||
| MSTATUS_MBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUS_MDT_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The M-mode-disable-trap (MDT) bit is a WARL field introduced by the Smdbltrp extension. | norm:mstatus_mdt_sz_warl | ||||||||||
| MSTATUS_SBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUS_SXL_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | ||||||||||
| MSTATUS_TSR_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The TSR (Trap SRET) bit is a WARL field that supports intercepting the supervisor exception return instruction, SRET. |
norm:mstatus_tsr_warl | ||||||||||
| MSTATUS_TVM_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported. | norm:mstatus_tvm_warl_op | ||||||||||
| MSTATUS_TW_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The TW (Timeout Wait) bit is a WARL field that supports intercepting the WFI instruction (see wfi). |
norm:mstatus_tw_warl | ||||||||||
| MSTATUS_UBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUS_UXL_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | ||||||||||
| MSTATUS_VS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The FS[1:0] and VS[1:0] WARL fields | norm:mstatus_fs_vs_warl | ||||||||||
| MSTATUS_XPP_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| xPP fields are WARL fields that can hold only privilege mode x and any implemented privilege mode lower than x. | norm:mstatus_xpp_warl | ||||||||||
| MTINST_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| mtinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:mtinst_val | ||||||||||
| MTVAL2_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| mtval2 is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:mtval2_val | ||||||||||
| MTVAL_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If mtval is not read-only zero, it is a WARL register | norm:mtval_warl | ||||||||||
| MTVEC_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mtvec register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). |
norm:mtvec_sz_warl_acc | ||||||||||
| PMP_ADDR_WARL | PMP address registers are WARL due to optional physical address bits | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Sm | Rule's "instance" property | ||||||||||
| Not all physical address bits may be implemented, and so the pmpaddr registers are WARL. |
norm:pmp_addr_warl | ||||||||||
| PMP_CSRS_WARL_ACCESS | PMP CSRs are WARL, may read as zero, and are accessible only in M-mode | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Sm | Rule's "instance" property | ||||||||||
| All PMP CSR fields are WARL and may be read-only zero. |
norm:pmp_csrs_warl_access | ||||||||||
| PMP_RWX_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved. |
norm:pmp_rwx_warl | ||||||||||
| SCOUNTEREN_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| scounteren must be implemented. However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when executing in U-mode. Hence, they are effectively WARL fields. | norm:scounteren_acc | ||||||||||
| SCTRDEPTH_DEPTH | WARL field encoding CTR buffer depth (16–256, reserved encodings). | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Smctr | Rule's "instance" property | ||||||||||
| WARL field that selects the depth of the CTR buffer. | norm:sctrdepth_depth_op0 | ||||||||||
| The depth of the CTR buffer dictates the number of entries to which the hardware records transfers. For a depth of N, the hardware records transfers to entries 0..N-1. All Entry Registers read as '0' and are read-only when the selected entry is in the range N to 255. When the depth is increased, the newly accessible entries contain unspecified but legal values. | norm:sctrdepth_depth_op1 | ||||||||||
| It is implementation-specific which DEPTH value(s) are supported. | norm:sctrdepth_depth | ||||||||||
| SCTRDEPTH_WARL | extension | Rule's "kind" property | |||||||||
| Smctr | Rule's "instance" property | ||||||||||
| WARL field that selects the depth of the CTR buffer. | norm:sctrdepth_depth_op0 | ||||||||||
| SCTRSTATUS_WRPTR_WARL | extension | Rule's "kind" property | |||||||||
| Smctr | Rule's "instance" property | ||||||||||
| WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see Behavior), though there are exceptions when xctrctl.RASEMU=1, see RAS (Return Address Stack) Emulation Mode. For a given CTR depth (where depth = 2(DEPTH+4)), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value. | norm:sctrstatus_wrptr | ||||||||||
| SENVCFG_CBIE_WARL | extension | Rule's "kind" property | |||||||||
| Zicboz | Rule's "instance" property | ||||||||||
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to senvcfg to control execution of the CBO.INVAL instruction in U-mode. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. Execution of CBO.INVAL in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and CBIE is set to 01b or 11b; otherwise, an illegal-instruction exception is raised. | norm:senvcfg_cbie | ||||||||||
| SEPC_ACC_INVALID_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| sepc is a WARL register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid addresses. Prior to writing sepc, implementations may convert an invalid address into some other invalid address that sepc is capable of holding. | norm:sepc_acc_invalid_addr | ||||||||||
| SIE_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| All bits in sip and sie are WARL fields. The implemented interrupts may be found by writing one to every bit location in sie, then reading back to see which bit positions hold a one. |
norm:sip_sie_warl | ||||||||||
| SIP_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| All bits in sip and sie are WARL fields. The implemented interrupts may be found by writing one to every bit location in sie, then reading back to see which bit positions hold a one. |
norm:sip_sie_warl | ||||||||||
| SSTATUS_SDT_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| The S-mode-disable-trap (SDT) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M. | norm:sstatus_sdt | ||||||||||
| SSTATUS_UBE_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| The UBE bit is a WARL field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode. An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode. | norm:sstatus_ube | ||||||||||
| SSTATUS_UXL_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| When SXLEN=32, the UXL field does not exist, and UXLEN=32. When SXLEN=64, it is a WARL field that encodes the current value of UXLEN. In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN. | norm:sstatus_uxl_sz | ||||||||||
| STATEEN_WARL_ACCESS | extension | Rule's "kind" property | |||||||||
| Smstateen | Rule's "instance" property | ||||||||||
| Each standard-defined bit of a stateen CSR is WARL and may be read-only zero or one, subject to the following conditions. | norm:stateen_warl_access | ||||||||||
| STVAL_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| stval is a WARL register that must be able to hold all valid virtual addresses and the value 0. It need not be capable of holding all possible invalid addresses. Prior to writing stval, implementations may convert an invalid address into some other invalid address that stval is capable of holding. If the feature to return the faulting instruction bits is implemented, stval must also be able to hold all values less than 2N, where N is the smaller of SXLEN and ILEN. | norm:stval_acc | ||||||||||
| STVEC_BASE_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| (No text available) | norm:stvec_img | ||||||||||
| STVEC_MODE_WARL | extension | Rule's "kind" property | |||||||||
| S | Rule's "instance" property | ||||||||||
| (No text available) | norm:stvec_img | ||||||||||
| VSATP_MODE_UNSUPPORTED_V0_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| When V=0, a write to vsatp with an unsupported MODE value is either ignored as it is for satp, or the fields of vsatp are treated as WARL in the normal way. |
norm:vsatp_mode_unsupported_v0 | ||||||||||
| VSEPC_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| vsepc is a WARL register that must be able to hold the same set of values that sepc can hold. | norm:vsepc_warl | ||||||||||
| VSIE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:vsie_img | ||||||||||
| VSIP_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:vsip_img | ||||||||||
| VSSTATUS_UXL_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| The UXL field controls the effective XLEN for VU-mode, which may differ from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a WARL field that is encoded the same as the MXL field of misa, shown in . In particular, an implementation may make UXL be a read-only copy of field VSXL of hstatus, forcing VU-mode XLEN=VSXLEN. | norm:vsstatus_uxl_op | ||||||||||
| VSTVAL_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| vstval is a WARL register that must be able to hold the same set of values that stval can hold. | norm:vstval_warl | ||||||||||
| VSTVEC_BASE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:vstvec_img | ||||||||||
| VSTVEC_MODE_WARL | extension | Rule's "kind" property | |||||||||
| H | Rule's "instance" property | ||||||||||
| (No text available) | norm:vstvec_img | ||||||||||
| WARL_RST | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| No WARL field contains an illegal value. | norm:warl_rst | ||||||||||
| ZICSR_WARL | extension | Rule's "kind" property | |||||||||
| Zicsr | Rule's "instance" property | ||||||||||
| Implementations will not raise an exception on writes of unsupported values to a WARL field. |
norm:Zicsr_warl |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| HSTATUS_VGEIN_WLRL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| The VGEIN (Virtual Guest External Interrupt Number) field selects a guest external interrupt source for VS-level external interrupts. VGEIN is a WLRL field that must be able to hold values between zero and the maximum guest external interrupt number (known as GEILEN), inclusive. When VGEIN=0, no guest external interrupt source is selected for VS-level external interrupts. GEILEN may be zero, in which case VGEIN may be read-only zero. Guest external interrupts are explained in , and the use of VGEIN is covered further in . | norm:hstatus_vgein_op | |
| MCAUSE_EXCCODE_WLRL | extension | Rule's "kind" property |
| Sm | Rule's "instance" property | |
| The Exception Code is a WLRL field, so is only guaranteed to hold supported exception codes. | norm:mcause_exccode_wlrl | |
| SCAUSE_EXCEPTION_CODE_ACC | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| The Exception Code is a WLRL field. |
norm:scause_exception_code_acc | |
| VSCAUSE_WLRL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| vscause is a WLRL register that must be able to hold the same set of values that scause can hold. | norm:vscause_wlrl |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| LR_SC_ALIGNMENT | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| For LR and SC, the Zalrsc extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words). If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated. |
norm:lr_sc_alignment | |
| LR_RESERVATION_SET_SIZE | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword. |
norm:lr_reservation_set_size | |
| MISALIGNED_ATOMICITY_GRANULE_SIZE | extension | Rule's "kind" property |
| A | Rule's "instance" property | |
| The misaligned atomicity granule PMA, defined in Volume II of this manual, optionally relaxes this alignment requirement. If present, the misaligned atomicity granule PMA specifies the size of a misaligned atomicity granule, a power-of-two number of bytes. The misaligned atomicity granule PMA applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions, and compressed encodings thereof. For an instruction in that set, if all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO--i.e., it will execute atomically. |
norm:misaligned_atomicity_granule_size |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| CACHE_BLOCK_SIZE | extension | Rule's "kind" property |
| [Zicbom, Zicbop, Zicboz] | Rule's "instances" property | |
| The capacity and organization of a cache and the size of a cache block are both implementation-specific, and the execution environment provides software a means to discover information about the caches and cache blocks in a system. In the initial set of CMO extensions, the size of a cache block shall be uniform throughout the system. |
norm:cache_block_size |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| HPM_PLATFORM_SPECIFIC_IMPL | extension | Rule's "kind" property |
| Zihpm | Rule's "instance" property | |
| The implemented number and width of these additional counters, and the set of events they count, are platform-specific. |
norm:hpm_platform_specific_impl | |
| HPM_UNIMPLEMENTED_COUNTER_ACCESS | extension | Rule's "kind" property |
| Zihpm | Rule's "instance" property | |
| Accessing an unimplemented counter may cause an illegal-instruction exception or may return a constant value. |
norm:hpm_unimplemented_counter_access |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| HSXLEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| we use the term HSXLEN to refer to the effective XLEN when executing in HS-mode |
norm:hsxlen | |
| VSXLEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| VSXLEN to refer to the effective XLEN when executing in VS-mode. |
norm:vsxlen | |
| HSTATUS_VSXL_64_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| When HSXLEN=64, VSXL is a WARL field that is encoded the same as the MXL field of misa, shown in norm:misa_mxl_enc. |
norm:hstatus_vsxl_64 | |
| VSXL_RO | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN. |
norm:vsxl_ro | |
| VTW_VIRTINSTR | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| An implementation may have WFI always raise a virtual-instruction exception in VS-mode when VTW=1 (and mstatus.TW=0), even if there are pending globally-disabled interrupts when the instruction is executed. |
norm:vtw_virtinstr | |
| HSTATUS_VGEIN_WLRL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WLRL | Implementation-defined behavior category | |
| The VGEIN (Virtual Guest External Interrupt Number) field selects a guest external interrupt source for VS-level external interrupts. VGEIN is a WLRL field that must be able to hold values between zero and the maximum guest external interrupt number (known as GEILEN), inclusive. When VGEIN=0, no guest external interrupt source is selected for VS-level external interrupts. GEILEN may be zero, in which case VGEIN may be read-only zero. Guest external interrupts are explained in , and the use of VGEIN is covered further in . | norm:hstatus_vgein_op | |
| HSTATUS_VSBE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| The VSBE bit is a WARL field that controls the endianness of explicit memory accesses made from VS-mode. If VSBE=0, explicit load and store memory accesses made from VS-mode are little-endian, and if VSBE=1, they are big-endian. VSBE also controls the endianness of all implicit accesses to VS-level memory management data structures, such as page tables. An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode. | norm:hstatus_vsbe_op | |
| HEDELEG_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hedeleg_img | |
| HIDELEG_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hideleg_img | |
| HVIP_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hvip_img | |
| HIP_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hip_img | |
| HIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hie_img | |
| HGEIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:hgeie_img | |
| GEILEN | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie. | norm:geilen | |
| HCOUNTEREN_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| hcounteren must be implemented. However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when V=1. Hence, they are effectively WARL fields. | norm:hcounteren_warl | |
| HTVAL_TRAPVAL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| When a guest-page-fault trap is taken into HS-mode, htval is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, htval is set to zero, but a future standard or extension may redefine htval’s setting for other traps. | norm:htval_trapval | |
| HTVAL_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:htval_val | |
| HTINST_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:htinst_val | |
| HGATP_MODE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| A write to hgatp with an unsupported MODE value is not ignored as it is for satp. Instead, the fields of hgatp are WARL in the normal way, when so indicated. | norm:hgatp_mode_warl | |
| HGATP_VMID | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| The number of VMID bits is UNSPECIFIED and may be zero. | norm:hgatp_vmid | |
| VSSTATUS_UXL_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| The UXL field controls the effective XLEN for VU-mode, which may differ from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32. When VSXLEN=64, UXL is a WARL field that is encoded the same as the MXL field of misa, shown in . In particular, an implementation may make UXL be a read-only copy of field VSXL of hstatus, forcing VU-mode XLEN=VSXLEN. | norm:vsstatus_uxl_op | |
| VSSTATUS_UBE | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| An implementation may make field UBE be a read-only copy of hstatus.VSBE. | norm:vsstatus_ube | |
| VSIP_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vsip_img | |
| VSIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vsie_img | |
| VSTVEC_MODE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vstvec_img | |
| VSTVEC_BASE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:vstvec_img | |
| VSEPC_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| vsepc is a WARL register that must be able to hold the same set of values that sepc can hold. | norm:vsepc_warl | |
| VSCAUSE_WLRL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WLRL | Implementation-defined behavior category | |
| vscause is a WLRL register that must be able to hold the same set of values that scause can hold. | norm:vscause_wlrl | |
| VSTVAL_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| vstval is a WARL register that must be able to hold the same set of values that stval can hold. | norm:vstval_warl | |
| VSATP_MODE_UNSUPPORTED_V0_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| When V=0, a write to vsatp with an unsupported MODE value is either ignored as it is for satp, or the fields of vsatp are treated as WARL in the normal way. |
norm:vsatp_mode_unsupported_v0 | |
| MTVAL2_TRAPVAL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| When a guest-page-fault trap is taken into M-mode, mtval2 is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, mtval2 is set to zero, but a future standard or extension may redefine mtval2’s setting for other traps. | norm:mtval2_trapval | |
| MTVAL2_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| mtval2 is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any. | norm:mtval2_val | |
| MTINST_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| mtinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap. | norm:mtinst_val | |
| HENVCFG_CBIE_WARL | extension | Rule's "kind" property |
| H | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to henvcfg. The CBIE field controls execution of the cache block invalidate instruction (CBO.INVAL) in privilege modes VS and VU. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. | norm:henvcfg_cbie |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| MISELECT_WARL | extension | Rule's "kind" property |
| Smcsrind | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| miselect is a WARL register. |
norm:miselect_WARL |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| EE_IMPL_FLEX | base | Rule's "kind" property |
| Any | Rule's "instance" property | |
| The implementation of a RISC-V execution environment can be pure hardware, pure software, or a combination of hardware and software. For example, opcode traps and software emulation can be used to implement functionality not provided in hardware. |
norm:ee_impl_flex |
| Rule Name | Rule Description | Origin of Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| MISA_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The misa CSR is a WARL read-write register | norm:misa_acc | ||||||||||
| MISA_CSR_IMPLEMENTED | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| a value of zero can be returned to indicate the misa register has not been implemented | norm:misa_csr_implemented | ||||||||||
| MXLEN | XLEN in M-mode | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Sm | Rule's "instance" property | ||||||||||
| If misa is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN. |
norm:misa_mxl_op_nz | ||||||||||
| XLEN is never greater than MXLEN, but XLEN might be smaller than MXLEN in less-privileged modes. |
norm:xlen_le_mxlen | ||||||||||
| MISA_EXTENSIONS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. |
norm:misa_extensions_warl_op | ||||||||||
| MISA_EXTENSIONS_WRITABLE_BITS | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. |
norm:misa_extensions_warl_op | ||||||||||
| VENDOR_ID_BANK | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | ||||||||||
| VENDOR_ID_OFFSET | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
norm:mvendorid_sz_acc_op | ||||||||||
| ARCH_ID | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The marchid CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
norm:marchid_sz_acc_op | ||||||||||
| IMP_ID | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mimpid CSR provides a unique encoding of the version of the processor implementation. |
norm:mimpid_op | ||||||||||
| HART_ID | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mhartid CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
norm:mhartid_sz_acc_op | ||||||||||
| MSTATUS_XPP_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| xPP fields are WARL fields that can hold only privilege mode x and any implemented privilege mode lower than x. | norm:mstatus_xpp_warl | ||||||||||
| MSTATUS_MDT_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The M-mode-disable-trap (MDT) bit is a WARL field introduced by the Smdbltrp extension. | norm:mstatus_mdt_sz_warl | ||||||||||
| MSTATUS_SXL_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | ||||||||||
| MSTATUS_UXL_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. |
norm:mstatus_sxl_uxl_warl_op | ||||||||||
| MSTATUS_SXL_RDONLY_MXLEN64 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| an implementation may make SXL be a read-only field whose value always ensures that SXLEN=MXLEN. |
norm:mstatus_sxl_rdonly_mxlen64 | ||||||||||
| MSTATUS_MBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUS_SBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUS_UBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUSH_MBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUSH_SBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUSH_UBE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields | norm:mstatus_mstatush_xbe_warl | ||||||||||
| MSTATUS_SBE_ROCOPY | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If S-mode is supported, an implementation may make SBE be a read-only copy of MBE. |
norm:mstatus_sbe_rocopy | ||||||||||
| MSTATUS_UBE_ROCOPY | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If U-mode is supported, an implementation may make UBE be a read-only copy of either MBE or SBE. |
norm:mstatus_ube_rocopy | ||||||||||
| MSTATUS_TVM_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported. | norm:mstatus_tvm_warl_op | ||||||||||
| MSTATUS_TW_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The TW (Timeout Wait) bit is a WARL field that supports intercepting the WFI instruction (see wfi). |
norm:mstatus_tw_warl | ||||||||||
| MSTATUS_TW_TIME_LIMIT | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception. |
norm:mstatus_tw_op | ||||||||||
| MSTATUS_TW_ALWAYS_ILLEGAL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| An implementation may have WFI always raise an illegal-instruction exception in modes less privileged than M when TW=1, even if there are pending globally-disabled interrupts when the instruction is executed. |
norm:mstatus_tw_always_illegal | ||||||||||
| MSTATUS_TSR_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The TSR (Trap SRET) bit is a WARL field that supports intercepting the supervisor exception return instruction, SRET. |
norm:mstatus_tsr_warl | ||||||||||
| MSTATUS_FS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The FS[1:0] and VS[1:0] WARL fields | norm:mstatus_fs_vs_warl | ||||||||||
| MSTATUS_VS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The FS[1:0] and VS[1:0] WARL fields | norm:mstatus_fs_vs_warl | ||||||||||
| MSTATUS_FS_RDONLY0_S_NO_F | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If S-mode is implemented but the F extension is not, FS may optionally be read-only zero. |
norm:mstatus_fs_rdonly0_s_no_f | ||||||||||
| MSTATUS_VS_RDONLY0_S_NO_V | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If S-mode is implemented but the v registers are not, VS may optionally be read-only zero. |
norm:mstatus_vs_rdonly0_s_no_v | ||||||||||
| MSTATUS_FS_IMPRECISE | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified. On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty. |
norm:mstatus_fs_imprecise | ||||||||||
| MSTATUS_FS_NO_DIRTY_TRACK | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| dirtiness might not be tracked at all, in which case the valid FS states are Off and Dirty, and an attempt to set FS to Initial or Clean causes it to be set to Dirty. |
norm:mstatus_fs_no_dirty_track | ||||||||||
| MSTATUS_FS_NO_CHANGE_DIRTY | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If an instruction explicitly or implicitly writes a floating-point register or the fcsr but does not alter its contents, and FS=Initial or FS=Clean, it is implementation-defined whether FS transitions to Dirty. |
norm:mstatus_fs_no_change_dirty | ||||||||||
| MSTATUS_VS_IMPRECISE | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| [CONTEXT] Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified. On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty. |
norm:mstatus_fs_imprecise | ||||||||||
| Implementations may choose to track the dirtiness of the vector register state in an analogous imprecise fashion, including possibly setting VS to Dirty when software attempts to set VS=Initial or VS=Clean. |
norm:mstatus_vs_imprecise | ||||||||||
| MSTATUS_VS_NO_CHANGE_DIRTY | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| When VS=Initial or VS=Clean, it is implementation-defined whether an instruction that writes a vector register or vector CSR but does not alter its contents causes VS to transition to Dirty. |
norm:mstatus_vs_no_change_dirty | ||||||||||
| MTVEC_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The mtvec register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). |
norm:mtvec_sz_warl_acc | ||||||||||
| MTVEC_RDONLY | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| [CONTEXT] The mtvec register must always be implemented | norm:mtvec_mandatory | ||||||||||
| can contain a read-only value. | norm:mtvec_rdonly | ||||||||||
| MTVEC_BASE_ALIGN_FUNC_MODE | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| the MODE setting may impose additional alignment constraints on the value in the BASE field. |
norm:mtvec_base_align_func_mode | ||||||||||
| MEDELEG_OP | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| implementations can provide individual read/write bits within medeleg and mideleg to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. |
norm:medeleg_mideleg_op1 | ||||||||||
| setting a bit in medeleg or mideleg will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler. |
norm:medeleg_mideleg_op2 | ||||||||||
| MIDELEG_OP | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| implementations can provide individual read/write bits within medeleg and mideleg to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. |
norm:medeleg_mideleg_op1 | ||||||||||
| setting a bit in medeleg or mideleg will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler. |
norm:medeleg_mideleg_op2 | ||||||||||
| MEDELEG_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in medeleg or mideleg to see which bit positions hold a one. |
norm:medeleg_mideleg_warl | ||||||||||
| MIDELEG_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in medeleg or mideleg to see which bit positions hold a one. |
norm:medeleg_mideleg_warl | ||||||||||
| MIDELEG_RD1_LOWER_LEVEL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| may do so for lower-level interrupts | norm:mideleg_rd1_lower_level | ||||||||||
| MIP_BITS_WR_OR_RDONLY | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Each individual bit in register mip may be writable or may be read-only. | norm:mip_bits_wr_or_rdonly | ||||||||||
| MIP_MSIP_MAYBE_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then mip.MSIP and mie.MSIE may both be read-only zeros. |
norm:mip_msip_mie_msie_maybe_rdonly0 | ||||||||||
| MIE_MSIE_MAYBE_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then mip.MSIP and mie.MSIE may both be read-only zeros. |
norm:mip_msip_mie_msie_maybe_rdonly0 | ||||||||||
| MSIP_UPDATE_MAX_TIME | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| When the memory-mapped msip register changes, it is guaranteed to be reflected in mip.MSIP eventually, but not necessarily immediately. |
norm:msip_update_max_time | ||||||||||
| MCYCLE_SHARED | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mcycle CSR may be shared between harts on the same core, in which case writes to mcycle will be visible to those harts. |
norm:mcycle_shared | ||||||||||
| MHPMCOUNTER_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The mhpmcounters are WARL registers | norm:mhpmcounter_warl | ||||||||||
| MHPMCOUNTER_N_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| a legal implementation is to make both the counter and its corresponding event selector be read-only 0. | norm:mhpmcounter_mhpmevent_rdonly0 | ||||||||||
| MHPMCOUNTER_N_SZ | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| support up to 64 bits of precision on RV32 and RV64. | norm:mhpmcounter_sz | ||||||||||
| MHPMEVENT_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The event selector CSRs, mhpmevent3-mhpmevent31, are 64-bit WARL registers that control which event causes the corresponding counter to increment. |
norm:mhpmevent_sz_warl_op | ||||||||||
| MHPMEVENT_N_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| a legal implementation is to make both the counter and its corresponding event selector be read-only 0. | norm:mhpmcounter_mhpmevent_rdonly0 | ||||||||||
| MCOUNTEREN_FLDS_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| In harts with U-mode, the mcounteren must be implemented, but all fields are WARL |
norm:mcounteren_flds_mandatory_warl | ||||||||||
| MCOUNTEREN_CY_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||
| MCOUNTEREN_TM_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||
| MCOUNTEREN_IR_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||
| MCOUNTEREN_HPM_N_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode. |
norm:mcounteren_flds_rdonly0 | ||||||||||
| MCOUNTINHIBIT_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
norm:mcountinhibit_sz_warl_op1 | ||||||||||
| MEPC_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| mepc is a WARL register | norm:mepc_warl | ||||||||||
| MEPC_INV_ADDR_CONV | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Prior to writing mepc, implementations may convert an invalid address into some other invalid address that mepc is capable of holding. |
norm:mepc_inv_addr_conv | ||||||||||
| MCAUSE_EXCCODE_WLRL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WLRL | Implementation-defined behavior category | ||||||||||
| The Exception Code is a WLRL field, so is only guaranteed to hold supported exception codes. | norm:mcause_exccode_wlrl | ||||||||||
| MTVAL_PER_EXC_BEHAVIOR | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The hardware platform will specify which exceptions must set mtval informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception. |
norm:mtval_per_exc_behavior | ||||||||||
| MTVAL_RDONLY0 | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If the hardware platform specifies that no exceptions set mtval to a nonzero value, then mtval is read-only zero. |
norm:mtval_rdonly0 | ||||||||||
| MTVAL_VARLEN_WR | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If mtval is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then mtval will contain the virtual address of the portion of the instruction that caused the fault |
norm:mtval_varlen_wr | ||||||||||
| MTVAL_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| If mtval is not read-only zero, it is a WARL register | norm:mtval_warl | ||||||||||
| MTVAL_INV_ADDR_CONV | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Prior to writing mtval, implementations may convert an invalid address into some other invalid address that mtval is capable of holding. |
norm:mtval_inv_addr_conv | ||||||||||
| MCONFIGPTR_VAL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| it may be zero to indicate the configuration data structure does not exist or that an alternative mechanism must be used to locate it. |
norm:mconfigptr_val | ||||||||||
| MENVCFG_FIOM_RDONLY0_OK | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If S-mode is not supported, or if satp.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero. |
norm:menvcfg_fiom_rdonly0_ok | ||||||||||
| MENVCFG_CBIE_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to menvcfg to control execution of the cache block invalidate instruction (CBO.INVAL) in modes less privileged than M. When CBIE is set to 00b, the instruction raises an illegal-instruction exception in modes less privileged than M. |
norm:menvcfg_cbie_warl_op | ||||||||||
| MSECCFG_RLB_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| When mseccfg.RLB (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify Locked PMP rules. When mseccfg.RLB is 1, locked PMP rules may be removed or modified and locked PMP rules may be edited. When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset. | norm:mseccfg_rlb_op_warl | ||||||||||
| MSECCFG_MMWP_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The mseccfg.MMWP (Machine-Mode Allowlist Policy) is a WARL field. This field changes the default PMP policy for Machine mode when accessing memory regions that don’t have a matching PMP rule. This is a sticky bit, meaning that once set it cannot be unset until a PMP reset. When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching PMP rule, to denied instead of ignored. | norm:mseccfg_mmwp_op_warl | ||||||||||
| MSECCFG_MML_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The mseccfg.MML (Machine Mode Lockdown) is a WARL field. | norm:mseccfg_mml_warl | ||||||||||
| MSECCFG_PMM_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
|
norm:mseccfg_pmm_enc | ||||||||||
| MTIME_TICK_PERIOD | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| the platform must provide a mechanism for determining the period of an mtime tick. |
norm:mtime_tick_period | ||||||||||
| MRET_CLR_LR_RESV | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If the A extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to. |
norm:xret_clr_lr_resv | ||||||||||
| SRET_CLR_LR_RESV | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| If the A extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to. |
norm:xret_clr_lr_resv | ||||||||||
| WFI_OPT_U_MODE | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| optionally available to U-mode. | norm:wfi_opt_U_mode | ||||||||||
| WFI_RESUME_REASON | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Implementations are permitted to resume execution for any reason, even if an enabled interrupt has not become pending. Hence, a legal implementation is to simply implement the WFI instruction as a NOP. |
norm:wfi_resume_reason | ||||||||||
| MCAUSE_RST_VAL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The mcause register is set to a value indicating the cause of the reset. | norm:mcause_rst1_val | ||||||||||
| The mcause values after reset have implementation-specific interpretation |
norm:mcause_rst2_val | ||||||||||
| PMP_A_L_RST | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers’ A and L fields. |
norm:pmp_A_L_rst | ||||||||||
| WARL_RST | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| No WARL field contains an illegal value. | norm:warl_rst | ||||||||||
| MSECCFG_MML_MMWP_RLB_RST | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The MML, MMWP, and RLB fields of the mseccfg register are set to 0, unless the platform mandates a different reset value. |
norm:mseccfg_mml_mmwp_rlb_rst | ||||||||||
| MSECCFG_USEED_SSEED_RST | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The USEED and SSEED fields of the mseccfg CSR must have defined reset values. The system must not allow them to be in an undefined state after reset. |
norm:mseccfg_useed_sseed_rst | ||||||||||
| MCAUSE_RST_ALIAS_OK | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| mcause reset values may alias mcause values following synchronous exceptions |
norm:mcause_rst_alias_ok | ||||||||||
| PMA_MM_IFETCH | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| [CONTEXT] Main memory regions always support read and write of all access widths required by the attached devices |
norm:pma_mm_rw | ||||||||||
| can specify whether instruction fetch is supported. | norm:pma_mm_ifetch | ||||||||||
| PMA_CACHE_MM_ALL_ATOMICS | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Some platforms might mandate that all of cacheable main memory support all atomic operations |
norm:pma_cache_mm_all_atomics | ||||||||||
| PMA_MAG_OP_LDST | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| [CONTEXT] If a misaligned AMO accesses a region that does not specify a misaligned atomicity granule PMA, or if not all accessed bytes lie within the same misaligned atomicity granule, then an exception is raised. |
norm:pma_mag_op_amo | ||||||||||
| For regular loads and stores that access such a region or for which not all accessed bytes lie within the same atomicity granule, then either an exception is raised, or the access proceeds but is not guaranteed to be atomic. |
norm:pma_mag_op_ldst | ||||||||||
| PMA_MAG_EXC | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Implementations may raise access-fault exceptions instead of address-misaligned exceptions for some misaligned accesses, indicating the instruction should not be emulated by a trap handler. |
norm:pma_mag_exc | ||||||||||
| PMA_MO_DYN | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Systems might support dynamic configuration of ordering properties on each memory region. | norm:pma_mo_dyn | ||||||||||
| PMA_IDP_IMPLICIT_SZ | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| [CONTEXT] For non-idempotent regions, implicit reads and writes must not be performed early or speculatively, with the following exceptions. When a non-speculative implicit read is performed, an implementation is permitted to additionally read any of the bytes within a naturally aligned power-of-2 region containing the address of the non-speculative implicit read. Furthermore, when a non-speculative instruction fetch is performed, an implementation is permitted to additionally read any of the bytes within the next naturally aligned power-of-2 region of the same size (with the address of the region taken modulo 2XLEN). |
norm:pma_idp_implicit_ok | ||||||||||
| The size of these naturally aligned power-of-2 regions is implementation-defined, but, for systems with page-based virtual memory, must not exceed the smallest supported page size. |
norm:pma_idp_implicit_sz | ||||||||||
| CRITICAL_ERROR | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The actions performed by the platform when a hart asserts a critical-error signal are platform-specific. The range of possible actions include restarting the affected hart or restarting the entire platform, among others. |
norm:critical_error | ||||||||||
| NMI_MCAUSE_VAL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| mcause is set to a value indicating the source of the NMI. |
norm:nmi_mcause_val1 | ||||||||||
| The values written to mcause on an NMI are implementation-defined. | norm:nmi_mcause_val2 | ||||||||||
| SXLEN | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively. | norm:sxlen_uxlen | ||||||||||
| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | ||||||||||
| UXLEN | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively. | norm:sxlen_uxlen | ||||||||||
| When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. | norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32 | ||||||||||
| XLEN_REDUCTION_HINT_OP | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., c.addi x8, 0. When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits MXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1. | norm:xlen_reduction_hint_op1 | ||||||||||
| This definition allows implementations to elide register write-back for some HINTs, while allowing them to execute other HINTs in the same manner as other integer computational instructions. The implementation choice is observable only by privilege modes with an XLEN setting greater than the current XLEN; it is invisible to the current privilege mode. |
norm:xlen_reduction_hint_op2 | ||||||||||
| RST_ADDR | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Reset and NMI vector locations are given in a platform specification. | norm:rst_and_nmi_addr | ||||||||||
| NMI_ADDR | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| Reset and NMI vector locations are given in a platform specification. | norm:rst_and_nmi_addr | ||||||||||
| PMP_GRANULARITY | Minimum PMP region granularity supported by the platform | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Sm | Rule's "instance" property | ||||||||||
| The granularity of PMP access control settings are platform-specific, but the standard PMP encoding supports regions as small as four bytes. |
norm:pmp_granularity | ||||||||||
| PMP_ENTRY_COUNT | PMP supports up to 64 entries with allowed implementation counts and ordering rules | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Sm | Rule's "instance" property | ||||||||||
| Up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first. |
norm:pmp_entry_count | ||||||||||
| PMP_CSRS_WARL_ACCESS | PMP CSRs are WARL, may read as zero, and are accessible only in M-mode | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| All PMP CSR fields are WARL and may be read-only zero. |
norm:pmp_csrs_warl_access | ||||||||||
| PMP_ADDR_WARL | PMP address registers are WARL due to optional physical address bits | Rule's "summary" property | |||||||||
| extension | Rule's "kind" property | ||||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| Not all physical address bits may be implemented, and so the pmpaddr registers are WARL. |
norm:pmp_addr_warl | ||||||||||
| PMP_RWX_WARL | extension | Rule's "kind" property | |||||||||
| Sm | Rule's "instance" property | ||||||||||
| WARL | Implementation-defined behavior category | ||||||||||
| The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved. |
norm:pmp_rwx_warl |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| ENDIANNESS | base | Rule's "kind" property |
| Any | Rule's "instance" property | |
| The EEI will define whether the memory system is little-endian or big-endian. | norm:ENDIANNESS | |
| MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| Loads and stores whose effective address is not naturally aligned to the referenced datatype (i.e., the effective address is not divisible by the size of the access in bytes) have behavior dependent on the EEI. |
norm:misaligned_ldst_eei_dependent_behavior | |
| MISALIGNED_LDST_HW_SUPPORT | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| misaligned loads and stores can be handled in hardware, or via an invisible trap into the execution environment implementation, or possibly a combination of hardware and invisible trap depending on address. |
norm:misaligned_ldst_hw_support | |
| MISALIGNED_LDST_EXC_TYPE | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| loads and stores that are not naturally aligned may either complete execution successfully or raise an exception. The exception raised can be either an address-misaligned exception or an access-fault exception. For a memory access that would otherwise be able to complete except for the misalignment, an access-fault exception can be raised instead of an address-misaligned exception if the misaligned access should not be emulated, e.g., if accesses to the memory region have side effects. |
norm:misaligned_ldst_exc_type | |
| MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP | base | Rule's "kind" property |
| RV32I | Rule's "instance" property | |
| When an EEI does not guarantee misaligned loads and stores are handled invisibly, the EEI must define if exceptions caused by address misalignment result in a contained trap (allowing software running inside the execution environment to handle the trap) or a fatal trap (terminating execution). |
norm:misaligned_ldst_contained_or_fatal_trap |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| SCTRDEPTH_DEPTH | WARL field encoding CTR buffer depth (16–256, reserved encodings). | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| WARL field that selects the depth of the CTR buffer. | norm:sctrdepth_depth_op0 | |
| The depth of the CTR buffer dictates the number of entries to which the hardware records transfers. For a depth of N, the hardware records transfers to entries 0..N-1. All Entry Registers read as '0' and are read-only when the selected entry is in the range N to 255. When the depth is increased, the newly accessible entries contain unspecified but legal values. | norm:sctrdepth_depth_op1 | |
| It is implementation-specific which DEPTH value(s) are supported. | norm:sctrdepth_depth | |
| SCTRDEPTH_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| WARL field that selects the depth of the CTR buffer. | norm:sctrdepth_depth_op0 | |
| SCTRSTATUS_WRPTR_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| WARL field that indicates the physical CTR buffer entry to be written next. It is incremented after new transfers are recorded (see Behavior), though there are exceptions when xctrctl.RASEMU=1, see RAS (Return Address Stack) Emulation Mode. For a given CTR depth (where depth = 2(DEPTH+4)), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0. Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0. On depth changes, WRPTR holds an unspecified but legal value. | norm:sctrstatus_wrptr | |
| CTRSOURCE_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| ctrsource is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended. | norm:Ssctr_ctrsource_sz_acc_op | |
| CTRTARGET_WARL | extension | Rule's "kind" property |
| Smctr | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| ctrtarget is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a pc. It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding. When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended. | norm:ctrtarget_sz_acc | |
| CTRDATA_CC_SUPPORTED | ctrdata register may optionally include a count of CPU cycles | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| The ctrdata register may optionally include a count of CPU cycles elapsed since the prior CTR record. The elapsed cycle count value is represented by the CC field, which has a 12-bit mantissa component (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE). | norm:ctrdata_cc_supported | |
| CTR_CCOUNTER_IMPL | Implementation can support 0 to 4 exponent bits | Rule's "summary" property |
| extension | Rule's "kind" property | |
| Smctr | Rule's "instance" property | |
| An implementation that supports cycle counting must implement CCV and all CCM bits, but may implement 0..4 exponent bits in CCE. Unimplemented CCE bits are read-only 0. For implementations that support transfer type filtering, it is recommended to implement at least 3 exponent bits. This allows capturing the full latency of most functions, when recording only calls and returns. |
norm:ctr_ccounter_impl |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| MNEPC_WARL | extension | Rule's "kind" property |
| Smrnmi | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| mnepc is a WARL register that must be able to hold all valid virtual addresses. |
norm:mnepc_warl | |
| MNCAUSE_WARL | extension | Rule's "kind" property |
| Smrnmi | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:mncause_img | |
| MNSTATUS_WARL | extension | Rule's "kind" property |
| Smrnmi | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:mnstatus_img |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| STATEEN_WARL_ACCESS | extension | Rule's "kind" property |
| Smstateen | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| Each standard-defined bit of a stateen CSR is WARL and may be read-only zero or one, subject to the following conditions. | norm:stateen_warl_access |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| SSTATUS_UXL_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| When SXLEN=32, the UXL field does not exist, and UXLEN=32. When SXLEN=64, it is a WARL field that encodes the current value of UXLEN. In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN. | norm:sstatus_uxl_sz | |
| HINT_SXLEN | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., c.addi x8, 0. When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits SXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1. | norm:hint_sxlen | |
| SSTATUS_UBE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| The UBE bit is a WARL field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode. An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode. | norm:sstatus_ube | |
| SSTATUS_SDT_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| The S-mode-disable-trap (SDT) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M. | norm:sstatus_sdt | |
| STVEC_MODE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:stvec_img | |
| STVEC_BASE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| (No text available) | norm:stvec_img | |
| SEI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| STI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| SSI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| LCOFI_INTR_IMPL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. |
norm:std_super_intr_impl | |
| SIP_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| All bits in sip and sie are WARL fields. The implemented interrupts may be found by writing one to every bit location in sie, then reading back to see which bit positions hold a one. |
norm:sip_sie_warl | |
| SIE_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| All bits in sip and sie are WARL fields. The implemented interrupts may be found by writing one to every bit location in sie, then reading back to see which bit positions hold a one. |
norm:sip_sie_warl | |
| SCOUNTEREN_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| scounteren must be implemented. However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when executing in U-mode. Hence, they are effectively WARL fields. | norm:scounteren_acc | |
| SEPC_ACC_INVALID_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| sepc is a WARL register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid addresses. Prior to writing sepc, implementations may convert an invalid address into some other invalid address that sepc is capable of holding. | norm:sepc_acc_invalid_addr | |
| SCAUSE_EXCEPTION_CODE_ACC | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WLRL | Implementation-defined behavior category | |
| The Exception Code is a WLRL field. |
norm:scause_exception_code_acc | |
| STVAL_WARL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| stval is a WARL register that must be able to hold all valid virtual addresses and the value 0. It need not be capable of holding all possible invalid addresses. Prior to writing stval, implementations may convert an invalid address into some other invalid address that stval is capable of holding. If the feature to return the faulting instruction bits is implemented, stval must also be able to hold all values less than 2N, where N is the smaller of SXLEN and ILEN. | norm:stval_acc | |
| ASIDLEN | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| The number of ASID bits is UNSPECIFIED and may be zero. The number of implemented ASID bits, termed ASIDLEN, may be determined by writing one to every bit position in the ASID field, then reading back the value in satp to see which bit positions in the ASID field hold a one. The least-significant bits of ASID are implemented first: that is, if ASIDLEN > 0, ASID[ASIDLEN-1:0] is writable. The maximal value of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57. | norm:asidlen | |
| SATP_MODE_ROZ_SFENCE_ILLEGAL | extension | Rule's "kind" property |
| S | Rule's "instance" property | |
| For implementations that make satp.MODE read-only zero (always Bare), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception. | norm:satp_mode_roz_sfence_illegal | |
| SENVCFG_CBIE_WARL | extension | Rule's "kind" property |
| Zicboz | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| The Zicbom extension adds the CBIE (Cache Block Invalidate instruction Enable) WARL field to senvcfg to control execution of the CBO.INVAL instruction in U-mode. The encoding 10b is reserved. When the Zicbom extension is not implemented, CBIE is read-only zero. Execution of CBO.INVAL in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and CBIE is set to 01b or 11b; otherwise, an illegal-instruction exception is raised. | norm:senvcfg_cbie |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| ELEN | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| The maximum size in bits of a vector element that any operation can produce or consume, ELEN {ge} 8, which must be a power of 2. |
norm:elen | |
| VLEN | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| The number of bits in a single vector register, VLEN {ge} ELEN, which must be a power of 2, and must be no greater than 216. | norm:vlen | |
| HW_MSTATUS_VS_DIRTY_UPDATE | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementations may also change mstatus.VS or vsstatus.VS from Initial or Clean to Dirty at any time, even when there is no change in vector state. |
norm:hw_mstatus_vs_dirty_update | |
| RESERVED_VILL_SET | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| [CONTEXT] Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if vill was 1 beforehand. | norm:vtype_vset_rsv | |
| Implementations may set vill in either case. | norm:reserved_vill_set | |
| MUTABLE_MISA_V | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementations may have a writable misa.V field. | norm:mutable_misa_v | |
| MSTATUS_VS_EXISTS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Analogous to the way in which the floating-point unit is handled, the mstatus.VS field may exist even if misa.V is clear. |
norm:mstatus_vs_exists | |
| VSSTATUS_VS_EXISTS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| For implementations with a writable misa.V field, the vsstatus.VS field may exist even if misa.V is clear. | norm:vsstatus_vs_exists | |
| VECTOR_LS_VSTART | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| All vector loads and stores may generate and accept a non-zero vstart value. | norm:vector_ls_vstart | |
| VECTOR_LS_CONSTANT_STRIDE_X0 | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| When rs2=x0, then an implementation is allowed, but not required, to perform fewer memory operations than the number of active elements, and may perform different numbers of memory operations across different dynamic executions of the same static instruction. | norm:vector_ls_constant_stride_x0 | |
| VECTOR_LS_OVERWRITE_PAST_TRAP | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported. |
norm:vector_ls_overwrite_past_trap | |
| VECTOR_FF_PAST_TRAP | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming of the vector length (but not past the original vector length). The values of these spurious updates do not have to correspond to the values in memory at the addressed memory locations. Non-idempotent memory locations can only be accessed when it is known the corresponding element load operation will not be restarted due to a trap or vector-length trimming. | norm:vector_ff_past_trap | |
| VECTOR_LS_SEG_PARTIAL_ACCESS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| If a trap occurs during access to a segment, it is implementation-defined whether a subset of the faulting segment's accesses are performed before the trap is taken. |
norm:vector_ls_seg_partial_access | |
| VECTOR_FF_SEG_PARTIAL_ACCESS | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| [CONTEXT] For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken. If an exception is detected partway through accessing a subsequent segment, vl is reduced to the index of that segment. | norm:vector_ls__seg_ff_unit-stride_op | |
| In both cases, it is implementation-defined whether a subset of the segment is loaded. | norm:vector_ff_seg_partial_access | |
| VECTOR_LS_SEG_FF_OVERLOAD | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| These instructions may overwrite destination vector register group elements past the point at which a trap is reported or past the point at which vector length is trimmed. | norm:vector_ls_seg_ff_overload | |
| VECTOR_LS_WHOLEREG_MISSALIGNED_EXCEPTION | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation’s smallest supported SEW size in bytes (SEWMIN/8). | norm:vector_ls_wholereg_missaligned_exception | |
| VECTOR_LS_MISSALIGNED_EXCEPTION | extension | Rule's "kind" property |
| V | Rule's "instance" property | |
| If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address-misaligned exception is raised on that element. | norm:vector_ls_missaligned_exception |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| INTERRUPTS_ALLOWED_IN_PUSHPOP | extension | Rule's "kind" property |
| Zcmp | Rule's "instance" property | |
| It is implementation defined whether interrupts can also be taken during the sequence execution. | norm:interrupts_allowed_in_pushpop | |
| JVT_WARL | extension | Rule's "kind" property |
| Zcmt | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| The jvt register is an XLEN-bit WARL read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE). | norm:jvt_reg | |
| JVT_MODE_WARL | extension | Rule's "kind" property |
| Zcmt | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| jvt.mode is a WARL field, so can only be programmed to modes which are implemented. | norm:jvt_mode_acc |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| ZICSR_WLRL_EXCEPTION | extension | Rule's "kind" property |
| Zicsr | Rule's "instance" property | |
| Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a WLRL field. |
norm:Zicsr_wlrl_exception | |
| ZICSR_WARL | extension | Rule's "kind" property |
| Zicsr | Rule's "instance" property | |
| WARL | Implementation-defined behavior category | |
| Implementations will not raise an exception on writes of unsupported values to a WARL field. |
norm:Zicsr_warl |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| NTL_TRAP_BEHAVIOR | In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler. Instead, implementations are recommended to ignore the HINT in this case. |
Rule's "summary" property |
| extension | Rule's "kind" property | |
| Zihintntl | Rule's "instance" property | |
| In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler. Instead, implementations are recommended to ignore the HINT in this case. |
norm:NTL_trap_behavior |
| Rule Name | Rule Description | Origin of Description |
|---|---|---|
| ZILSD_ALIGN8_ATOMIC | extension | Rule's "kind" property |
| Zilsd | Rule's "instance" property | |
| Even if naturally aligned, the memory access might not be performed atomically. | norm:Zilsd_align8_atomic |